From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Thu, 9 Jun 2016 21:20:54 +0000 (-0700)
Subject: Trap on tdrdata registers when tdrselect[XLEN-1]=0
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f5ecf65e5e2c6e60355933b8a2aca230e8443ff5;p=riscv-isa-sim.git

Trap on tdrdata registers when tdrselect[XLEN-1]=0
---

diff --git a/riscv/processor.cc b/riscv/processor.cc
index ed9a83b..dac5d5b 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -483,9 +483,6 @@ reg_t processor_t::get_csr(int which)
     case CSR_MEDELEG: return state.medeleg;
     case CSR_MIDELEG: return state.mideleg;
     case CSR_TDRSELECT: return 0;
-    case CSR_TDRDATA1: return 0;
-    case CSR_TDRDATA2: return 0;
-    case CSR_TDRDATA3: return 0;
     case CSR_DCSR:
       {
         uint32_t v = 0;