From: Andrew Waterman <waterman@s144.Millennium.Berkeley.EDU>
Date: Wed, 13 Apr 2011 01:22:07 +0000 (-0700)
Subject: [xcc,sim] fixed RM field
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f5f9ed0a0d40680acb24d6a1c4fdb992e0277f67;p=riscv-isa-sim.git

[xcc,sim] fixed RM field
---

diff --git a/riscv/decode.h b/riscv/decode.h
index af6b57f..e6d0e8a 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -182,8 +182,10 @@ private:
 #define TARGET insn.jtype.target
 #define BRANCH_TARGET (pc + (BIMM << BRANCH_ALIGN_BITS))
 #define JUMP_TARGET (pc + (TARGET << JUMP_ALIGN_BITS))
-#define RM ((insn.ftype.rm != 7) ? insn.ftype.rm : \
-            ((fsr & FSR_RD) >> FSR_RD_SHIFT))
+#define RM ({ int rm = insn.ftype.rm; \
+              if(rm == 7) rm = (fsr & FSR_RD) >> FSR_RD_SHIFT; \
+              if(rm > 4) throw trap_illegal_instruction; \
+              rm; })
 
 #define require_supervisor if(!(sr & SR_S)) throw trap_privileged_instruction
 #define xpr64 (xprlen == 64)