From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 10 Jun 2020 12:33:19 +0000 (+0100)
Subject: code-morph ALU output test check phase
X-Git-Tag: div_pipeline~430
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f614b3fa1d31d8c8cbc2da8b7494b6adb96e895d;p=soc.git

code-morph ALU output test check phase
---

diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py
index 400afc98..c6378859 100644
--- a/src/soc/fu/alu/test/test_pipe_caller.py
+++ b/src/soc/fu/alu/test/test_pipe_caller.py
@@ -257,24 +257,24 @@ class TestRunner(FHDLTestCase):
                         yield
                         vld = yield alu.n.valid_o
                     yield
-                    alu_out = yield alu.n.data_o.o.data
-                    out_reg_valid = yield pdecode2.e.write_reg.ok
-                    if out_reg_valid:
-                        write_reg_idx = yield pdecode2.e.write_reg.data
-                        expected = sim.gpr(write_reg_idx).value
-                        print(f"expected {expected:x}, actual: {alu_out:x}")
-                        self.assertEqual(expected, alu_out, code)
-                    yield from self.check_extra_alu_outputs(alu, pdecode2,
-                                                            sim, code)
+
+                    yield from self.check_alu_outputs(alu, pdecode2, sim, code)
 
         sim.add_sync_process(process)
         with sim.write_vcd("alu_simulator.vcd", "simulator.gtkw",
                             traces=[]):
             sim.run()
 
-    def check_extra_alu_outputs(self, alu, dec2, sim, code):
+    def check_alu_outputs(self, alu, dec2, sim, code):
+        sim_o = {}
+        res = {}
+
+        # check RT
+        yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
+        yield from ALUHelpers.get_int_o(res, alu, dec2)
+        ALUHelpers.check_int_o(self, res, sim_o, code)
+
         rc = yield dec2.e.rc.data
-        op = yield dec2.e.insn_type
         cridx_ok = yield dec2.e.write_cr.ok
         cridx = yield dec2.e.write_cr.data
 
@@ -282,11 +282,9 @@ class TestRunner(FHDLTestCase):
         if rc:
             self.assertEqual(cridx, 0, code)
 
-        if cridx_ok:
-            cr_expected = sim.crl[cridx].get_range().value
-            cr_actual = yield alu.n.data_o.cr0.data
-            print ("CR", cridx, cr_expected, cr_actual)
-            self.assertEqual(cr_expected, cr_actual, "CR%d %s" % (cridx, code))
+        yield from ALUHelpers.get_sim_cr_a(sim_o, sim, dec2)
+        yield from ALUHelpers.get_cr_a(res, alu, dec2)
+        ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))
 
         cry_out = yield dec2.e.output_carry
         if cry_out:
diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py
index e373a708..997f022b 100644
--- a/src/soc/fu/test/common.py
+++ b/src/soc/fu/test/common.py
@@ -83,9 +83,38 @@ class ALUHelpers:
             yield alu.p.data_i.full_cr.eq(0)
 
     def get_int_o(res, alu, dec2):
-        out_reg_valid = yield pdecode2.e.write_reg.ok
+        out_reg_valid = yield dec2.e.write_reg.ok
         if out_reg_valid:
             res['o'] = yield alu.n.data_o.o.data 
 
-    def check_int_o(dut, alu, sim, dec2):
-        pass
+    def get_cr_a(res, alu, dec2):
+        cridx_ok = yield dec2.e.write_cr.ok
+        if cridx_ok:
+            res['cr_a'] = yield alu.n.data_o.cr0.data
+
+    def get_sim_int_o(res, sim, dec2):
+        out_reg_valid = yield dec2.e.write_reg.ok
+        if out_reg_valid:
+            write_reg_idx = yield dec2.e.write_reg.data
+            res['o'] = sim.gpr(write_reg_idx).value
+
+    def get_sim_cr_a(res, sim, dec2):
+        cridx_ok = yield dec2.e.write_cr.ok
+        if cridx_ok:
+            cridx = yield dec2.e.write_cr.data
+            res['cr_a'] = sim.crl[cridx].get_range().value
+
+    def check_int_o(dut, res, sim_o, msg):
+        if 'o' in res:
+            expected = sim_o['o']
+            alu_out = res['o']
+            print(f"expected {expected:x}, actual: {alu_out:x}")
+            dut.assertEqual(expected, alu_out, msg)
+
+    def check_cr_a(dut, res, sim_o, msg):
+        if 'cr_a' in res:
+            cr_expected = sim_o['cr_a']
+            cr_actual = res['cr_a']
+            print ("CR", cr_expected, cr_actual)
+            dut.assertEqual(cr_expected, cr_actual, msg)
+