From: lkcl <lkcl@web>
Date: Thu, 9 Sep 2021 11:19:23 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~175
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f61e854ad63b82fcc3bd451d26927123b910adb3;p=libreriscv.git

---

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index 3a6919033..0944e9e61 100644
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -1,5 +1,9 @@
 # Condition Register SVP64 Operations
 
+Links:
+
+* <https://bugs.libre-soc.org/show_bug.cgi?id=687>
+
 Condition Register Fields are only 4 bits wide: this presents some
 interesting conceptual challenges for SVP64, particularly with respect to element
 width (which is clearly meaningless for a 4-bit