From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 30 Sep 2019 04:55:53 +0000 (-0700)
Subject: Missing endmodule
X-Git-Tag: working-ls180~881^2^2~201
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f6203e6bd65f7383f14a15e926fc4b8f5f9a3edf;p=yosys.git

Missing endmodule
---

diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v
index b302e46f6..8255804c2 100644
--- a/techlibs/xilinx/abc_model.v
+++ b/techlibs/xilinx/abc_model.v
@@ -35,6 +35,7 @@ endmodule
 
 (* abc_box_id = 1000 *)
 module \$__ABC_ASYNC (input A, S, output Y);
+endmodule
 
 // Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
 //   Necessary since RAMD* and SRL* have both combinatorial (i.e.