From: lkcl <lkcl@web>
Date: Wed, 8 Sep 2021 00:26:15 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~187
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f621254830d10825377bb7b1b567a40a36706993;p=libreriscv.git

---

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index 7e86257e4..601a9bb28 100644
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -9,7 +9,8 @@ has no meaning. Consequently an alternative Mode Format is required.
 This alternative mapping **only** applies to instructions that **only**
 reference a CR Field or CR bit as the sole exclusive result. This section
 **does not** apply to instructions which primarily produce arithmetic
-results that also produce a CR Field (such as when Rc=1).
+results that also, as an aside, produce a corresponding
+CR Field (such as when Rc=1).
 Instructions that involve Rc=1 are definitively arithmetic in nature,
 where the corresponding Condition Register Field can be considered to
 be a "co-result". Thus, if the arithmetic result is Vectorised, so