From: Nathan Binkert <binkertn@umich.edu>
Date: Fri, 21 May 2004 17:58:39 +0000 (-0400)
Subject: add a few statistics events
X-Git-Tag: m5_1.0_beta2~22
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f622d74f81f6d0c451bc8437d19a38057bc0d164;p=gem5.git

add a few statistics events

arch/alpha/ev5.cc:
    Add an event for faults
cpu/simple_cpu/simple_cpu.cc:
    add events for uncached reads/writes

--HG--
extra : convert_revision : 747bdf12761e2de6ebbf54fecc9e0b71915b3a02
---

diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index f037a34ac..96d54c54c 100644
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -1,15 +1,14 @@
 /* $Id$ */
 
-#include "targetarch/alpha_memory.hh"
-#ifdef DEBUG
-#include "sim/debug.hh"
-#endif
+#include "arch/alpha/alpha_memory.hh"
+#include "arch/alpha/isa_traits.hh"
+#include "arch/alpha/osfpal.hh"
+#include "base/kgdb.h"
+#include "base/remote_gdb.hh"
+#include "base/stats/events.hh"
 #include "cpu/exec_context.hh"
+#include "sim/debug.hh"
 #include "sim/sim_events.hh"
-#include "targetarch/isa_traits.hh"
-#include "base/remote_gdb.hh"
-#include "base/kgdb.h"	// for ALPHA_KENTRY_IF
-#include "targetarch/osfpal.hh"
 
 #ifdef FULL_SYSTEM
 
@@ -102,6 +101,8 @@ AlphaISA::initIPRs(RegFile *regs)
 void
 ExecContext::ev5_trap(Fault fault)
 {
+    Stats::recordEvent(csprintf("Fault %s", FaultName(fault)));
+
     assert(!misspeculating());
     kernelStats.fault(fault);
 
diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc
index 765507345..1ade235ed 100644
--- a/cpu/simple_cpu/simple_cpu.cc
+++ b/cpu/simple_cpu/simple_cpu.cc
@@ -42,6 +42,7 @@
 #include "base/pollevent.hh"
 #include "base/range.hh"
 #include "base/trace.hh"
+#include "base/stats/events.hh"
 #include "cpu/base_cpu.hh"
 #include "cpu/exec_context.hh"
 #include "cpu/exetrace.hh"
@@ -402,6 +403,9 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
         }
     }
 
+    if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
+        Stats::recordEvent("Uncached Read");
+
     return fault;
 }
 
@@ -487,6 +491,9 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
     if (res && (fault == No_Fault))
         *res = memReq->result;
 
+    if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
+        Stats::recordEvent("Uncached Write");
+
     return fault;
 }