From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 13 Nov 2020 17:48:28 +0000 (+0000)
Subject: fix clk_sel width (2 not 3)
X-Git-Tag: partial-core-ls180-gdsii~11
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f62336a0d6d274067596bb2727da917f174566bd;p=soclayout.git

fix clk_sel width (2 not 3)
---

diff --git a/experiments9/non_generated/full_core_ls180.il b/experiments9/non_generated/full_core_ls180.il
index 2b897fa..cabbad1 100644
--- a/experiments9/non_generated/full_core_ls180.il
+++ b/experiments9/non_generated/full_core_ls180.il
@@ -72483,7 +72483,7 @@ module \ls180
   wire $0\builder_sync_rhs_array_muxed5[0:0]
   attribute \src "ls180.v:7184.1-7200.4"
   wire $0\builder_sync_rhs_array_muxed6[0:0]
-  attribute \src "ls180.v:140.11-140.24"
+  attribute \src "ls180.v:154.11-154.24"
   wire width 3 $0\eint_1[2:0]
   attribute \src "ls180.v:7431.1-10055.4"
   wire $0\main_cmd_consumed[0:0]
@@ -72627,17 +72627,17 @@ module \ls180
   wire $0\main_libresocsim_interface2_converted_interface_stb[0:0]
   attribute \src "ls180.v:2910.1-2956.4"
   wire $0\main_libresocsim_interface2_converted_interface_we[0:0]
-  attribute \src "ls180.v:133.12-133.74"
+  attribute \src "ls180.v:155.12-155.74"
   wire width 16 $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0]
-  attribute \src "ls180.v:159.5-159.69"
+  attribute \src "ls180.v:130.5-130.69"
   wire $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0]
-  attribute \src "ls180.v:137.5-137.72"
+  attribute \src "ls180.v:134.5-134.72"
   wire $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0]
-  attribute \src "ls180.v:147.12-147.78"
+  attribute \src "ls180.v:143.12-143.78"
   wire width 16 $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0]
-  attribute \src "ls180.v:132.5-132.74"
+  attribute \src "ls180.v:141.5-141.74"
   wire $0\main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso[0:0]
-  attribute \src "ls180.v:145.5-145.74"
+  attribute \src "ls180.v:161.5-161.74"
   wire $0\main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso[0:0]
   attribute \src "ls180.v:2850.1-2896.4"
   wire $0\main_libresocsim_libresoc_dbus_ack[0:0]
@@ -82727,24 +82727,24 @@ module \ls180
   wire \builder_sync_rhs_array_muxed6
   attribute \src "ls180.v:1898.6-1898.18"
   wire \builder_wait
-  attribute \src "ls180.v:19.20-19.24"
-  wire width 3 output 15 \eint
-  attribute \src "ls180.v:140.11-140.17"
+  attribute \src "ls180.v:35.20-35.24"
+  wire width 3 output 31 \eint
+  attribute \src "ls180.v:154.11-154.17"
   wire width 3 \eint_1
-  attribute \src "ls180.v:9.21-9.27"
-  wire width 16 output 5 \gpio_i
-  attribute \src "ls180.v:10.21-10.27"
-  wire width 16 output 6 \gpio_o
-  attribute \src "ls180.v:11.21-11.28"
-  wire width 16 output 7 \gpio_oe
-  attribute \src "ls180.v:39.14-39.21"
-  wire output 35 \i2c_scl
-  attribute \src "ls180.v:40.14-40.23"
-  wire output 36 \i2c_sda_i
-  attribute \src "ls180.v:41.14-41.23"
-  wire output 37 \i2c_sda_o
-  attribute \src "ls180.v:42.14-42.24"
-  wire output 38 \i2c_sda_oe
+  attribute \src "ls180.v:36.21-36.27"
+  wire width 16 output 32 \gpio_i
+  attribute \src "ls180.v:37.21-37.27"
+  wire width 16 output 33 \gpio_o
+  attribute \src "ls180.v:38.21-38.28"
+  wire width 16 output 34 \gpio_oe
+  attribute \src "ls180.v:5.14-5.21"
+  wire output 1 \i2c_scl
+  attribute \src "ls180.v:6.14-6.23"
+  wire output 2 \i2c_sda_i
+  attribute \src "ls180.v:7.14-7.23"
+  wire output 3 \i2c_sda_o
+  attribute \src "ls180.v:8.14-8.24"
+  wire output 4 \i2c_sda_oe
   attribute \src "ls180.v:49.13-49.21"
   wire input 45 \jtag_tck
   attribute \src "ls180.v:50.13-50.21"
@@ -83036,66 +83036,66 @@ module \ls180
   attribute \src "ls180.v:125.13-125.39"
   wire width 64 \main_libresocsim_libresoc2
   attribute \src "ls180.v:127.12-127.45"
-  wire width 3 \main_libresocsim_libresoc_clk_sel
-  attribute \src "ls180.v:133.12-133.66"
+  wire width 2 \main_libresocsim_libresoc_clk_sel
+  attribute \src "ls180.v:155.12-155.66"
   wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_i
-  attribute \src "ls180.v:134.13-134.67"
+  attribute \src "ls180.v:156.13-156.67"
   wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_o
-  attribute \src "ls180.v:135.13-135.68"
+  attribute \src "ls180.v:157.13-157.68"
   wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe
-  attribute \src "ls180.v:158.6-158.61"
+  attribute \src "ls180.v:129.6-129.61"
   wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl
-  attribute \src "ls180.v:159.5-159.62"
+  attribute \src "ls180.v:130.5-130.62"
   wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i
-  attribute \src "ls180.v:160.6-160.63"
+  attribute \src "ls180.v:131.6-131.63"
   wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o
-  attribute \src "ls180.v:161.6-161.64"
+  attribute \src "ls180.v:132.6-132.64"
   wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe
-  attribute \src "ls180.v:136.6-136.64"
+  attribute \src "ls180.v:133.6-133.64"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk
-  attribute \src "ls180.v:137.5-137.65"
+  attribute \src "ls180.v:134.5-134.65"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i
-  attribute \src "ls180.v:138.6-138.66"
+  attribute \src "ls180.v:135.6-135.66"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o
-  attribute \src "ls180.v:139.6-139.67"
+  attribute \src "ls180.v:136.6-136.67"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe
-  attribute \src "ls180.v:146.13-146.68"
+  attribute \src "ls180.v:142.13-142.68"
   wire width 13 \main_libresocsim_libresoc_constraintmanager_obj_sdram_a
-  attribute \src "ls180.v:155.12-155.68"
+  attribute \src "ls180.v:151.12-151.68"
   wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba
-  attribute \src "ls180.v:152.6-152.65"
+  attribute \src "ls180.v:148.6-148.65"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n
-  attribute \src "ls180.v:154.6-154.63"
+  attribute \src "ls180.v:150.6-150.63"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke
-  attribute \src "ls180.v:153.6-153.64"
+  attribute \src "ls180.v:149.6-149.64"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n
-  attribute \src "ls180.v:156.12-156.68"
+  attribute \src "ls180.v:152.12-152.68"
   wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm
-  attribute \src "ls180.v:147.12-147.70"
+  attribute \src "ls180.v:143.12-143.70"
   wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i
-  attribute \src "ls180.v:148.13-148.71"
+  attribute \src "ls180.v:144.13-144.71"
   wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o
-  attribute \src "ls180.v:149.6-149.65"
+  attribute \src "ls180.v:145.6-145.65"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
-  attribute \src "ls180.v:151.6-151.65"
+  attribute \src "ls180.v:147.6-147.65"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n
-  attribute \src "ls180.v:150.6-150.64"
+  attribute \src "ls180.v:146.6-146.64"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n
-  attribute \src "ls180.v:129.6-129.67"
+  attribute \src "ls180.v:138.6-138.67"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk
-  attribute \src "ls180.v:131.6-131.68"
+  attribute \src "ls180.v:140.6-140.68"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n
-  attribute \src "ls180.v:132.5-132.67"
+  attribute \src "ls180.v:141.5-141.67"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso
-  attribute \src "ls180.v:130.6-130.68"
+  attribute \src "ls180.v:139.6-139.68"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi
-  attribute \src "ls180.v:142.6-142.67"
+  attribute \src "ls180.v:158.6-158.67"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk
-  attribute \src "ls180.v:144.6-144.68"
+  attribute \src "ls180.v:160.6-160.68"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n
-  attribute \src "ls180.v:145.5-145.67"
+  attribute \src "ls180.v:161.5-161.67"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso
-  attribute \src "ls180.v:143.6-143.68"
+  attribute \src "ls180.v:159.6-159.68"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi
   attribute \src "ls180.v:72.5-72.39"
   wire \main_libresocsim_libresoc_dbus_ack
@@ -86273,50 +86273,50 @@ module \ls180
   wire width 36 input 48 \nc
   attribute \src "ls180.v:251.6-251.13"
   wire \por_clk
-  attribute \src "ls180.v:22.19-22.22"
-  wire width 2 output 18 \pwm
-  attribute \src "ls180.v:141.12-141.17"
+  attribute \src "ls180.v:18.19-18.22"
+  wire width 2 output 14 \pwm
+  attribute \src "ls180.v:137.12-137.17"
   wire width 2 \pwm_1
-  attribute \src "ls180.v:12.13-12.23"
-  wire output 8 \sdcard_clk
-  attribute \src "ls180.v:13.14-13.26"
-  wire output 9 \sdcard_cmd_i
-  attribute \src "ls180.v:14.13-14.25"
-  wire output 10 \sdcard_cmd_o
-  attribute \src "ls180.v:15.13-15.26"
-  wire output 11 \sdcard_cmd_oe
+  attribute \src "ls180.v:11.13-11.23"
+  wire output 7 \sdcard_clk
+  attribute \src "ls180.v:12.14-12.26"
+  wire output 8 \sdcard_cmd_i
+  attribute \src "ls180.v:13.13-13.25"
+  wire output 9 \sdcard_cmd_o
+  attribute \src "ls180.v:14.13-14.26"
+  wire output 10 \sdcard_cmd_oe
+  attribute \src "ls180.v:15.19-15.32"
+  wire width 4 input 11 \sdcard_data_i
   attribute \src "ls180.v:16.19-16.32"
-  wire width 4 input 12 \sdcard_data_i
-  attribute \src "ls180.v:17.19-17.32"
-  wire width 4 output 13 \sdcard_data_o
-  attribute \src "ls180.v:18.13-18.27"
-  wire output 14 \sdcard_data_oe
-  attribute \src "ls180.v:27.20-27.27"
-  wire width 13 output 23 \sdram_a
-  attribute \src "ls180.v:36.19-36.27"
-  wire width 2 output 32 \sdram_ba
-  attribute \src "ls180.v:33.13-33.24"
-  wire output 29 \sdram_cas_n
-  attribute \src "ls180.v:35.13-35.22"
-  wire output 31 \sdram_cke
-  attribute \src "ls180.v:38.13-38.24"
-  wire output 34 \sdram_clock
-  attribute \src "ls180.v:157.6-157.19"
+  wire width 4 output 12 \sdcard_data_o
+  attribute \src "ls180.v:17.13-17.27"
+  wire output 13 \sdcard_data_oe
+  attribute \src "ls180.v:23.20-23.27"
+  wire width 13 output 19 \sdram_a
+  attribute \src "ls180.v:32.19-32.27"
+  wire width 2 output 28 \sdram_ba
+  attribute \src "ls180.v:29.13-29.24"
+  wire output 25 \sdram_cas_n
+  attribute \src "ls180.v:31.13-31.22"
+  wire output 27 \sdram_cke
+  attribute \src "ls180.v:34.13-34.24"
+  wire output 30 \sdram_clock
+  attribute \src "ls180.v:153.6-153.19"
   wire \sdram_clock_1
-  attribute \src "ls180.v:34.13-34.23"
-  wire output 30 \sdram_cs_n
-  attribute \src "ls180.v:37.19-37.27"
-  wire width 2 output 33 \sdram_dm
-  attribute \src "ls180.v:28.21-28.31"
-  wire width 16 output 24 \sdram_dq_i
-  attribute \src "ls180.v:29.20-29.30"
-  wire width 16 output 25 \sdram_dq_o
-  attribute \src "ls180.v:30.13-30.24"
-  wire output 26 \sdram_dq_oe
-  attribute \src "ls180.v:32.13-32.24"
-  wire output 28 \sdram_ras_n
-  attribute \src "ls180.v:31.13-31.23"
-  wire output 27 \sdram_we_n
+  attribute \src "ls180.v:30.13-30.23"
+  wire output 26 \sdram_cs_n
+  attribute \src "ls180.v:33.19-33.27"
+  wire width 2 output 29 \sdram_dm
+  attribute \src "ls180.v:24.21-24.31"
+  wire width 16 output 20 \sdram_dq_i
+  attribute \src "ls180.v:25.20-25.30"
+  wire width 16 output 21 \sdram_dq_o
+  attribute \src "ls180.v:26.13-26.24"
+  wire output 22 \sdram_dq_oe
+  attribute \src "ls180.v:28.13-28.24"
+  wire output 24 \sdram_ras_n
+  attribute \src "ls180.v:27.13-27.23"
+  wire output 23 \sdram_we_n
   attribute \src "ls180.v:2647.6-2647.15"
   wire \sdrio_clk
   attribute \src "ls180.v:2648.6-2648.17"
@@ -86455,28 +86455,28 @@ module \ls180
   wire \sdrio_clk_8
   attribute \src "ls180.v:2656.6-2656.17"
   wire \sdrio_clk_9
-  attribute \src "ls180.v:5.13-5.26"
-  wire output 1 \spimaster_clk
-  attribute \src "ls180.v:7.13-7.27"
-  wire output 3 \spimaster_cs_n
-  attribute \src "ls180.v:8.14-8.28"
-  wire output 4 \spimaster_miso
-  attribute \src "ls180.v:6.13-6.27"
-  wire output 2 \spimaster_mosi
-  attribute \src "ls180.v:23.13-23.26"
-  wire output 19 \spisdcard_clk
-  attribute \src "ls180.v:25.13-25.27"
-  wire output 21 \spisdcard_cs_n
-  attribute \src "ls180.v:26.14-26.28"
-  wire output 22 \spisdcard_miso
-  attribute \src "ls180.v:24.13-24.27"
-  wire output 20 \spisdcard_mosi
+  attribute \src "ls180.v:19.13-19.26"
+  wire output 15 \spimaster_clk
+  attribute \src "ls180.v:21.13-21.27"
+  wire output 17 \spimaster_cs_n
+  attribute \src "ls180.v:22.14-22.28"
+  wire output 18 \spimaster_miso
+  attribute \src "ls180.v:20.13-20.27"
+  wire output 16 \spimaster_mosi
+  attribute \src "ls180.v:39.13-39.26"
+  wire output 35 \spisdcard_clk
+  attribute \src "ls180.v:41.13-41.27"
+  wire output 37 \spisdcard_cs_n
+  attribute \src "ls180.v:42.14-42.28"
+  wire output 38 \spisdcard_miso
+  attribute \src "ls180.v:40.13-40.27"
+  wire output 36 \spisdcard_mosi
   attribute \src "ls180.v:43.13-43.20"
   wire input 39 \sys_clk
   attribute \src "ls180.v:249.6-249.15"
   wire \sys_clk_1
   attribute \src "ls180.v:45.19-45.31"
-  wire width 3 input 41 \sys_clksel_i
+  wire width 2 input 41 \sys_clksel_i
   attribute \src "ls180.v:46.14-46.26"
   wire output 42 \sys_pll_18_o
   attribute \src "ls180.v:47.14-47.27"
@@ -86485,10 +86485,10 @@ module \ls180
   wire input 40 \sys_rst
   attribute \src "ls180.v:250.6-250.15"
   wire \sys_rst_1
-  attribute \src "ls180.v:21.13-21.20"
-  wire input 17 \uart_rx
-  attribute \src "ls180.v:20.13-20.20"
-  wire output 16 \uart_tx
+  attribute \src "ls180.v:10.13-10.20"
+  wire input 6 \uart_rx
+  attribute \src "ls180.v:9.13-9.20"
+  wire output 5 \uart_tx
   attribute \src "ls180.v:10057.12-10057.15"
   memory width 32 size 128 \mem
   attribute \src "ls180.v:10077.12-10077.19"
@@ -115915,6 +115915,14 @@ module \ls180
       update \main_sdphy_datar_pads_in_pads_in_payload_data_oe $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0]
     sync init
   end
+  attribute \src "ls180.v:130.5-130.69"
+  process $proc$ls180.v:130$2787
+    assign { } { }
+    assign $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] 1'0
+    sync always
+      update \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0]
+    sync init
+  end
   attribute \src "ls180.v:1301.5-1301.49"
   process $proc$ls180.v:1301$3316
     assign { } { }
@@ -116059,14 +116067,6 @@ module \ls180
     sync init
       update \main_sdphy_datar_count $1\main_sdphy_datar_count[9:0]
   end
-  attribute \src "ls180.v:132.5-132.74"
-  process $proc$ls180.v:132$2787
-    assign { } { }
-    assign $0\main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso[0:0] 1'0
-    sync always
-      update \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso $0\main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso[0:0]
-    sync init
-  end
   attribute \src "ls180.v:1320.5-1320.48"
   process $proc$ls180.v:1320$3334
     assign { } { }
@@ -116075,14 +116075,6 @@ module \ls180
       update \main_sdphy_datar_datar_pads_in_ready $0\main_sdphy_datar_datar_pads_in_ready[0:0]
     sync init
   end
-  attribute \src "ls180.v:133.12-133.74"
-  process $proc$ls180.v:133$2788
-    assign { } { }
-    assign $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] 16'0000000000000000
-    sync always
-      update \main_libresocsim_libresoc_constraintmanager_obj_gpio_i $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0]
-    sync init
-  end
   attribute \src "ls180.v:1331.5-1331.55"
   process $proc$ls180.v:1331$3335
     assign { } { }
@@ -116107,6 +116099,14 @@ module \ls180
       update \main_sdphy_datar_datar_converter_sink_first $0\main_sdphy_datar_datar_converter_sink_first[0:0]
     sync init
   end
+  attribute \src "ls180.v:134.5-134.72"
+  process $proc$ls180.v:134$2788
+    assign { } { }
+    assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] 1'0
+    sync always
+      update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0]
+    sync init
+  end
   attribute \src "ls180.v:1340.5-1340.54"
   process $proc$ls180.v:1340$3338
     assign { } { }
@@ -116211,14 +116211,6 @@ module \ls180
     sync init
       update \main_sdphy_sdpads_cmd_i $1\main_sdphy_sdpads_cmd_i[0:0]
   end
-  attribute \src "ls180.v:137.5-137.72"
-  process $proc$ls180.v:137$2789
-    assign { } { }
-    assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] 1'0
-    sync always
-      update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0]
-    sync init
-  end
   attribute \src "ls180.v:1371.11-1371.42"
   process $proc$ls180.v:1371$3351
     assign { } { }
@@ -116291,14 +116283,6 @@ module \ls180
     sync init
       update \main_sdcore_block_length_re $1\main_sdcore_block_length_re[0:0]
   end
-  attribute \src "ls180.v:140.11-140.24"
-  process $proc$ls180.v:140$2790
-    assign { } { }
-    assign $0\eint_1[2:0] 3'000
-    sync always
-      update \eint_1 $0\eint_1[2:0]
-    sync init
-  end
   attribute \src "ls180.v:1400.12-1400.51"
   process $proc$ls180.v:1400$3360
     assign { } { }
@@ -116323,6 +116307,22 @@ module \ls180
     sync init
       update \main_sdcore_crc7_inserter_crcreg0 $1\main_sdcore_crc7_inserter_crcreg0[6:0]
   end
+  attribute \src "ls180.v:141.5-141.74"
+  process $proc$ls180.v:141$2789
+    assign { } { }
+    assign $0\main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso[0:0] 1'0
+    sync always
+      update \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso $0\main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso[0:0]
+    sync init
+  end
+  attribute \src "ls180.v:143.12-143.78"
+  process $proc$ls180.v:143$2790
+    assign { } { }
+    assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] 16'0000000000000000
+    sync always
+      update \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0]
+    sync init
+  end
   attribute \src "ls180.v:1444.11-1444.47"
   process $proc$ls180.v:1444$3363
     assign { } { }
@@ -116339,14 +116339,6 @@ module \ls180
     sync init
       update \main_sdcore_crc16_inserter_sink_ready $1\main_sdcore_crc16_inserter_sink_ready[0:0]
   end
-  attribute \src "ls180.v:145.5-145.74"
-  process $proc$ls180.v:145$2791
-    assign { } { }
-    assign $0\main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso[0:0] 1'0
-    sync always
-      update \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso $0\main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso[0:0]
-    sync init
-  end
   attribute \src "ls180.v:1452.5-1452.51"
   process $proc$ls180.v:1452$3365
     assign { } { }
@@ -116427,14 +116419,6 @@ module \ls180
     sync init
       update \main_sdcore_crc16_inserter_crc1_crc $1\main_sdcore_crc16_inserter_crc1_crc[15:0]
   end
-  attribute \src "ls180.v:147.12-147.78"
-  process $proc$ls180.v:147$2792
-    assign { } { }
-    assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] 16'0000000000000000
-    sync always
-      update \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0]
-    sync init
-  end
   attribute \src "ls180.v:1472.12-1472.59"
   process $proc$ls180.v:1472$3375
     assign { } { }
@@ -116739,6 +116723,14 @@ module \ls180
     sync init
       update \main_sdcore_crc16_checker_fifo3 $1\main_sdcore_crc16_checker_fifo3[15:0]
   end
+  attribute \src "ls180.v:154.11-154.24"
+  process $proc$ls180.v:154$2791
+    assign { } { }
+    assign $0\eint_1[2:0] 3'000
+    sync always
+      update \eint_1 $0\eint_1[2:0]
+    sync init
+  end
   attribute \src "ls180.v:1540.11-1540.39"
   process $proc$ls180.v:1540$3413
     assign { } { }
@@ -116803,6 +116795,14 @@ module \ls180
     sync init
       update \main_sdcore_data_timeout $1\main_sdcore_data_timeout[0:0]
   end
+  attribute \src "ls180.v:155.12-155.74"
+  process $proc$ls180.v:155$2792
+    assign { } { }
+    assign $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] 16'0000000000000000
+    sync always
+      update \main_libresocsim_libresoc_constraintmanager_obj_gpio_i $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0]
+    sync init
+  end
   attribute \src "ls180.v:1557.11-1557.41"
   process $proc$ls180.v:1557$3421
     assign { } { }
@@ -116859,14 +116859,6 @@ module \ls180
     sync init
       update \main_sdblock2mem_fifo_wrport_adr $1\main_sdblock2mem_fifo_wrport_adr[4:0]
   end
-  attribute \src "ls180.v:159.5-159.69"
-  process $proc$ls180.v:159$2793
-    assign { } { }
-    assign $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] 1'0
-    sync always
-      update \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0]
-    sync init
-  end
   attribute \src "ls180.v:1605.5-1605.51"
   process $proc$ls180.v:1605$3428
     assign { } { }
@@ -116907,6 +116899,14 @@ module \ls180
     sync init
       update \main_sdblock2mem_converter_demux $1\main_sdblock2mem_converter_demux[1:0]
   end
+  attribute \src "ls180.v:161.5-161.74"
+  process $proc$ls180.v:161$2793
+    assign { } { }
+    assign $0\main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso[0:0] 1'0
+    sync always
+      update \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso $0\main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso[0:0]
+    sync init
+  end
   attribute \src "ls180.v:1611.5-1611.49"
   process $proc$ls180.v:1611$3433
     assign { } { }
@@ -126467,11 +126467,11 @@ module \ls180
   end
   attribute \src "ls180.v:7431.1-10055.4"
   process $proc$ls180.v:7431$2374
+    assign $0\uart_tx[0:0] \uart_tx
+    assign $0\pwm[1:0] \pwm
     assign $0\spimaster_clk[0:0] \spimaster_clk
     assign $0\spimaster_mosi[0:0] \spimaster_mosi
     assign { } { }
-    assign $0\uart_tx[0:0] \uart_tx
-    assign $0\pwm[1:0] \pwm
     assign $0\spisdcard_clk[0:0] \spisdcard_clk
     assign $0\spisdcard_mosi[0:0] \spisdcard_mosi
     assign { } { }
@@ -131011,11 +131011,11 @@ module \ls180
         assign $0\main_libresocsim_scratch_storage[31:0] 305419896
         assign $0\main_libresocsim_scratch_re[0:0] 1'0
         assign $0\main_libresocsim_bus_errors[31:0] 0
+        assign $0\uart_tx[0:0] 1'1
+        assign $0\pwm[1:0] 2'00
         assign $0\spimaster_clk[0:0] 1'0
         assign $0\spimaster_mosi[0:0] 1'0
         assign $0\spimaster_cs_n[0:0] 1'0
-        assign $0\uart_tx[0:0] 1'1
-        assign $0\pwm[1:0] 2'00
         assign $0\spisdcard_clk[0:0] 1'0
         assign $0\spisdcard_mosi[0:0] 1'0
         assign $0\spisdcard_cs_n[0:0] 1'0
@@ -131302,11 +131302,11 @@ module \ls180
       case 
     end
     sync posedge \sys_clk_1
+      update \uart_tx $0\uart_tx[0:0]
+      update \pwm $0\pwm[1:0]
       update \spimaster_clk $0\spimaster_clk[0:0]
       update \spimaster_mosi $0\spimaster_mosi[0:0]
       update \spimaster_cs_n $0\spimaster_cs_n[0:0]
-      update \uart_tx $0\uart_tx[0:0]
-      update \pwm $0\pwm[1:0]
       update \spisdcard_clk $0\spisdcard_clk[0:0]
       update \spisdcard_mosi $0\spisdcard_mosi[0:0]
       update \spisdcard_cs_n $0\spisdcard_cs_n[0:0]
diff --git a/pinmux b/pinmux
index 7f8cbf7..f5495dc 160000
--- a/pinmux
+++ b/pinmux
@@ -1 +1 @@
-Subproject commit 7f8cbf72abced671b4d0d1ae358d656470220ca4
+Subproject commit f5495dcca0e6c7ce85743df7f93206ac77b8cd64