From: Luke Kenneth Casson Leighton Date: Fri, 17 Apr 2020 14:01:13 +0000 (+0100) Subject: delay too long X-Git-Tag: div_pipeline~1432^2~3 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f6276a771213fd16b8b70a310411721c14a919ad;p=soc.git delay too long --- diff --git a/src/soc/experiment/score6600_multi.py b/src/soc/experiment/score6600_multi.py index da30ca67..ee958630 100644 --- a/src/soc/experiment/score6600_multi.py +++ b/src/soc/experiment/score6600_multi.py @@ -1186,7 +1186,7 @@ def power_sim(m, dut, pdecode2, instruction, alusim): # issue instruction(s), wait for issue to be free before proceeding for ins, code in zip(gen, program.assembly.splitlines()): yield instruction.eq(ins) # raw binary instr. - yield Delay(1e-6) + yield #Delay(1e-6) print("binary 0x{:X}".format(ins & 0xffffffff)) print("assembly", code)