From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Date: Tue, 12 May 2020 11:37:36 +0000 (+1000)
Subject: WB2CSR: Use CSR address_width for the wishbone bus
X-Git-Tag: 24jan2021_ls180~353^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f628ff6b47d90c783c60bbada5abbf7bc0fc6660;p=litex.git

WB2CSR: Use CSR address_width for the wishbone bus

Currently, we create a wishbone interface with the default address
width (30 bits) for the bridge. Instead, create an interface that
has the same number of address bits as the CSR bus.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---

diff --git a/litex/soc/interconnect/wishbone2csr.py b/litex/soc/interconnect/wishbone2csr.py
index b9544aad..c9e30779 100644
--- a/litex/soc/interconnect/wishbone2csr.py
+++ b/litex/soc/interconnect/wishbone2csr.py
@@ -10,12 +10,12 @@ from litex.soc.interconnect import csr_bus, wishbone
 
 class WB2CSR(Module):
     def __init__(self, bus_wishbone=None, bus_csr=None):
-        if bus_wishbone is None:
-            bus_wishbone = wishbone.Interface()
-        self.wishbone = bus_wishbone
         if bus_csr is None:
             bus_csr = csr_bus.Interface()
         self.csr = bus_csr
+        if bus_wishbone is None:
+            bus_wishbone = wishbone.Interface(adr_width=bus_csr.address_width)
+        self.wishbone = bus_wishbone
 
         # # #