From: lkcl <lkcl@web>
Date: Sat, 2 Apr 2022 12:08:46 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2929
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f62eec9f6c1fd2903381dacb137e4eebebdba54f;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index fe16696c6..1f31f6577 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -459,11 +459,11 @@ have to work round the fact that the Condition Testing is NOR or NAND.
 The alternative to not having additional behavioural inversion
 (`SNZ`, `VSb`, `CTi`) would be to have a second (unconditional)
 branch directly after the first, which the first branch jumps over.
-This contrived construct is avoided by the behavioural inversion bits.
+This contrivance is avoided by the behavioural inversion bits.
 
 # Pseudocode and examples
 
-For comparative purposes this is a copy of the v3.0B bc pseudocode,
+For comparative purposes this is a copy of the v3.0B `bc` pseudocode,
 noting that M and AA have not been added to the SVP64 versions
 for simplicity of illustration.  ctr_ok does not appear in the SVP64
 versions because of the way that CTRtest Mode interacts.