From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 30 Mar 2020 15:19:56 +0000 (-0700)
Subject: Apply suggestions from code review
X-Git-Tag: working-ls180~707^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f64d59d824424756794fcb8c1fad4d6a088358d8;p=yosys.git

Apply suggestions from code review

Co-Authored-By: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
---

diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc
index 236c3c99c..0111c2309 100644
--- a/passes/memory/memory_share.cc
+++ b/passes/memory/memory_share.cc
@@ -665,9 +665,7 @@ struct MemoryShareWorker
 	// Setup and run
 	// -------------
 
-	MemoryShareWorker(RTLIL::Design *design) :
-			design(design), modwalker(design)
-	{
+	MemoryShareWorker(RTLIL::Design *design) : design(design), modwalker(design) {}
 	}
 
 	void operator()(RTLIL::Module* module)
@@ -764,7 +762,6 @@ struct MemorySharePass : public Pass {
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE {
 		log_header(design, "Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).\n");
 		extra_args(args, 1, design);
-
 		MemoryShareWorker msw(design);
 
 		for (auto module : design->selected_modules())
diff --git a/passes/opt/share.cc b/passes/opt/share.cc
index fd72c762b..ec2e110a8 100644
--- a/passes/opt/share.cc
+++ b/passes/opt/share.cc
@@ -1148,11 +1148,10 @@ struct ShareWorker
 	#endif
 
 		limit = config.limit;
-
 		modwalker.setup(module);
 
 		cells_to_remove.clear();
-		recursion_state.clear();;
+		recursion_state.clear();
 		topo_cell_drivers.clear();
 		topo_bit_drivers.clear();
 		exclusive_ctrls.clear();