From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 22 Apr 2020 20:07:19 +0000 (-0700)
Subject: abc9_ops: update docs
X-Git-Tag: working-ls180~549^2~10
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f652a9c11c75b7728db838c1c74c587ba92043ca;p=yosys.git

abc9_ops: update docs
---

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 5521bdf62..a87a94b1d 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -1516,29 +1516,28 @@ struct Abc9OpsPass : public Pass {
 		log("        derive all used (* abc9_box *) requiring bypass, or (* abc9_flop *) (if\n");
 		log("        -dff option) whitebox modules. with (* abc9_box *) modules, bypassing is\n");
 		log("        necessary if sequential elements (e.g. $dff, $mem, etc.) are discovered\n");
-		log("        inside, to ensure that any combinatorial paths are correctly captured.\n");
+		log("        inside to ensure that any combinatorial paths are correctly captured.\n");
 		log("        with (* abc9_flop *) modules, only those containing $dff/$_DFF_[NP]_\n");
 		log("        cells with zero initial state -- due to an ABC limitation -- will be\n");
-		log("        derived. for such derived modules, add a rule inside the '$abc9_unmap'\n");
-		log("        design that can map a cell instantiating a derived module back to the\n");
-		log("        original cell with parameters.\n");
+		log("        derived.\n");
 		log("\n");
 		log("    -prep_bypass\n");
 		log("        create techmap rules in the '$abc9_map' and '$abc9_unmap' designs for\n");
 		log("        bypassing sequential (* abc9_box *) modules using a combinatorial box\n");
-		log("        (named *_$abc9_byp) that has inherited all its $specify2 (simple path)\n");
-		log("        cells.\n");
+		log("        (named *_$abc9_byp). this bypass box will only contain ports that are\n");
+		log("        referenced by a simple path declaration ($specify2 cell) inside a\n");
+		log("        specify block.\n");
 		log("\n");
 		log("    -prep_dff\n");
 		log("        select all (* abc9_flop *) modules instantiated in the design and store\n");
 		log("        in the named selection '$abc9_flops'.\n");
 		log("\n");
 		log("    -prep_dff_submod\n");
-		log("        within (* abc9_flop *) modules, attach dummy buffers to all ports and move\n");
-		log("        all $specify3/$specrule cells that share a 'DST' port with the $_DFF_[NP]_.Q\n");
-		log("        port from this 'Q' port to the DFF's 'D' port. this is to ensure that all\n");
-		log("        module ports will exist in any submodule, and prepare such specify cells to\n");
-		log("        be moved within.\n");
+		log("        within (* abc9_flop *) modules, rewrite all edge-sensitive path\n");
+		log("        declarations and $setup() timing checks ($specify3 and $specrule cells)\n");
+		log("        that share a 'DST' port with the $_DFF_[NP]_.Q port from this 'Q' port to\n");
+		log("        the DFF's 'D' port. this is to prepare such specify cells to be moved\n");
+		log("        into the flop box.\n");
 		log("\n");
 		log("    -prep_dff_unmap\n");
 		log("        populate the '$abc9_unmap' design with techmap rules for mapping *_$abc9_flop\n");