From: R Veera Kumar <vklr@vkten.in>
Date: Tue, 23 Nov 2021 06:09:04 +0000 (+0530)
Subject: Add computed CR0 to expected version of case_adde_0
X-Git-Tag: sv_maxu_works-initial~712
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f65613cc41caa21aa82cc91691fd0b113f5401de;p=openpower-isa.git

Add computed CR0 to expected version of case_adde_0
---

diff --git a/src/openpower/test/alu/alu_cases.py b/src/openpower/test/alu/alu_cases.py
index 1eead0fa..2afff938 100644
--- a/src/openpower/test/alu/alu_cases.py
+++ b/src/openpower/test/alu/alu_cases.py
@@ -248,13 +248,19 @@ class ALUTestCase(TestAccumulatorBase):
             eq = 0
             gt = 0
             le = 0
+            if (result & (1<<63)) != 0:
+                le = 1
+            elif result == 0:
+                eq = 1
+            else:
+                gt = 1
             # now construct the state
             e = ExpectedState(pc=4)
             e.intregs[6] = initial_regs[6] # should be same as initial
             e.intregs[7] = initial_regs[7] # should be same as initial
             e.intregs[5] = result
             e.ca = carry_out | (carry_out32<<1)  # maybe other way round
-            e.crregs[0] = eq | (gt<<1) | (le<<2) # something like this
+            e.crregs[0] = (eq<<1) | (gt<<2) | (le<<3) # something like this
 
             self.add_case(Program(lst, bigendian),
                           initial_regs, initial_sprs, expected=e)