From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 23 Apr 2019 15:58:34 +0000 (-0700)
Subject: Fix spelling
X-Git-Tag: yosys-0.9~169
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f66792c43afeacdcceedde83785471e51ee12593;p=yosys.git

Fix spelling
---

diff --git a/README.md b/README.md
index 46bed4242..7b4477053 100644
--- a/README.md
+++ b/README.md
@@ -370,7 +370,7 @@ Verilog Attributes and non-standard features
 
 - When defining a macro with `define, all text between triple double quotes
   is interpreted as macro body, even if it contains unescaped newlines. The
-  tipple double quotes are removed from the macro body. For example:
+  triple double quotes are removed from the macro body. For example:
 
       `define MY_MACRO(a, b) """
          assign a = 23;