From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 12 Feb 2021 15:23:05 +0000 (+0000)
Subject: add SVSTATE to TestCase infrastructure for use in TestIssuer
X-Git-Tag: convert-csv-opcode-to-binary~239
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f67cd9f81a517e3b6e75c58bdc1d0d836fae26b7;p=soc.git

add SVSTATE to TestCase infrastructure for use in TestIssuer
---

diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py
index 6489f5a0..c21ebd7f 100644
--- a/src/soc/fu/test/common.py
+++ b/src/soc/fu/test/common.py
@@ -100,13 +100,15 @@ class TestAccumulatorBase:
 
     def add_case(self, prog, initial_regs=None, initial_sprs=None,
                  initial_cr=0, initial_msr=0,
-                 initial_mem=None):
+                 initial_mem=None,
+                 initial_svstate=0):
 
         test_name = inspect.stack()[1][3]  # name of caller of this function
         tc = TestCase(prog, test_name,
                       regs=initial_regs, sprs=initial_sprs, cr=initial_cr,
                       msr=initial_msr,
-                      mem=initial_mem)
+                      mem=initial_mem,
+                      svstate=initial_svstate)
 
         self.test_data.append(tc)
 
@@ -115,7 +117,8 @@ class TestCase:
     def __init__(self, program, name, regs=None, sprs=None, cr=0, mem=None,
                  msr=0,
                  do_sim=True,
-                 extra_break_addr=None):
+                 extra_break_addr=None,
+                 svstate=0):
 
         self.program = program
         self.name = name
@@ -133,6 +136,7 @@ class TestCase:
         self.msr = msr
         self.do_sim = do_sim
         self.extra_break_addr = extra_break_addr
+        self.svstate = svstate
 
 
 class ALUHelpers:
diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py
index 78662579..4cb3bc0b 100644
--- a/src/soc/simple/test/test_issuer.py
+++ b/src/soc/simple/test/test_issuer.py
@@ -214,7 +214,8 @@ class TestRunner(FHDLTestCase):
                           test.msr,
                           initial_insns=gen, respect_pc=True,
                           disassembly=insncode,
-                          bigendian=bigendian)
+                          bigendian=bigendian,
+                          initial_svstate=test.svstate)
 
                 pc = 0  # start address
                 counter = 0  # test to pause/start