From: lkcl <lkcl@web>
Date: Sun, 3 Jul 2022 12:34:41 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1384
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f6806b579041a3e31910a22cfac0ff5aeb0daf1c;p=libreriscv.git

---

diff --git a/openpower/sv/vector_isa_comparison.mdwn b/openpower/sv/vector_isa_comparison.mdwn
index 55e28b2fc..5accba345 100644
--- a/openpower/sv/vector_isa_comparison.mdwn
+++ b/openpower/sv/vector_isa_comparison.mdwn
@@ -55,7 +55,8 @@ of a Vector Processor. Transcendentals can be added as a sub-RFC.
 
 There is considerable confusion surrounding Vector ISAs
 because of a mis-use of the word "Vector" in the marketing
-material of most well-known Packed SIMD ISAs. These Packed
+material of most well-known Packed SIMD ISAs of the past 3
+decades. These Packed
 SIMD ISAs used features "inspired" from Scalable Vector ISAs.
 
 * PackedSIMD VSX. VSX, which has the word "Vector" in its name,