From: Florent Kermarrec Date: Mon, 13 Apr 2015 14:47:22 +0000 (+0200) Subject: global: pep8 (E302) X-Git-Tag: 24jan2021_ls180~2328 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f68423f4236b22a39211da059d37611237979660;p=litex.git global: pep8 (E302) --- diff --git a/crc.py b/crc.py index 7967802e..60efbabc 100644 --- a/crc.py +++ b/crc.py @@ -1,5 +1,6 @@ import binascii + def insert_crc(i_filename, fbi_mode=False, o_filename=None): if o_filename is None: o_filename = i_filename diff --git a/make.py b/make.py index 0ac7df7f..087466ba 100755 --- a/make.py +++ b/make.py @@ -11,6 +11,7 @@ from misoclib.mem.sdram.phy import initsequence from misoc_import import misoc_import + def _get_args(): parser = argparse.ArgumentParser(formatter_class=argparse.RawDescriptionHelpFormatter, description="""\ diff --git a/misoc_import.py b/misoc_import.py index 51868a34..5407a27b 100644 --- a/misoc_import.py +++ b/misoc_import.py @@ -1,5 +1,6 @@ import sys, importlib + def misoc_import(default, external, name): if external: try: diff --git a/misoclib/com/gpio/__init__.py b/misoclib/com/gpio/__init__.py index f5fc17ad..88a49040 100644 --- a/misoclib/com/gpio/__init__.py +++ b/misoclib/com/gpio/__init__.py @@ -2,16 +2,19 @@ from migen.fhdl.std import * from migen.genlib.cdc import MultiReg from migen.bank.description import * + class GPIOIn(Module, AutoCSR): def __init__(self, signal): self._in = CSRStatus(flen(signal)) self.specials += MultiReg(signal, self._in.status) + class GPIOOut(Module, AutoCSR): def __init__(self, signal): self._out = CSRStorage(flen(signal)) self.comb += signal.eq(self._out.storage) + class GPIOInOut(Module): def __init__(self, in_signal, out_signal): self.submodules.gpio_in = GPIOIn(in_signal) @@ -20,6 +23,7 @@ class GPIOInOut(Module): def get_csrs(self): return self.gpio_in.get_csrs() + self.gpio_out.get_csrs() + class Blinker(Module): def __init__(self, signal, divbits=26): counter = Signal(divbits) diff --git a/misoclib/com/spi/__init__.py b/misoclib/com/spi/__init__.py index 4080e5d4..058cf1e3 100644 --- a/misoclib/com/spi/__init__.py +++ b/misoclib/com/spi/__init__.py @@ -2,6 +2,7 @@ from migen.fhdl.std import * from migen.bank.description import * from migen.genlib.fsm import FSM, NextState + class SPIMaster(Module, AutoCSR): def __init__(self, pads, width=24, div=2, cpha=1): self.pads = pads diff --git a/misoclib/com/spi/test/spi_master_tb.py b/misoclib/com/spi/test/spi_master_tb.py index a4f48b7d..70d0f70d 100644 --- a/misoclib/com/spi/test/spi_master_tb.py +++ b/misoclib/com/spi/test/spi_master_tb.py @@ -4,6 +4,7 @@ from migen.sim.generic import run_simulation from misoclib.com.spi import SPIMaster + class SPISlave(Module): def __init__(self, pads, width): self.pads = pads @@ -66,6 +67,7 @@ def spi_access(selfp, length, mosi): while not (selfp.spi_master._status.status & 0x1): yield + class TB(Module): def __init__(self): pads = Record([("cs_n", 1), ("clk", 1), ("mosi", 1), ("miso", 1)]) diff --git a/misoclib/com/uart/__init__.py b/misoclib/com/uart/__init__.py index 1a225301..bc5c6cd4 100644 --- a/misoclib/com/uart/__init__.py +++ b/misoclib/com/uart/__init__.py @@ -4,6 +4,7 @@ from migen.bank.eventmanager import * from migen.genlib.record import Record from migen.flow.actor import Sink, Source + class UART(Module, AutoCSR): def __init__(self, phy): self._rxtx = CSR(8) diff --git a/misoclib/com/uart/phy/__init__.py b/misoclib/com/uart/phy/__init__.py index 67188c75..5e083462 100644 --- a/misoclib/com/uart/phy/__init__.py +++ b/misoclib/com/uart/phy/__init__.py @@ -1,6 +1,7 @@ from misoclib.com.liteeth.common import * from misoclib.com.liteeth.generic import * + def UARTPHY(pads, *args, **kwargs): # Autodetect PHY if hasattr(pads, "source_stb"): diff --git a/misoclib/com/uart/phy/serial.py b/misoclib/com/uart/phy/serial.py index 086494b2..d22c1931 100644 --- a/misoclib/com/uart/phy/serial.py +++ b/misoclib/com/uart/phy/serial.py @@ -3,6 +3,7 @@ from migen.genlib.cdc import MultiReg from migen.bank.description import * from migen.flow.actor import Sink, Source + class UARTPHYSerialRX(Module): def __init__(self, pads, tuning_word): self.source = Source([("data", 8)]) @@ -52,6 +53,7 @@ class UARTPHYSerialRX(Module): Cat(phase_accumulator_rx, uart_clk_rxen).eq(2**31) ) + class UARTPHYSerialTX(Module): def __init__(self, pads, tuning_word): self.sink = Sink([("data", 8)]) @@ -93,6 +95,7 @@ class UARTPHYSerialTX(Module): ) ] + class UARTPHYSerial(Module, AutoCSR): def __init__(self, pads, clk_freq, baudrate=115200): self._tuning_word = CSRStorage(32, reset=int((baudrate/clk_freq)*2**32)) diff --git a/misoclib/com/uart/phy/sim.py b/misoclib/com/uart/phy/sim.py index 346284f4..a12bd086 100644 --- a/misoclib/com/uart/phy/sim.py +++ b/misoclib/com/uart/phy/sim.py @@ -3,6 +3,7 @@ import os, pty, time from migen.fhdl.std import * from migen.flow.actor import Sink, Source + class UARTPHYSim(Module): def __init__(self, pads, *args, **kwargs): self.sink = Sink([("data", 8)]) diff --git a/misoclib/cpu/lm32/__init__.py b/misoclib/cpu/lm32/__init__.py index 9f60d8e2..76e99092 100644 --- a/misoclib/cpu/lm32/__init__.py +++ b/misoclib/cpu/lm32/__init__.py @@ -3,6 +3,7 @@ import os from migen.fhdl.std import * from migen.bus import wishbone + class LM32(Module): def __init__(self, platform, eba_reset): self.ibus = i = wishbone.Interface() diff --git a/misoclib/cpu/mor1kx/__init__.py b/misoclib/cpu/mor1kx/__init__.py index d45ca413..42d607f7 100644 --- a/misoclib/cpu/mor1kx/__init__.py +++ b/misoclib/cpu/mor1kx/__init__.py @@ -3,6 +3,7 @@ import os from migen.fhdl.std import * from migen.bus import wishbone + class MOR1KX(Module): def __init__(self, platform, reset_pc): self.ibus = i = wishbone.Interface() diff --git a/misoclib/cpu/peripherals/identifier/__init__.py b/misoclib/cpu/peripherals/identifier/__init__.py index 8153f610..fc21ed92 100644 --- a/misoclib/cpu/peripherals/identifier/__init__.py +++ b/misoclib/cpu/peripherals/identifier/__init__.py @@ -3,6 +3,7 @@ from migen.bank.description import * from misoclib.cpu.peripherals.identifier import git + class Identifier(Module, AutoCSR): def __init__(self, sysid, frequency, revision=None): self._sysid = CSRStatus(16) diff --git a/misoclib/cpu/peripherals/identifier/git.py b/misoclib/cpu/peripherals/identifier/git.py index 4a90fffc..e92a6088 100644 --- a/misoclib/cpu/peripherals/identifier/git.py +++ b/misoclib/cpu/peripherals/identifier/git.py @@ -1,5 +1,6 @@ import subprocess + def get_id(): output = subprocess.check_output(["git", "rev-parse", "HEAD"]).decode("ascii") return int(output[:8], 16) diff --git a/misoclib/cpu/peripherals/timer/__init__.py b/misoclib/cpu/peripherals/timer/__init__.py index c8ff24a0..4061f837 100644 --- a/misoclib/cpu/peripherals/timer/__init__.py +++ b/misoclib/cpu/peripherals/timer/__init__.py @@ -2,6 +2,7 @@ from migen.fhdl.std import * from migen.bank.description import * from migen.bank.eventmanager import * + class Timer(Module, AutoCSR): def __init__(self, width=32): self._load = CSRStorage(width) diff --git a/misoclib/mem/flash/norflash16/__init__.py b/misoclib/mem/flash/norflash16/__init__.py index 226196cf..42c68c07 100644 --- a/misoclib/mem/flash/norflash16/__init__.py +++ b/misoclib/mem/flash/norflash16/__init__.py @@ -2,6 +2,7 @@ from migen.fhdl.std import * from migen.bus import wishbone from migen.genlib.fsm import FSM, NextState + class NorFlash16(Module): def __init__(self, pads, rd_timing, wr_timing): self.bus = wishbone.Interface() diff --git a/misoclib/mem/flash/spiflash/__init__.py b/misoclib/mem/flash/spiflash/__init__.py index 4edd2535..f842bfdf 100644 --- a/misoclib/mem/flash/spiflash/__init__.py +++ b/misoclib/mem/flash/spiflash/__init__.py @@ -9,6 +9,7 @@ _FAST_READ = 0x0b _DIOFR = 0xbb _QIOFR = 0xeb + def _format_cmd(cmd, spi_width): """ `cmd` is the read instruction. Since everything is transmitted on all @@ -23,6 +24,7 @@ def _format_cmd(cmd, spi_width): c &= ~(1<<(b*spi_width)) return c + class SpiFlash(Module, AutoCSR): def __init__(self, pads, dummy=15, div=2, with_bitbang=True): """ @@ -141,6 +143,7 @@ class SpiFlash(Module, AutoCSR): self.sync += timeline(bus.cyc & bus.stb & (i == div - 1), tseq) + class SpiFlashTB(Module): def __init__(self): self.submodules.master = wishbone.Initiator(self.gen_reads()) diff --git a/misoclib/mem/sdram/core/__init__.py b/misoclib/mem/sdram/core/__init__.py index 65a433d7..8c1a6a63 100644 --- a/misoclib/mem/sdram/core/__init__.py +++ b/misoclib/mem/sdram/core/__init__.py @@ -6,6 +6,7 @@ from misoclib.mem.sdram.phy import dfii from misoclib.mem.sdram.core import minicon, lasmicon from misoclib.mem.sdram.core import lasmixbar + class SDRAMCore(Module, AutoCSR): def __init__(self, phy, geom_settings, timing_settings, controller_settings, **kwargs): # DFI diff --git a/misoclib/mem/sdram/core/lasmibus.py b/misoclib/mem/sdram/core/lasmibus.py index 2585ace4..65d385dc 100644 --- a/misoclib/mem/sdram/core/lasmibus.py +++ b/misoclib/mem/sdram/core/lasmibus.py @@ -4,6 +4,7 @@ from migen.genlib import roundrobin from migen.genlib.record import * from migen.genlib.misc import optree + class Interface(Record): def __init__(self, aw, dw, nbanks, req_queue_size, read_latency, write_latency): self.aw = aw @@ -33,6 +34,7 @@ class Interface(Record): ] Record.__init__(self, layout) + class Initiator(Module): def __init__(self, generator, bus): self.generator = generator @@ -75,6 +77,7 @@ class Initiator(Module): else: selfp.bus.we = 1 + class TargetModel: def __init__(self): self.last_bank = 0 @@ -96,6 +99,7 @@ class TargetModel: self.last_bank += 1 return self.last_bank + class _ReqFIFO(Module): def __init__(self, req_queue_size, bank): self.req_queue_size = req_queue_size @@ -112,6 +116,7 @@ class _ReqFIFO(Module): selfp.bank.lock = bool(self.contents) do_simulation.passive = True + class Target(Module): def __init__(self, model, *ifargs, **ifkwargs): self.model = model diff --git a/misoclib/mem/sdram/core/lasmicon/__init__.py b/misoclib/mem/sdram/core/lasmicon/__init__.py index b3a37e25..aeda333f 100644 --- a/misoclib/mem/sdram/core/lasmicon/__init__.py +++ b/misoclib/mem/sdram/core/lasmicon/__init__.py @@ -6,6 +6,7 @@ from misoclib.mem.sdram.core.lasmicon.refresher import * from misoclib.mem.sdram.core.lasmicon.bankmachine import * from misoclib.mem.sdram.core.lasmicon.multiplexer import * + class LASMIconSettings: def __init__(self, req_queue_size=8, read_time=32, write_time=16, @@ -24,6 +25,7 @@ class LASMIconSettings: self.with_memtest = with_memtest self.with_refresh = with_refresh + class LASMIcon(Module): def __init__(self, phy_settings, geom_settings, timing_settings, controller_settings, **kwargs): if phy_settings.memtype in ["SDR"]: diff --git a/misoclib/mem/sdram/core/lasmicon/bankmachine.py b/misoclib/mem/sdram/core/lasmicon/bankmachine.py index 6bdc1a69..9337f097 100644 --- a/misoclib/mem/sdram/core/lasmicon/bankmachine.py +++ b/misoclib/mem/sdram/core/lasmicon/bankmachine.py @@ -6,6 +6,7 @@ from migen.genlib.fifo import SyncFIFO from misoclib.mem.sdram.core.lasmicon.multiplexer import * + class _AddressSlicer: def __init__(self, colbits, address_align): self.colbits = colbits @@ -25,6 +26,7 @@ class _AddressSlicer: else: return Cat(Replicate(0, self.address_align), address[:split]) + class BankMachine(Module): def __init__(self, geom_settings, timing_settings, controller_settings, address_align, bankn, req): self.refresh_req = Signal() diff --git a/misoclib/mem/sdram/core/lasmicon/multiplexer.py b/misoclib/mem/sdram/core/lasmicon/multiplexer.py index f1a811d3..50fd11d2 100644 --- a/misoclib/mem/sdram/core/lasmicon/multiplexer.py +++ b/misoclib/mem/sdram/core/lasmicon/multiplexer.py @@ -6,6 +6,7 @@ from migen.bank.description import AutoCSR from misoclib.mem.sdram.core.lasmicon.perf import Bandwidth + class CommandRequest: def __init__(self, a, ba): self.a = Signal(a) @@ -14,6 +15,7 @@ class CommandRequest: self.ras_n = Signal(reset=1) self.we_n = Signal(reset=1) + class CommandRequestRW(CommandRequest): def __init__(self, a, ba): CommandRequest.__init__(self, a, ba) @@ -23,6 +25,7 @@ class CommandRequestRW(CommandRequest): self.is_read = Signal() self.is_write = Signal() + class _CommandChooser(Module): def __init__(self, requests): self.want_reads = Signal() @@ -56,6 +59,7 @@ class _CommandChooser(Module): for i, req in enumerate(requests)] self.comb += rr.ce.eq(self.cmd.ack) + class _Steerer(Module): def __init__(self, commands, dfi): ncmd = len(commands) @@ -88,6 +92,7 @@ class _Steerer(Module): phase.wrdata_en.eq(Array(stb_and(cmd, "is_write") for cmd in commands)[sel]) ] + class Multiplexer(Module, AutoCSR): def __init__(self, phy_settings, geom_settings, timing_settings, controller_settings, bank_machines, refresher, dfi, lasmic, with_bandwidth=False): diff --git a/misoclib/mem/sdram/core/lasmicon/perf.py b/misoclib/mem/sdram/core/lasmicon/perf.py index 377f6b1e..2c7e8cf0 100644 --- a/misoclib/mem/sdram/core/lasmicon/perf.py +++ b/misoclib/mem/sdram/core/lasmicon/perf.py @@ -1,6 +1,7 @@ from migen.fhdl.std import * from migen.bank.description import * + class Bandwidth(Module, AutoCSR): def __init__(self, cmd, data_width, period_bits=24): self._update = CSR() diff --git a/misoclib/mem/sdram/core/lasmicon/refresher.py b/misoclib/mem/sdram/core/lasmicon/refresher.py index 98946998..60f30479 100644 --- a/misoclib/mem/sdram/core/lasmicon/refresher.py +++ b/misoclib/mem/sdram/core/lasmicon/refresher.py @@ -4,6 +4,7 @@ from migen.genlib.fsm import FSM from misoclib.mem.sdram.core.lasmicon.multiplexer import * + class Refresher(Module): def __init__(self, a, ba, tRP, tREFI, tRFC, enabled=True): self.req = Signal() diff --git a/misoclib/mem/sdram/core/lasmixbar.py b/misoclib/mem/sdram/core/lasmixbar.py index 4bd70ff1..56e67aa5 100644 --- a/misoclib/mem/sdram/core/lasmixbar.py +++ b/misoclib/mem/sdram/core/lasmixbar.py @@ -5,6 +5,7 @@ from migen.genlib.misc import optree from misoclib.mem.sdram.core.lasmibus import Interface + def _getattr_all(l, attr): it = iter(l) r = getattr(next(it), attr) @@ -13,6 +14,7 @@ def _getattr_all(l, attr): raise ValueError return r + class LASMIxbar(Module): def __init__(self, controllers, cba_shift): self._controllers = controllers diff --git a/misoclib/mem/sdram/core/minicon/__init__.py b/misoclib/mem/sdram/core/minicon/__init__.py index f68de824..b7fb2148 100644 --- a/misoclib/mem/sdram/core/minicon/__init__.py +++ b/misoclib/mem/sdram/core/minicon/__init__.py @@ -4,6 +4,7 @@ from migen.genlib.fsm import FSM, NextState from misoclib.mem.sdram.phy import dfi as dfibus + class _AddressSlicer: def __init__(self, colbits, bankbits, rowbits, address_align): self.colbits = colbits @@ -34,10 +35,12 @@ class _AddressSlicer: else: return Cat(Replicate(0, self.address_align), address[:split]) + class MiniconSettings: def __init__(self): pass + class Minicon(Module): def __init__(self, phy_settings, geom_settings, timing_settings): if phy_settings.memtype in ["SDR"]: diff --git a/misoclib/mem/sdram/frontend/dma_lasmi.py b/misoclib/mem/sdram/frontend/dma_lasmi.py index 785a6c4a..54c48433 100644 --- a/misoclib/mem/sdram/frontend/dma_lasmi.py +++ b/misoclib/mem/sdram/frontend/dma_lasmi.py @@ -2,6 +2,7 @@ from migen.fhdl.std import * from migen.flow.actor import * from migen.genlib.fifo import SyncFIFO + class Reader(Module): def __init__(self, lasmim, fifo_depth=None): self.address = Sink([("a", lasmim.aw)]) diff --git a/misoclib/mem/sdram/frontend/memtest.py b/misoclib/mem/sdram/frontend/memtest.py index ec255a89..df5ba9fe 100644 --- a/misoclib/mem/sdram/frontend/memtest.py +++ b/misoclib/mem/sdram/frontend/memtest.py @@ -5,6 +5,7 @@ from migen.actorlib.spi import * from misoclib.mem.sdram.frontend import dma_lasmi + @DecorateModule(InsertReset) @DecorateModule(InsertCE) class LFSR(Module): @@ -28,6 +29,7 @@ class LFSR(Module): memtest_magic = 0x361f + class MemtestWriter(Module): def __init__(self, lasmim): self._magic = CSRStatus(16) @@ -64,6 +66,7 @@ class MemtestWriter(Module): def get_csrs(self): return [self._magic, self._reset, self._shoot] + self._dma.get_csrs() + class MemtestReader(Module): def __init__(self, lasmim): self._magic = CSRStatus(16) @@ -95,6 +98,7 @@ class MemtestReader(Module): def get_csrs(self): return [self._magic, self._reset, self._error_count] + self._dma.get_csrs() + class _LFSRTB(Module): def __init__(self, *args, **kwargs): self.submodules.dut = LFSR(*args, **kwargs) diff --git a/misoclib/mem/sdram/frontend/wishbone2lasmi.py b/misoclib/mem/sdram/frontend/wishbone2lasmi.py index ea849733..d13999e8 100644 --- a/misoclib/mem/sdram/frontend/wishbone2lasmi.py +++ b/misoclib/mem/sdram/frontend/wishbone2lasmi.py @@ -5,6 +5,7 @@ from migen.genlib.fsm import FSM, NextState from migen.genlib.misc import split, displacer, chooser from migen.genlib.record import Record, layout_len + # cachesize (in 32-bit words) is the size of the data store, must be a power of 2 class WB2LASMI(Module, AutoCSR): def __init__(self, cachesize, lasmim): diff --git a/misoclib/mem/sdram/module.py b/misoclib/mem/sdram/module.py index 39b3fa23..ca5a9176 100644 --- a/misoclib/mem/sdram/module.py +++ b/misoclib/mem/sdram/module.py @@ -19,6 +19,7 @@ from math import ceil from migen.fhdl.std import * from misoclib.mem import sdram + class SDRAMModule: def __init__(self, clk_freq, memtype, geom_settings, timing_settings): self.clk_freq = clk_freq @@ -43,6 +44,7 @@ class SDRAMModule: t += clk_period_ns/2 return ceil(t/clk_period_ns) + # SDR class IS42S16160(SDRAMModule): geom_settings = { @@ -63,6 +65,7 @@ class IS42S16160(SDRAMModule): SDRAMModule.__init__(self, clk_freq, "SDR", self.geom_settings, self.timing_settings) + class MT48LC4M16(SDRAMModule): geom_settings = { "nbanks": 4, @@ -81,6 +84,7 @@ class MT48LC4M16(SDRAMModule): SDRAMModule.__init__(self, clk_freq, "SDR", self.geom_settings, self.timing_settings) + class AS4C16M16(SDRAMModule): geom_settings = { "nbanks": 4, @@ -100,6 +104,7 @@ class AS4C16M16(SDRAMModule): SDRAMModule.__init__(self, clk_freq, "SDR", self.geom_settings, self.timing_settings) + # DDR class MT46V32M16(SDRAMModule): geom_settings = { @@ -119,6 +124,7 @@ class MT46V32M16(SDRAMModule): SDRAMModule.__init__(self, clk_freq, "DDR", self.geom_settings, self.timing_settings) + # LPDDR class MT46H32M16(SDRAMModule): geom_settings = { @@ -138,6 +144,7 @@ class MT46H32M16(SDRAMModule): SDRAMModule.__init__(self, clk_freq, "LPDDR", self.geom_settings, self.timing_settings) + # DDR2 class MT47H128M8(SDRAMModule): geom_settings = { @@ -157,6 +164,7 @@ class MT47H128M8(SDRAMModule): SDRAMModule.__init__(self, clk_freq, "DDR2", self.geom_settings, self.timing_settings) + # DDR3 class MT8JTF12864(SDRAMModule): geom_settings = { diff --git a/misoclib/mem/sdram/phy/dfi.py b/misoclib/mem/sdram/phy/dfi.py index 158cfffc..4182faec 100644 --- a/misoclib/mem/sdram/phy/dfi.py +++ b/misoclib/mem/sdram/phy/dfi.py @@ -1,6 +1,7 @@ from migen.fhdl.std import * from migen.genlib.record import * + def phase_cmd_description(addressbits, bankbits): return [ ("address", addressbits, DIR_M_TO_S), @@ -14,6 +15,7 @@ def phase_cmd_description(addressbits, bankbits): ("reset_n", 1, DIR_M_TO_S) ] + def phase_wrdata_description(databits): return [ ("wrdata", databits, DIR_M_TO_S), @@ -21,6 +23,7 @@ def phase_wrdata_description(databits): ("wrdata_mask", databits//8, DIR_M_TO_S) ] + def phase_rddata_description(databits): return [ ("rddata_en", 1, DIR_M_TO_S), @@ -28,12 +31,14 @@ def phase_rddata_description(databits): ("rddata_valid", 1, DIR_S_TO_M) ] + def phase_description(addressbits, bankbits, databits): r = phase_cmd_description(addressbits, bankbits) r += phase_wrdata_description(databits) r += phase_rddata_description(databits) return r + class Interface(Record): def __init__(self, addressbits, bankbits, databits, nphases=1): layout = [("p"+str(i), phase_description(addressbits, bankbits, databits)) for i in range(nphases)] @@ -62,6 +67,7 @@ class Interface(Record): r.append(("dfi_" + field + suffix, getattr(phase, field))) return r + class Interconnect(Module): def __init__(self, master, slave): self.comb += master.connect(slave) diff --git a/misoclib/mem/sdram/phy/dfii.py b/misoclib/mem/sdram/phy/dfii.py index 9f1af130..8495addc 100644 --- a/misoclib/mem/sdram/phy/dfii.py +++ b/misoclib/mem/sdram/phy/dfii.py @@ -3,6 +3,7 @@ from migen.bank.description import * from misoclib.mem.sdram.phy import dfi + class PhaseInjector(Module, AutoCSR): def __init__(self, phase): self._command = CSRStorage(6) # cs, we, cas, ras, wren, rden @@ -35,6 +36,7 @@ class PhaseInjector(Module, AutoCSR): ] self.sync += If(phase.rddata_valid, self._rddata.status.eq(phase.rddata)) + class DFIInjector(Module, AutoCSR): def __init__(self, addressbits, bankbits, databits, nphases=1): inti = dfi.Interface(addressbits, bankbits, databits, nphases) diff --git a/misoclib/mem/sdram/phy/gensdrphy.py b/misoclib/mem/sdram/phy/gensdrphy.py index 10b348ff..6a3e07c1 100644 --- a/misoclib/mem/sdram/phy/gensdrphy.py +++ b/misoclib/mem/sdram/phy/gensdrphy.py @@ -28,6 +28,7 @@ from migen.fhdl.specials import * from misoclib.mem.sdram.phy.dfi import * from misoclib.mem import sdram + class GENSDRPHY(Module): def __init__(self, pads, module): addressbits = flen(pads.a) diff --git a/misoclib/mem/sdram/phy/initsequence.py b/misoclib/mem/sdram/phy/initsequence.py index 1f103d51..7609131e 100644 --- a/misoclib/mem/sdram/phy/initsequence.py +++ b/misoclib/mem/sdram/phy/initsequence.py @@ -1,5 +1,6 @@ from migen.fhdl.std import log2_int + def get_sdram_phy_header(sdram_phy_settings): r = "#ifndef __GENERATED_SDRAM_PHY_H\n#define __GENERATED_SDRAM_PHY_H\n" r += "#include \n#include \n#include \n\n" diff --git a/misoclib/mem/sdram/phy/k7ddrphy.py b/misoclib/mem/sdram/phy/k7ddrphy.py index db8ada18..4f8ee965 100644 --- a/misoclib/mem/sdram/phy/k7ddrphy.py +++ b/misoclib/mem/sdram/phy/k7ddrphy.py @@ -6,6 +6,7 @@ from migen.bank.description import * from misoclib.mem.sdram.phy.dfi import * from misoclib.mem import sdram + class K7DDRPHY(Module, AutoCSR): def __init__(self, pads, module): addressbits = flen(pads.a) diff --git a/misoclib/mem/sdram/phy/s6ddrphy.py b/misoclib/mem/sdram/phy/s6ddrphy.py index 36ed10a4..c270305a 100644 --- a/misoclib/mem/sdram/phy/s6ddrphy.py +++ b/misoclib/mem/sdram/phy/s6ddrphy.py @@ -20,6 +20,7 @@ from migen.genlib.record import * from misoclib.mem.sdram.phy.dfi import * from misoclib.mem import sdram + class S6DDRPHY(Module): def __init__(self, pads, module, rd_bitslip, wr_bitslip, dqs_ddr_alignment): if module.memtype not in ["DDR", "LPDDR", "DDR2"]: diff --git a/misoclib/mem/sdram/phy/simphy.py b/misoclib/mem/sdram/phy/simphy.py index 8b93f687..944d69e1 100644 --- a/misoclib/mem/sdram/phy/simphy.py +++ b/misoclib/mem/sdram/phy/simphy.py @@ -11,6 +11,7 @@ from migen.fhdl.specials import * from misoclib.mem.sdram.phy.dfi import * from misoclib.mem import sdram + class Bank(Module): def __init__(self, data_width, nrows, ncols): self.activate = Signal() @@ -53,6 +54,7 @@ class Bank(Module): ) ] + class DFIPhase(Module): def __init__(self, dfi, n): phase = getattr(dfi, "p"+str(n)) @@ -83,6 +85,7 @@ class DFIPhase(Module): ) ] + class SDRAMPHYSim(Module): def __init__(self, module, settings): addressbits = module.geom_settings.addressbits diff --git a/misoclib/mem/sdram/test/abstract_transactions_lasmi.py b/misoclib/mem/sdram/test/abstract_transactions_lasmi.py index 5ad8d789..b53d46c2 100644 --- a/misoclib/mem/sdram/test/abstract_transactions_lasmi.py +++ b/misoclib/mem/sdram/test/abstract_transactions_lasmi.py @@ -4,6 +4,7 @@ from migen.sim.generic import run_simulation from misoclib.mem.sdram.core import lasmibus + def my_generator(n): bank = n % 4 for x in range(4): @@ -17,6 +18,7 @@ def my_generator(n): print("{0}: Read {1:x} in {2} cycle(s)".format(n, t.data, t.latency)) assert(t.data == 0x1000*bank + 0x100*x) + class MyModel(lasmibus.TargetModel): def read(self, bank, address): r = 0x1000*bank + 0x100*address @@ -27,6 +29,7 @@ class MyModel(lasmibus.TargetModel): print("write to bank {0} address {1:x} data {2:x}".format(bank, address, data)) assert(data == 0x1000*bank + 0x100*address) + class TB(Module): def __init__(self): self.submodules.controller = lasmibus.Target(MyModel(), aw=4, dw=32, nbanks=4, req_queue_size=4, diff --git a/misoclib/mem/sdram/test/bankmachine_tb.py b/misoclib/mem/sdram/test/bankmachine_tb.py index 9c6f4900..ca7a16c5 100644 --- a/misoclib/mem/sdram/test/bankmachine_tb.py +++ b/misoclib/mem/sdram/test/bankmachine_tb.py @@ -6,12 +6,14 @@ from misoclib.mem.sdram.core.lasmicon.bankmachine import * from common import sdram_phy, sdram_geom, sdram_timing, CommandLogger + def my_generator(): for x in range(10): yield True, x for x in range(10): yield False, 128*x + class TB(Module): def __init__(self): self.req = Interface(32, 32, 1, diff --git a/misoclib/mem/sdram/test/common.py b/misoclib/mem/sdram/test/common.py index f4b7dc2b..0f3b9c32 100644 --- a/misoclib/mem/sdram/test/common.py +++ b/misoclib/mem/sdram/test/common.py @@ -9,6 +9,8 @@ MHz = 1000000 clk_freq = (83 + Fraction(1, 3))*MHz clk_period_ns = 1000000000/clk_freq + + def ns(t, margin=True): if margin: t += clk_period_ns/2 @@ -45,6 +47,7 @@ sdram_timing = sdram.TimingSettings( write_time=16 ) + def decode_sdram(ras_n, cas_n, we_n, bank, address): elts = [] if not ras_n and cas_n and we_n: @@ -73,6 +76,7 @@ def decode_sdram(ras_n, cas_n, we_n, bank, address): elts.append("LMR") return elts + class CommandLogger(Module): def __init__(self, cmd, rw=False): self.cmd = cmd @@ -87,6 +91,7 @@ class CommandLogger(Module): print("\t".join(elts)) do_simulation.passive = True + class DFILogger(Module): def __init__(self, dfi): self.dfi = dfi diff --git a/misoclib/mem/sdram/test/lasmicon_df_tb.py b/misoclib/mem/sdram/test/lasmicon_df_tb.py index 5db8befe..6f1a30cf 100644 --- a/misoclib/mem/sdram/test/lasmicon_df_tb.py +++ b/misoclib/mem/sdram/test/lasmicon_df_tb.py @@ -7,6 +7,7 @@ from misoclib.mem.sdram.frontend import dma_lasmi from common import sdram_phy, sdram_geom, sdram_timing, DFILogger + class TB(Module): def __init__(self): self.submodules.ctler = LASMIcon(sdram_phy, sdram_geom, sdram_timing) diff --git a/misoclib/mem/sdram/test/lasmicon_tb.py b/misoclib/mem/sdram/test/lasmicon_tb.py index be4ad1f8..1169898c 100644 --- a/misoclib/mem/sdram/test/lasmicon_tb.py +++ b/misoclib/mem/sdram/test/lasmicon_tb.py @@ -6,24 +6,28 @@ from misoclib.mem.sdram.core.lasmicon import * from common import sdram_phy, sdram_geom, sdram_timing, DFILogger + def my_generator_r(n): for x in range(10): t = TRead(128*n + 48*n*x) yield t print("{0:3}: reads done".format(n)) + def my_generator_w(n): for x in range(10): t = TWrite(128*n + 48*n*x, x) yield t print("{0:3}: writes done".format(n)) + def my_generator(n): if n % 2: return my_generator_w(n // 2) else: return my_generator_r(n // 2) + class TB(Module): def __init__(self): self.submodules.dut = LASMIcon(sdram_phy, sdram_geom, sdram_timing) diff --git a/misoclib/mem/sdram/test/lasmicon_wb.py b/misoclib/mem/sdram/test/lasmicon_wb.py index eb78e5a5..0f5998f9 100644 --- a/misoclib/mem/sdram/test/lasmicon_wb.py +++ b/misoclib/mem/sdram/test/lasmicon_wb.py @@ -11,6 +11,7 @@ from common import sdram_phy, sdram_geom, sdram_timing, DFILogger l2_size = 8192 # in bytes + def my_generator(): for x in range(20): t = TWrite(x, x) @@ -25,6 +26,7 @@ def my_generator(): yield t print(str(t) + " delay=" + str(t.latency)) + class TB(Module): def __init__(self): self.submodules.ctler = LASMIcon(sdram_phy, sdram_geom, sdram_timing) diff --git a/misoclib/mem/sdram/test/minicon_tb.py b/misoclib/mem/sdram/test/minicon_tb.py index d664aecb..86f348a9 100644 --- a/misoclib/mem/sdram/test/minicon_tb.py +++ b/misoclib/mem/sdram/test/minicon_tb.py @@ -15,12 +15,14 @@ clk_freq = 80000000 from math import ceil + def ns(t, margin=True): clk_period_ns = 1000000000/clk_freq if margin: t += clk_period_ns/2 return ceil(t/clk_period_ns) + class MiniconTB(Module): def __init__(self, sdrphy, dfi, sdram_geom, sdram_timing, pads, sdram_clk): @@ -76,6 +78,7 @@ class MiniconTB(Module): while True: yield + class MyTopLevel: def __init__(self, vcd_name=None, vcd_level=1, top_name="top", dut_type="dut", dut_name="dut", diff --git a/misoclib/mem/sdram/test/refresher.py b/misoclib/mem/sdram/test/refresher.py index 00a39887..06367230 100644 --- a/misoclib/mem/sdram/test/refresher.py +++ b/misoclib/mem/sdram/test/refresher.py @@ -7,6 +7,7 @@ from misoclib.mem.sdram.core.lasmicon.refresher import * from common import CommandLogger + class Granter(Module): def __init__(self, req, ack): self.req = req @@ -35,6 +36,7 @@ class Granter(Module): if len(elts) > 1: print("\t".join(elts)) + class TB(Module): def __init__(self): self.submodules.dut = Refresher(13, 2, tRP=3, tREFI=100, tRFC=5) diff --git a/misoclib/others/mxcrg/__init__.py b/misoclib/others/mxcrg/__init__.py index cb0e60e0..c87daa66 100644 --- a/misoclib/others/mxcrg/__init__.py +++ b/misoclib/others/mxcrg/__init__.py @@ -2,6 +2,7 @@ from fractions import Fraction from migen.fhdl.std import * + class MXCRG(Module): def __init__(self, pads, outfreq1x): self.clock_domains.cd_sys = ClockDomain() diff --git a/misoclib/soc/__init__.py b/misoclib/soc/__init__.py index b9b56226..c982339a 100644 --- a/misoclib/soc/__init__.py +++ b/misoclib/soc/__init__.py @@ -9,9 +9,11 @@ from misoclib.com import uart from misoclib.cpu import lm32, mor1kx from misoclib.cpu.peripherals import identifier, timer + def mem_decoder(address, start=26, end=29): return lambda a: a[start:end] == ((address >> (start+2)) & (2**(end-start))-1) + class SoC(Module): csr_map = { "crg": 0, # user diff --git a/misoclib/soc/cpuif.py b/misoclib/soc/cpuif.py index c35c134e..771e515f 100644 --- a/misoclib/soc/cpuif.py +++ b/misoclib/soc/cpuif.py @@ -1,6 +1,7 @@ from migen.fhdl.std import * from migen.bank.description import CSRStatus + def get_cpu_mak(cpu_type): if cpu_type == "lm32": cpuflags = "-mbarrel-shift-enabled -mmultiply-enabled -mdivide-enabled -msign-extend-enabled" @@ -10,9 +11,11 @@ def get_cpu_mak(cpu_type): raise ValueError("Unsupported CPU type: "+cpu_type) return "CPU={}\nCPUFLAGS={}\n".format(cpu_type, cpuflags) + def get_linker_output_format(cpu_type): return "OUTPUT_FORMAT(\"elf32-{}\")\n".format(cpu_type) + def get_linker_regions(regions): r = "MEMORY {\n" for name, origin, length in regions: @@ -20,6 +23,7 @@ def get_linker_regions(regions): r += "}\n" return r + def get_mem_header(regions, flash_boot_address): r = "#ifndef __GENERATED_MEM_H\n#define __GENERATED_MEM_H\n\n" for name, base, size in regions: @@ -29,6 +33,7 @@ def get_mem_header(regions, flash_boot_address): r += "#endif\n" return r + def _get_rw_functions(reg_name, reg_base, nwords, busword, read_only): r = "" @@ -68,6 +73,7 @@ def _get_rw_functions(reg_name, reg_base, nwords, busword, read_only): r += "}\n" return r + def get_csr_header(regions, constants): r = "#ifndef __GENERATED_CSR_H\n#define __GENERATED_CSR_H\n#include \n" for name, origin, busword, obj in regions: @@ -88,6 +94,7 @@ def get_csr_header(regions, constants): r += "\n#endif\n" return r + def get_csr_csv(regions): r = "" for name, origin, busword, obj in regions: diff --git a/misoclib/soc/sdram.py b/misoclib/soc/sdram.py index 05bbdec6..2977bd05 100644 --- a/misoclib/soc/sdram.py +++ b/misoclib/soc/sdram.py @@ -8,6 +8,7 @@ from misoclib.mem.sdram.core.minicon import MiniconSettings from misoclib.mem.sdram.frontend import memtest, wishbone2lasmi from misoclib.soc import SoC + class SDRAMSoC(SoC): csr_map = { "sdram": 8, diff --git a/misoclib/video/dvisampler/__init__.py b/misoclib/video/dvisampler/__init__.py index 2bc38f2f..c376fb01 100644 --- a/misoclib/video/dvisampler/__init__.py +++ b/misoclib/video/dvisampler/__init__.py @@ -11,6 +11,7 @@ from misoclib.video.dvisampler.chansync import ChanSync from misoclib.video.dvisampler.analysis import SyncPolarity, ResolutionDetection, FrameExtraction from misoclib.video.dvisampler.dma import DMA + class DVISampler(Module, AutoCSR): def __init__(self, pads, lasmim, n_dma_slots=2): self.submodules.edid = EDID(pads) diff --git a/misoclib/video/dvisampler/analysis.py b/misoclib/video/dvisampler/analysis.py index 1d2f0847..6c945cea 100644 --- a/misoclib/video/dvisampler/analysis.py +++ b/misoclib/video/dvisampler/analysis.py @@ -7,6 +7,7 @@ from migen.flow.actor import * from misoclib.video.dvisampler.common import channel_layout + class SyncPolarity(Module): def __init__(self): self.valid_i = Signal() @@ -51,6 +52,7 @@ class SyncPolarity(Module): ) ] + class ResolutionDetection(Module, AutoCSR): def __init__(self, nbits=11): self.valid_i = Signal() @@ -105,6 +107,7 @@ class ResolutionDetection(Module, AutoCSR): ) self.specials += MultiReg(vcounter_st, self._vres.status) + class FrameExtraction(Module, AutoCSR): def __init__(self, word_width): # in pix clock domain diff --git a/misoclib/video/dvisampler/chansync.py b/misoclib/video/dvisampler/chansync.py index 7b37593e..0e5d0d6f 100644 --- a/misoclib/video/dvisampler/chansync.py +++ b/misoclib/video/dvisampler/chansync.py @@ -7,6 +7,7 @@ from migen.bank.description import * from misoclib.video.dvisampler.common import channel_layout + class _SyncBuffer(Module): def __init__(self, width, depth): self.din = Signal(width) @@ -37,6 +38,7 @@ class _SyncBuffer(Module): ] self.sync += If(self.re, _inc(consume, depth)) + class ChanSync(Module, AutoCSR): def __init__(self, nchan=3, depth=8): self.valid_i = Signal() @@ -87,6 +89,7 @@ class ChanSync(Module, AutoCSR): ) self.specials += MultiReg(self.chan_synced, self._channels_synced.status) + class _TB(Module): def __init__(self, test_seq_it): self.test_seq_it = test_seq_it diff --git a/misoclib/video/dvisampler/charsync.py b/misoclib/video/dvisampler/charsync.py index ee302d7e..343303e2 100644 --- a/misoclib/video/dvisampler/charsync.py +++ b/misoclib/video/dvisampler/charsync.py @@ -5,6 +5,7 @@ from migen.bank.description import * from misoclib.video.dvisampler.common import control_tokens + class CharSync(Module, AutoCSR): def __init__(self, required_controls=8): self.raw_data = Signal(10) diff --git a/misoclib/video/dvisampler/clocking.py b/misoclib/video/dvisampler/clocking.py index 215cdba6..3c8bc7c9 100644 --- a/misoclib/video/dvisampler/clocking.py +++ b/misoclib/video/dvisampler/clocking.py @@ -2,6 +2,7 @@ from migen.fhdl.std import * from migen.genlib.cdc import MultiReg from migen.bank.description import * + class Clocking(Module, AutoCSR): def __init__(self, pads): self._pll_reset = CSRStorage(reset=1) diff --git a/misoclib/video/dvisampler/datacapture.py b/misoclib/video/dvisampler/datacapture.py index 0649917b..c4c40bbe 100644 --- a/misoclib/video/dvisampler/datacapture.py +++ b/misoclib/video/dvisampler/datacapture.py @@ -2,6 +2,7 @@ from migen.fhdl.std import * from migen.genlib.cdc import MultiReg, PulseSynchronizer from migen.bank.description import * + class DataCapture(Module, AutoCSR): def __init__(self, pad_p, pad_n, ntbits): self.serdesstrobe = Signal() diff --git a/misoclib/video/dvisampler/debug.py b/misoclib/video/dvisampler/debug.py index 472f7384..6cbc5a3b 100644 --- a/misoclib/video/dvisampler/debug.py +++ b/misoclib/video/dvisampler/debug.py @@ -9,6 +9,7 @@ from misoclib.video.dvisampler.edid import EDID from misoclib.video.dvisampler.clocking import Clocking from misoclib.video.dvisampler.datacapture import DataCapture + class RawDVISampler(Module, AutoCSR): def __init__(self, pads, asmiport): self.submodules.edid = EDID(pads) diff --git a/misoclib/video/dvisampler/decoding.py b/misoclib/video/dvisampler/decoding.py index 0ceb2827..db0b48e1 100644 --- a/misoclib/video/dvisampler/decoding.py +++ b/misoclib/video/dvisampler/decoding.py @@ -3,6 +3,7 @@ from migen.genlib.record import Record from misoclib.video.dvisampler.common import control_tokens, channel_layout + class Decoding(Module): def __init__(self): self.valid_i = Signal() diff --git a/misoclib/video/dvisampler/dma.py b/misoclib/video/dvisampler/dma.py index d811ab7f..5f477526 100644 --- a/misoclib/video/dvisampler/dma.py +++ b/misoclib/video/dvisampler/dma.py @@ -6,6 +6,7 @@ from migen.flow.actor import * from misoclib.mem.sdram.frontend import dma_lasmi + # Slot status: EMPTY=0 LOADED=1 PENDING=2 class _Slot(Module, AutoCSR): def __init__(self, addr_bits, alignment_bits): @@ -30,6 +31,7 @@ class _Slot(Module, AutoCSR): self.ev_source.trigger.eq(self._status.storage[1]) ] + class _SlotArray(Module, AutoCSR): def __init__(self, nslots, addr_bits, alignment_bits): self.submodules.ev = EventManager() @@ -58,6 +60,7 @@ class _SlotArray(Module, AutoCSR): self.comb += [slot.address_reached.eq(self.address_reached) for slot in slots] self.comb += [slot.address_done.eq(self.address_done & (current_slot == n)) for n, slot in enumerate(slots)] + class DMA(Module): def __init__(self, lasmim, nslots): bus_aw = lasmim.aw diff --git a/misoclib/video/dvisampler/edid.py b/misoclib/video/dvisampler/edid.py index efe54d38..16f18753 100644 --- a/misoclib/video/dvisampler/edid.py +++ b/misoclib/video/dvisampler/edid.py @@ -16,6 +16,7 @@ _default_edid = [ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x34, ] + class EDID(Module, AutoCSR): def __init__(self, pads, default=_default_edid): self._hpd_notif = CSRStatus() diff --git a/misoclib/video/dvisampler/wer.py b/misoclib/video/dvisampler/wer.py index f75d4452..17399c23 100644 --- a/misoclib/video/dvisampler/wer.py +++ b/misoclib/video/dvisampler/wer.py @@ -5,6 +5,7 @@ from migen.genlib.cdc import PulseSynchronizer from misoclib.video.dvisampler.common import control_tokens + class WER(Module, AutoCSR): def __init__(self, period_bits=24): self.data = Signal(10) diff --git a/misoclib/video/framebuffer/__init__.py b/misoclib/video/framebuffer/__init__.py index 54f25d81..10ea2015 100644 --- a/misoclib/video/framebuffer/__init__.py +++ b/misoclib/video/framebuffer/__init__.py @@ -8,6 +8,7 @@ from misoclib.mem.sdram.frontend import dma_lasmi from misoclib.video.framebuffer.format import bpp, pixel_layout, FrameInitiator, VTG from misoclib.video.framebuffer.phy import Driver + class Framebuffer(Module, AutoCSR): def __init__(self, pads_vga, pads_dvi, lasmim): pack_factor = lasmim.dw//bpp diff --git a/misoclib/video/framebuffer/dvi.py b/misoclib/video/framebuffer/dvi.py index ac51493e..65060e31 100644 --- a/misoclib/video/framebuffer/dvi.py +++ b/misoclib/video/framebuffer/dvi.py @@ -3,6 +3,7 @@ from migen.genlib.misc import optree control_tokens = [0b1101010100, 0b0010101011, 0b0101010100, 0b1010101011] + class Encoder(Module): def __init__(self): self.d = Signal(8) @@ -83,6 +84,7 @@ class Encoder(Module): cnt.eq(0) ) + class _EncoderSerializer(Module): def __init__(self, serdesstrobe, pad_p, pad_n): self.submodules.encoder = RenameClockDomains(Encoder(), "pix") @@ -156,6 +158,7 @@ class PHY(Module): self.es2.de.eq(self.de), ] + class _EncoderTB(Module): def __init__(self, inputs): self.outs = [] @@ -177,9 +180,11 @@ class _EncoderTB(Module): if selfp.simulator.cycle_counter > 4: self.outs.append(selfp.dut.out) + def _bit(i, n): return (i >> n) & 1 + def _decode_tmds(b): try: c = control_tokens.index(b) diff --git a/misoclib/video/framebuffer/format.py b/misoclib/video/framebuffer/format.py index 5b177644..e3a3931f 100644 --- a/misoclib/video/framebuffer/format.py +++ b/misoclib/video/framebuffer/format.py @@ -16,6 +16,8 @@ pixel_layout_s = [ ("g", bpc), ("b", bpc) ] + + def pixel_layout(pack_factor): return [("p"+str(i), pixel_layout_s) for i in range(pack_factor)] @@ -25,12 +27,15 @@ phy_layout_s = [ ("g", bpc_phy), ("b", bpc_phy) ] + + def phy_layout(pack_factor): r = [("hsync", 1), ("vsync", 1), ("de", 1)] for i in range(pack_factor): r.append(("p"+str(i), phy_layout_s)) return r + class FrameInitiator(spi.SingleGenerator): def __init__(self, bus_aw, pack_factor, ndmas=1): h_alignment_bits = log2_int(pack_factor) @@ -59,6 +64,7 @@ class FrameInitiator(spi.SingleGenerator): def dma_subr(self, i=0): return ["length", "base"+str(i)] + class VTG(Module): def __init__(self, pack_factor): hbits_dyn = _hbits - log2_int(pack_factor) diff --git a/misoclib/video/framebuffer/phy.py b/misoclib/video/framebuffer/phy.py index 297fc025..c55efde3 100644 --- a/misoclib/video/framebuffer/phy.py +++ b/misoclib/video/framebuffer/phy.py @@ -7,6 +7,7 @@ from migen.flow.actor import * from misoclib.video.framebuffer.format import bpc_phy, phy_layout from misoclib.video.framebuffer import dvi + class _FIFO(Module): def __init__(self, pack_factor): self.phy = Sink(phy_layout(pack_factor)) @@ -48,6 +49,7 @@ class _FIFO(Module): ) self.comb += fifo.re.eq(unpack_counter == (pack_factor - 1)) + # This assumes a 50MHz base clock class _Clocking(Module, AutoCSR): def __init__(self, pads_vga, pads_dvi): @@ -189,6 +191,7 @@ class _Clocking(Module, AutoCSR): self.specials += Instance("OBUFDS", i_I=dvi_clk_se, o_O=pads_dvi.clk_p, o_OB=pads_dvi.clk_n) + class Driver(Module, AutoCSR): def __init__(self, pack_factor, pads_vga, pads_dvi): fifo = _FIFO(pack_factor) diff --git a/targets/de0nano.py b/targets/de0nano.py index 8a6802fc..a10d4f04 100644 --- a/targets/de0nano.py +++ b/targets/de0nano.py @@ -5,6 +5,7 @@ from misoclib.mem.sdram.phy import gensdrphy from misoclib.mem.sdram.core.lasmicon import LASMIconSettings from misoclib.soc.sdram import SDRAMSoC + class _PLL(Module): def __init__(self, period_in, name, phase_shift, operation_mode): self.clk_in = Signal() @@ -43,6 +44,7 @@ class _PLL(Module): i_scanwrite=0 ) + class _CRG(Module): def __init__(self, platform): self.clock_domains.cd_sys = ClockDomain() @@ -76,6 +78,7 @@ class _CRG(Module): self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk) + class BaseSoC(SDRAMSoC): default_platform = "de0nano" diff --git a/targets/kc705.py b/targets/kc705.py index e5ceba10..fd4f461c 100644 --- a/targets/kc705.py +++ b/targets/kc705.py @@ -11,6 +11,7 @@ from misoclib.soc.sdram import SDRAMSoC from misoclib.com.liteeth.phy import LiteEthPHY from misoclib.com.liteeth.mac import LiteEthMAC + class _CRG(Module): def __init__(self, platform): self.clock_domains.cd_sys = ClockDomain() @@ -67,6 +68,7 @@ class _CRG(Module): ) self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset) + class BaseSoC(SDRAMSoC): default_platform = "kc705" @@ -98,6 +100,7 @@ class BaseSoC(SDRAMSoC): self.flash_boot_address = 0xb00000 self.register_rom(self.spiflash.bus) + class MiniSoC(BaseSoC): csr_map = { "ethphy": 18, diff --git a/targets/minispartan6.py b/targets/minispartan6.py index dd0a287a..42d49184 100644 --- a/targets/minispartan6.py +++ b/targets/minispartan6.py @@ -8,6 +8,7 @@ from misoclib.mem.sdram.phy import gensdrphy from misoclib.mem.sdram.core.lasmicon import LASMIconSettings from misoclib.soc.sdram import SDRAMSoC + class _CRG(Module): def __init__(self, platform, clk_freq): self.clock_domains.cd_sys = ClockDomain() @@ -58,6 +59,7 @@ class _CRG(Module): i_C0=self.cd_sys.clk, i_C1=~self.cd_sys.clk, o_Q=platform.request("sdram_clock")) + class BaseSoC(SDRAMSoC): default_platform = "minispartan6" diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py index 30af6423..a9aa1c4c 100644 --- a/targets/mlabs_video.py +++ b/targets/mlabs_video.py @@ -17,6 +17,7 @@ from misoclib.com import gpio from misoclib.com.liteeth.phy import LiteEthPHY from misoclib.com.liteeth.mac import LiteEthMAC + class _MXClockPads: def __init__(self, platform): self.clk50 = platform.request("clk50") @@ -30,6 +31,7 @@ class _MXClockPads: self.ddr_clk_p = ddram_clock.p self.ddr_clk_n = ddram_clock.n + class BaseSoC(SDRAMSoC): default_platform = "mixxeo" # also supports m1 @@ -64,6 +66,7 @@ INST "mxcrg/rd_bufpll" LOC = "BUFPLL_X0Y3"; """) platform.add_source_dir(os.path.join("misoclib", "others", "mxcrg")) + class MiniSoC(BaseSoC): csr_map = { "ethphy": 16, @@ -95,6 +98,7 @@ class MiniSoC(BaseSoC): self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"]+0x80000000, 0x2000) + def get_vga_dvi(platform): try: pads_vga = platform.request("vga_out") @@ -110,6 +114,7 @@ PIN "dviout_pix_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE; """) return pads_vga, pads_dvi + def add_vga_tig(platform, fb): platform.add_platform_command(""" NET "{vga_clk}" TNM_NET = "GRPvga_clk"; @@ -118,6 +123,7 @@ TIMESPEC "TSise_sucks1" = FROM "GRPvga_clk" TO "GRPsys_clk" TIG; TIMESPEC "TSise_sucks2" = FROM "GRPsys_clk" TO "GRPvga_clk" TIG; """, vga_clk=fb.driver.clocking.cd_pix.clk) + class FramebufferSoC(MiniSoC): csr_map = { "fb": 18, diff --git a/targets/pipistrello.py b/targets/pipistrello.py index a5a4d63f..43aea7d9 100644 --- a/targets/pipistrello.py +++ b/targets/pipistrello.py @@ -9,6 +9,7 @@ from misoclib.mem.sdram.core.lasmicon import LASMIconSettings from misoclib.mem.flash import spiflash from misoclib.soc.sdram import SDRAMSoC + class _CRG(Module): def __init__(self, platform, clk_freq): self.clock_domains.cd_sys = ClockDomain() @@ -86,6 +87,7 @@ class _CRG(Module): i_C0=clk_sdram_half_shifted, i_C1=~clk_sdram_half_shifted, o_Q=clk.n) + class BaseSoC(SDRAMSoC): default_platform = "pipistrello" diff --git a/targets/ppro.py b/targets/ppro.py index d93341c2..6918302c 100644 --- a/targets/ppro.py +++ b/targets/ppro.py @@ -9,6 +9,7 @@ from misoclib.mem.sdram.core.lasmicon import LASMIconSettings from misoclib.mem.flash import spiflash from misoclib.soc.sdram import SDRAMSoC + class _CRG(Module): def __init__(self, platform, clk_freq): self.clock_domains.cd_sys = ClockDomain() @@ -59,6 +60,7 @@ class _CRG(Module): i_C0=self.cd_sys.clk, i_C1=~self.cd_sys.clk, o_Q=platform.request("sdram_clock")) + class BaseSoC(SDRAMSoC): default_platform = "papilio_pro" diff --git a/targets/simple.py b/targets/simple.py index 56313901..e89fd5ec 100644 --- a/targets/simple.py +++ b/targets/simple.py @@ -6,6 +6,7 @@ from misoclib.soc import SoC, mem_decoder from misoclib.com.liteeth.phy import LiteEthPHY from misoclib.com.liteeth.mac import LiteEthMAC + class BaseSoC(SoC): def __init__(self, platform, **kwargs): SoC.__init__(self, platform, @@ -15,6 +16,7 @@ class BaseSoC(SoC): **kwargs) self.submodules.crg = CRG(platform.request(platform.default_clk_name)) + class MiniSoC(BaseSoC): csr_map = { "ethphy": 20, diff --git a/targets/versa.py b/targets/versa.py index 55cfb286..2ea16ac2 100644 --- a/targets/versa.py +++ b/targets/versa.py @@ -4,6 +4,7 @@ from migen.genlib.io import CRG from misoclib.soc import SoC + class BaseSoC(SoC): default_platform = "versa" def __init__(self, platform, **kwargs): diff --git a/tools/flterm.py b/tools/flterm.py index ea87cf9c..c8dd9e23 100644 --- a/tools/flterm.py +++ b/tools/flterm.py @@ -54,12 +54,14 @@ crc16_table = [ 0x6E17, 0x7E36, 0x4E55, 0x5E74, 0x2E93, 0x3EB2, 0x0ED1, 0x1EF0 ] + def crc16(l): crc = 0 for d in l: crc = crc16_table[((crc >> 8) ^ d) & 0xff] ^ (crc << 8) return crc + class SFLFrame: def __init__(self): self.length = None @@ -86,6 +88,7 @@ class SFLFrame: for d in self.payload: self.raw.append(d) + def get_file_data(filename): with open(filename, "rb") as f: data = [] @@ -96,6 +99,7 @@ def get_file_data(filename): data.append(int.from_bytes(w, "big")) return data + class Flterm: def __init__(self, kernel_image, kernel_address): self.kernel_image = kernel_image @@ -268,6 +272,7 @@ class Flterm: if not writer_only: self.reader_thread.join() + def _get_args(): parser = argparse.ArgumentParser() parser.add_argument("--port", default="2", help="serial port")