From: Stefan Biereigel <stefan@biereigel.de>
Date: Mon, 27 May 2019 16:45:54 +0000 (+0200)
Subject: reformat wand/wor test
X-Git-Tag: yosys-0.9~102^2~2^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f68b658b4b88b9a71377d19d7d693f07eccf433e;p=yosys.git

reformat wand/wor test
---

diff --git a/tests/various/wandwor.v b/tests/various/wandwor.v
index d1dca6269..fc072daa3 100644
--- a/tests/various/wandwor.v
+++ b/tests/various/wandwor.v
@@ -1,34 +1,33 @@
 module a(Q);
-    output wire Q;
-
-    assign Q = 0;
+	output wire Q = 0;
 endmodule
 
 module b(D);
-    input wire D;
+	input wire D;
 endmodule
 
 module c;
-    wor D;
-    assign D = 1;
-    assign D = 0;
-    assign D = 1;
-    assign D = 0;
+	// net definitions
+	wor D;
+	wand E;
+
+	// assignments to wired logic nets
+	assign D = 1;
+	assign D = 0;
+	assign D = 1;
+	assign D = 0;
 
+	// assignments of wired logic nets to wires
+	wire F = E;
 
-    wand E;
-    
-    genvar i;
-    for (i = 0; i < 3; i = i + 1)
-    begin :genloop
-        a a_inst (
-            .Q(E)
-        );
-        
-        b b_inst (
-            .D(E)
-        );
-    end
+	genvar i;
+	for (i = 0; i < 3; i = i + 1)
+	begin : genloop
+		// connection of module outputs
+		a a_inst (.Q(E));
 
+		// connection of module inputs
+		b b_inst (.D(E));
+	end
 endmodule