From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 12 Oct 2018 15:20:27 +0000 (+0100)
Subject: add frs2 redirect
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f68fc475550820a273657676424c7e97886de2c9;p=riscv-isa-sim.git

add frs2 redirect
---

diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index 283543a..05c55d1 100644
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -33,3 +33,8 @@ freg_t sv_proc_t::get_frs1()
     return READ_FREG(insn->rs1());
 }
 
+freg_t sv_proc_t::get_frs2()
+{
+    return READ_FREG(insn->rs2());
+}
+
diff --git a/riscv/sv_insn_redirect.h b/riscv/sv_insn_redirect.h
index 64338e0..95550ba 100644
--- a/riscv/sv_insn_redirect.h
+++ b/riscv/sv_insn_redirect.h
@@ -9,11 +9,13 @@
 #undef RS2
 #undef RS3
 #undef FRS1
+#undef FRS2
 
 class processor_t;
 class insn_t;
 
 #define FRS1 get_frs1()
+#define FRS2 get_frs2()
 #define RS1 get_rs1()
 #define RS2 get_rs2()
 #define RS3 get_rs3()
@@ -48,6 +50,7 @@ public:
     reg_t get_rs3();
 
     freg_t get_frs1();
+    freg_t get_frs2();
 
 #include "sv_insn_decl.h"
 };