From: colepoirier <colepoirier@gmail.com>
Date: Tue, 26 May 2020 01:04:37 +0000 (-0700)
Subject: First attempt at implementing block access rd and wr regfile port onto
X-Git-Tag: div_pipeline~819
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f690846a710a75ea8ed809a7b7a4351236210fc9;p=soc.git

First attempt at implementing block access rd and wr regfile port onto
an array-based regfile
---

diff --git a/src/soc/regfile/virtual_port.py b/src/soc/regfile/virtual_port.py
new file mode 100644
index 00000000..7f02ecc2
--- /dev/null
+++ b/src/soc/regfile/virtual_port.py
@@ -0,0 +1,25 @@
+from nmigen.compat.sim import run_simulation
+from nmigen.cli import verilog, rtlil
+
+from nmigen import Cat, Const, Array, Signal, Elaboratable, Module
+from nmutil.iocontrol import RecordObject
+
+from soc.regfile import RegFileArray
+
+
+class VirtualPort(RegFileArray):
+    def __init__(self, bitwidth, n_regs):
+        self.bitwidth = bitwidth
+        self.nregs = n_regs
+        self.regwidth = bitwidth / n_regs
+        self.w_ports = [ self.write_port(f"{i}") for i in range(n_regs) ]
+        self.r_ports = [ self.read_port(f"{i}") for i in range(n_regs) ]
+        self.extra_wr.append(RecordObject([("ren", nregs), ("data_o", bitwidth, name="extra")]))
+        self.extra_rd.append(RecordObject([("ren", nregs), ("data_o", bitwidth, name="extra")]))
+
+    def elaborate(self, platform):
+        m = Module()
+        with m.If(self._get_en_sig(extra, "ren") == 0)
+            pass
+        with m.Else()
+            "send data through the corresponding lower indexed ports"