From: Luke Kenneth Casson Leighton Date: Thu, 2 Mar 2023 13:06:29 +0000 (+0000) Subject: ls003: add to motivation (about dsld and dsrd), X-Git-Tag: opf_rfc_ls001_v3~207 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f69dec9cf3eff82a11d4444f52ed83be6041ede0;p=libreriscv.git ls003: add to motivation (about dsld and dsrd), correction of "warm words" for dsld and dsrd, proposing four instructions not two --- diff --git a/openpower/sv/rfc/ls003.mdwn b/openpower/sv/rfc/ls003.mdwn index 43e231ce3..f5204c320 100644 --- a/openpower/sv/rfc/ls003.mdwn +++ b/openpower/sv/rfc/ls003.mdwn @@ -45,7 +45,7 @@ Instructions added **Impact on processor**: ``` - Addition of two new GPR-based instructions + Addition of four new GPR-based instructions ``` **Impact on software**: @@ -69,6 +69,9 @@ Instructions added * Similar to `divdeu`, and has similar advantages to `maddedu`, Modulo result is available with the quotient in a single instruction allowing highly-efficient arbitrary-length big-integer division. +* Combining at least three instructions into one, the `dsld` and `dsrd` + instructions make shifting an arbitrary-length big-integer vector by + a scalar 64-bit quantity highly efficient. **Notes and Observations**: @@ -275,11 +278,11 @@ Special Registers Altered: The contents of register RA are shifted left the number of bits specified by (RB) 58:63. The same number of -shifted bits are taken from the **right** (MSB) end of register -RC and placed into the LSBs of the result, RT. -Additionally, the MSB bits of register RA that would normally +shifted bits are taken from the **right** (LSB) end of register +RC and placed into the *rightmost* (LSB) end of the result, RT. +Additionally, the MSB (leftmost) bits of register RA that would normally be discarded by a 64-bit left shift are placed into the -MSBs of RS. +LSBs of RS. When Rc=1, and the value in RS is nonzero, the overflow flag is raised in CR0. All other bits of CR0 @@ -318,7 +321,7 @@ The contents of register RA are shifted right the number of bits specified by (RB) 58:63. The same number of shifted bits are taken from the **left** (LSB) end of register RC and placed into the MSBs of the result, RT. -Additionally, the MSB bits of register RA that would normally +Additionally, the LSB (rightmost) bits of register RA that would normally be discarded by a 64-bit right shift are placed into the MSBs of RS.