From: Romain Naour Date: Sun, 15 Mar 2020 16:18:46 +0000 (+0100) Subject: package/gcc: bump 9.x series to version 9.3.0 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f6bf6281f018b4cc0ebb11227f68ac59001781ec;p=buildroot.git package/gcc: bump 9.x series to version 9.3.0 Remove upstream patch [1] Rebase and rename 0002-xtensa-fix-PR-target-91880.patch and 0003-or1k-Fix-issue-with-set_got-clobbering-LR-r9.patch Tested using gitlab with Qemu runtime testing series [2] [3]. [1] https://gcc.gnu.org/git/?p=gcc.git;a=commitdiff;h=2e1e7ad18e121663082525a872f0d6fb32db4535 [2] https://gitlab.com/kubu93/buildroot/pipelines/125828238 [3] http://patchwork.ozlabs.org/project/buildroot/list/?series=159088 See: https://gcc.gnu.org/pipermail/gcc-announce/2020/000161.html Signed-off-by: Romain Naour Signed-off-by: Thomas Petazzoni --- diff --git a/package/gcc/9.2.0/0001-xtensa-backport-fix-for-PR-target-90922.patch b/package/gcc/9.2.0/0001-xtensa-backport-fix-for-PR-target-90922.patch deleted file mode 100644 index bc1d13a9e4..0000000000 --- a/package/gcc/9.2.0/0001-xtensa-backport-fix-for-PR-target-90922.patch +++ /dev/null @@ -1,43 +0,0 @@ -From a592242578e573778241cae6d3928c064dcdfda4 Mon Sep 17 00:00:00 2001 -From: jcmvbkbc -Date: Tue, 18 Jun 2019 22:19:12 +0000 -Subject: [PATCH] xtensa: fix for PR target/90922 - -Stack pointer adjustment code in prologue missed a case of no -callee-saved registers and a stack frame size bigger than 128 bytes. -Handle that case. - -This fixes the following gcc tests with call0 ABI: - gcc.c-torture/execute/stdarg-2.c - gcc.dg/torture/pr55882.c - gcc.dg/torture/pr57569.c - -gcc/ -2019-06-18 Max Filippov - - * config/xtensa/xtensa.c (xtensa_expand_prologue): Add stack - pointer adjustment for the case of no callee-saved registers and - stack frame bigger than 128 bytes. - -Signed-off-by: Max Filippov ---- - gcc/config/xtensa/xtensa.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/gcc/config/xtensa/xtensa.c b/gcc/config/xtensa/xtensa.c -index 19bd616d67f6..ee5612441e25 100644 ---- a/gcc/config/xtensa/xtensa.c -+++ b/gcc/config/xtensa/xtensa.c -@@ -2865,7 +2865,8 @@ xtensa_expand_prologue (void) - gen_rtx_SET (mem, reg)); - } - } -- if (total_size > 1024) -+ if (total_size > 1024 -+ || (!callee_save_size && total_size > 128)) - { - rtx tmp_reg = gen_rtx_REG (Pmode, A9_REG); - emit_move_insn (tmp_reg, GEN_INT (total_size - --- -2.11.0 - diff --git a/package/gcc/9.2.0/0002-xtensa-fix-PR-target-91880.patch b/package/gcc/9.2.0/0002-xtensa-fix-PR-target-91880.patch deleted file mode 100644 index 0dbf1124a3..0000000000 --- a/package/gcc/9.2.0/0002-xtensa-fix-PR-target-91880.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 7c11710230921246156aecc20eb4b6ccaeaaa473 Mon Sep 17 00:00:00 2001 -From: Max Filippov -Date: Tue, 24 Sep 2019 04:15:17 -0700 -Subject: [PATCH] xtensa: fix PR target/91880 - -Xtensa hwloop_optimize segfaults when zero overhead loop is about to be -inserted as the first instruction of the function. -Insert zero overhead loop instruction into new basic block before the -loop when basic block that precedes the loop is empty. - -2019-09-26 Max Filippov -gcc/ - * config/xtensa/xtensa.c (hwloop_optimize): Insert zero overhead - loop instruction into new basic block before the loop when basic - block that precedes the loop is empty. - -Signed-off-by: Max Filippov ---- -Backported from: r276166 - - gcc/config/xtensa/xtensa.c | 5 ++-- - 1 file changed, 3 insertions(+), 2 deletions(-) - -diff --git a/gcc/config/xtensa/xtensa.c b/gcc/config/xtensa/xtensa.c -index ee5612441e25..2527468d57db 100644 ---- a/gcc/config/xtensa/xtensa.c -+++ b/gcc/config/xtensa/xtensa.c -@@ -4235,7 +4235,9 @@ hwloop_optimize (hwloop_info loop) - - seq = get_insns (); - -- if (!single_succ_p (entry_bb) || vec_safe_length (loop->incoming) > 1) -+ entry_after = BB_END (entry_bb); -+ if (!single_succ_p (entry_bb) || vec_safe_length (loop->incoming) > 1 -+ || !entry_after) - { - basic_block new_bb; - edge e; -@@ -4256,7 +4258,6 @@ hwloop_optimize (hwloop_info loop) - } - else - { -- entry_after = BB_END (entry_bb); - while (DEBUG_INSN_P (entry_after) - || (NOTE_P (entry_after) - && NOTE_KIND (entry_after) != NOTE_INSN_BASIC_BLOCK)) --- -2.11.0 - diff --git a/package/gcc/9.2.0/0003-or1k-Fix-issue-with-set_got-clobbering-LR-r9.patch b/package/gcc/9.2.0/0003-or1k-Fix-issue-with-set_got-clobbering-LR-r9.patch deleted file mode 100644 index bdde2ce762..0000000000 --- a/package/gcc/9.2.0/0003-or1k-Fix-issue-with-set_got-clobbering-LR-r9.patch +++ /dev/null @@ -1,105 +0,0 @@ -From 94c7d630348671b781368d9270514dcf6c34e0c9 Mon Sep 17 00:00:00 2001 -From: shorne -Date: Sat, 31 Aug 2019 06:00:56 +0000 -Subject: [PATCH] or1k: Fix issue with set_got clobbering LR (r9) - -When compiling glibc we found that the GOT register was being allocated -r9 when the instruction was still set_got_tmp. That is a problem -because r9 is the Link Register (LR) in OpenRISC which is used/clobbered -in set_got. We cannot use r9 as the GOT register. Also, we cannot -simply say set_got_tmp clobbers r9 as this is the reason for having the -temporary set_got_tmp. - -Fix by using a register class constraint that does not allow r9 during -register allocation. - -gcc/ChangeLog: - - * config/or1k/constraints.md (t): New constraint. - * config/or1k/or1k.h (GOT_REGS): New register class. - * config/or1k/or1k.md (set_got_tmp, set_got): Use t contraint. - -git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@275242 138bc75d-0d04-0410-961f-82ee72b054a4 -(cherry picked from commit 5b9471ffca25d39635680516ba2ff85295480fc3) -Signed-off-by: Romain Naour ---- - gcc/config/or1k/constraints.md | 4 ++++ - gcc/config/or1k/or1k.h | 3 +++ - gcc/config/or1k/or1k.md | 4 ++-- - 3 files changed, 9 insertions(+), 2 deletions(-) - -diff --git a/gcc/config/or1k/constraints.md b/gcc/config/or1k/constraints.md -index 93da8c058c6..a16b749008f 100644 ---- a/gcc/config/or1k/constraints.md -+++ b/gcc/config/or1k/constraints.md -@@ -24,6 +24,7 @@ - - ; We use: - ; c - sibcall registers -+; t - got address registers (excludes LR (r9) which is clobbered by set_got) - ; I - constant signed 16-bit - ; K - constant unsigned 16-bit - ; M - constant signed 16-bit shifted left 16-bits (l.movhi) -@@ -32,6 +33,9 @@ - (define_register_constraint "c" "SIBCALL_REGS" - "Registers which can hold a sibling call address") - -+(define_register_constraint "t" "GOT_REGS" -+ "Registers which can be used to store the Global Offset Table (GOT) address.") -+ - ;; Immediates - (define_constraint "I" - "A signed 16-bit immediate in the range -32768 to 32767." -diff --git a/gcc/config/or1k/or1k.h b/gcc/config/or1k/or1k.h -index 6dda230f217..feee702d89c 100644 ---- a/gcc/config/or1k/or1k.h -+++ b/gcc/config/or1k/or1k.h -@@ -189,6 +189,7 @@ enum reg_class - { - NO_REGS, - SIBCALL_REGS, -+ GOT_REGS, - GENERAL_REGS, - FLAG_REGS, - ALL_REGS, -@@ -200,6 +201,7 @@ enum reg_class - #define REG_CLASS_NAMES { \ - "NO_REGS", \ - "SIBCALL_REGS", \ -+ "GOT_REGS", \ - "GENERAL_REGS", \ - "FLAG_REGS", \ - "ALL_REGS" } -@@ -212,6 +214,7 @@ enum reg_class - #define REG_CLASS_CONTENTS \ - { { 0x00000000, 0x00000000 }, \ - { SIBCALL_REGS_MASK, 0 }, \ -+ { 0xfffffdff, 0x00000000 }, \ - { 0xffffffff, 0x00000003 }, \ - { 0x00000000, 0x00000004 }, \ - { 0xffffffff, 0x00000007 } \ -diff --git a/gcc/config/or1k/or1k.md b/gcc/config/or1k/or1k.md -index 2dad51cd46b..88f3f02630f 100644 ---- a/gcc/config/or1k/or1k.md -+++ b/gcc/config/or1k/or1k.md -@@ -595,7 +595,7 @@ - ;; set_got pattern below. This works because the set_got_tmp insn is the - ;; first insn in the stream and that it isn't moved during RA. - (define_insn "set_got_tmp" -- [(set (match_operand:SI 0 "register_operand" "=r") -+ [(set (match_operand:SI 0 "register_operand" "=t") - (unspec_volatile:SI [(const_int 0)] UNSPECV_SET_GOT))] - "" - { -@@ -604,7 +604,7 @@ - - ;; The insn to initialize the GOT. - (define_insn "set_got" -- [(set (match_operand:SI 0 "register_operand" "=r") -+ [(set (match_operand:SI 0 "register_operand" "=t") - (unspec:SI [(const_int 0)] UNSPEC_SET_GOT)) - (clobber (reg:SI LR_REGNUM))] - "" --- -2.23.0 - diff --git a/package/gcc/9.3.0/0001-xtensa-fix-PR-target-91880.patch b/package/gcc/9.3.0/0001-xtensa-fix-PR-target-91880.patch new file mode 100644 index 0000000000..4e5aea2c7b --- /dev/null +++ b/package/gcc/9.3.0/0001-xtensa-fix-PR-target-91880.patch @@ -0,0 +1,50 @@ +From 0a59aa440a4c125b81504c777b066ae4eb1f09f0 Mon Sep 17 00:00:00 2001 +From: Max Filippov +Date: Tue, 24 Sep 2019 04:15:17 -0700 +Subject: [PATCH] xtensa: fix PR target/91880 + +Xtensa hwloop_optimize segfaults when zero overhead loop is about to be +inserted as the first instruction of the function. +Insert zero overhead loop instruction into new basic block before the +loop when basic block that precedes the loop is empty. + +2019-09-26 Max Filippov +gcc/ + * config/xtensa/xtensa.c (hwloop_optimize): Insert zero overhead + loop instruction into new basic block before the loop when basic + block that precedes the loop is empty. + +Signed-off-by: Max Filippov +Signed-off-by: Romain Naour +--- +Backported from: r276166 + + gcc/config/xtensa/xtensa.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +diff --git a/gcc/config/xtensa/xtensa.c b/gcc/config/xtensa/xtensa.c +index ee5612441e2..2527468d57d 100644 +--- a/gcc/config/xtensa/xtensa.c ++++ b/gcc/config/xtensa/xtensa.c +@@ -4235,7 +4235,9 @@ hwloop_optimize (hwloop_info loop) + + seq = get_insns (); + +- if (!single_succ_p (entry_bb) || vec_safe_length (loop->incoming) > 1) ++ entry_after = BB_END (entry_bb); ++ if (!single_succ_p (entry_bb) || vec_safe_length (loop->incoming) > 1 ++ || !entry_after) + { + basic_block new_bb; + edge e; +@@ -4256,7 +4258,6 @@ hwloop_optimize (hwloop_info loop) + } + else + { +- entry_after = BB_END (entry_bb); + while (DEBUG_INSN_P (entry_after) + || (NOTE_P (entry_after) + && NOTE_KIND (entry_after) != NOTE_INSN_BASIC_BLOCK)) +-- +2.24.1 + diff --git a/package/gcc/9.3.0/0002-or1k-Fix-issue-with-set_got-clobbering-LR-r9.patch b/package/gcc/9.3.0/0002-or1k-Fix-issue-with-set_got-clobbering-LR-r9.patch new file mode 100644 index 0000000000..e40b96fe0f --- /dev/null +++ b/package/gcc/9.3.0/0002-or1k-Fix-issue-with-set_got-clobbering-LR-r9.patch @@ -0,0 +1,105 @@ +From 1383012ae409ed91903b2b76ee15137bc1f89900 Mon Sep 17 00:00:00 2001 +From: shorne +Date: Sat, 31 Aug 2019 06:00:56 +0000 +Subject: [PATCH] or1k: Fix issue with set_got clobbering LR (r9) + +When compiling glibc we found that the GOT register was being allocated +r9 when the instruction was still set_got_tmp. That is a problem +because r9 is the Link Register (LR) in OpenRISC which is used/clobbered +in set_got. We cannot use r9 as the GOT register. Also, we cannot +simply say set_got_tmp clobbers r9 as this is the reason for having the +temporary set_got_tmp. + +Fix by using a register class constraint that does not allow r9 during +register allocation. + +gcc/ChangeLog: + + * config/or1k/constraints.md (t): New constraint. + * config/or1k/or1k.h (GOT_REGS): New register class. + * config/or1k/or1k.md (set_got_tmp, set_got): Use t contraint. + +git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@275242 138bc75d-0d04-0410-961f-82ee72b054a4 +(cherry picked from commit 5b9471ffca25d39635680516ba2ff85295480fc3) +Signed-off-by: Romain Naour +--- + gcc/config/or1k/constraints.md | 4 ++++ + gcc/config/or1k/or1k.h | 3 +++ + gcc/config/or1k/or1k.md | 4 ++-- + 3 files changed, 9 insertions(+), 2 deletions(-) + +diff --git a/gcc/config/or1k/constraints.md b/gcc/config/or1k/constraints.md +index 93da8c058c6..a16b749008f 100644 +--- a/gcc/config/or1k/constraints.md ++++ b/gcc/config/or1k/constraints.md +@@ -24,6 +24,7 @@ + + ; We use: + ; c - sibcall registers ++; t - got address registers (excludes LR (r9) which is clobbered by set_got) + ; I - constant signed 16-bit + ; K - constant unsigned 16-bit + ; M - constant signed 16-bit shifted left 16-bits (l.movhi) +@@ -32,6 +33,9 @@ + (define_register_constraint "c" "SIBCALL_REGS" + "Registers which can hold a sibling call address") + ++(define_register_constraint "t" "GOT_REGS" ++ "Registers which can be used to store the Global Offset Table (GOT) address.") ++ + ;; Immediates + (define_constraint "I" + "A signed 16-bit immediate in the range -32768 to 32767." +diff --git a/gcc/config/or1k/or1k.h b/gcc/config/or1k/or1k.h +index 6dda230f217..feee702d89c 100644 +--- a/gcc/config/or1k/or1k.h ++++ b/gcc/config/or1k/or1k.h +@@ -189,6 +189,7 @@ enum reg_class + { + NO_REGS, + SIBCALL_REGS, ++ GOT_REGS, + GENERAL_REGS, + FLAG_REGS, + ALL_REGS, +@@ -200,6 +201,7 @@ enum reg_class + #define REG_CLASS_NAMES { \ + "NO_REGS", \ + "SIBCALL_REGS", \ ++ "GOT_REGS", \ + "GENERAL_REGS", \ + "FLAG_REGS", \ + "ALL_REGS" } +@@ -212,6 +214,7 @@ enum reg_class + #define REG_CLASS_CONTENTS \ + { { 0x00000000, 0x00000000 }, \ + { SIBCALL_REGS_MASK, 0 }, \ ++ { 0xfffffdff, 0x00000000 }, \ + { 0xffffffff, 0x00000003 }, \ + { 0x00000000, 0x00000004 }, \ + { 0xffffffff, 0x00000007 } \ +diff --git a/gcc/config/or1k/or1k.md b/gcc/config/or1k/or1k.md +index 2dad51cd46b..88f3f02630f 100644 +--- a/gcc/config/or1k/or1k.md ++++ b/gcc/config/or1k/or1k.md +@@ -595,7 +595,7 @@ + ;; set_got pattern below. This works because the set_got_tmp insn is the + ;; first insn in the stream and that it isn't moved during RA. + (define_insn "set_got_tmp" +- [(set (match_operand:SI 0 "register_operand" "=r") ++ [(set (match_operand:SI 0 "register_operand" "=t") + (unspec_volatile:SI [(const_int 0)] UNSPECV_SET_GOT))] + "" + { +@@ -604,7 +604,7 @@ + + ;; The insn to initialize the GOT. + (define_insn "set_got" +- [(set (match_operand:SI 0 "register_operand" "=r") ++ [(set (match_operand:SI 0 "register_operand" "=t") + (unspec:SI [(const_int 0)] UNSPEC_SET_GOT)) + (clobber (reg:SI LR_REGNUM))] + "" +-- +2.24.1 + diff --git a/package/gcc/Config.in.host b/package/gcc/Config.in.host index bdfa1b5916..243310f61e 100644 --- a/package/gcc/Config.in.host +++ b/package/gcc/Config.in.host @@ -88,7 +88,7 @@ config BR2_GCC_VERSION default "5.5.0" if BR2_GCC_VERSION_5_X default "7.5.0" if BR2_GCC_VERSION_7_X default "8.4.0" if BR2_GCC_VERSION_8_X - default "9.2.0" if BR2_GCC_VERSION_9_X + default "9.3.0" if BR2_GCC_VERSION_9_X default "arc-2019.09-release" if BR2_GCC_VERSION_ARC default "48152afb96c59733d5bc79e3399bb7b3d4b44266" if BR2_GCC_VERSION_CSKY diff --git a/package/gcc/gcc.hash b/package/gcc/gcc.hash index ba63db1563..d9df3408d4 100644 --- a/package/gcc/gcc.hash +++ b/package/gcc/gcc.hash @@ -4,8 +4,8 @@ sha512 670ff52c2ae12c7852c12987e91798c5aa8bd6daf21f0d6e0cd57a4aa59cc4f06a837fe7 sha512 fe716cc19f2e3255d3a8b1b8290777bf769c6d98e6e0b07b81a3d6ad43f8af74cb170dfa18b1555dbfcd3f55ae582b91a286ccef496b9b65c1579902f96a1f60 gcc-7.5.0.tar.xz # From ftp://gcc.gnu.org/pub/gcc/releases/gcc-8.4.0/sha512.sum sha512 6de904f552a02de33b11ef52312bb664396efd7e1ce3bbe37bfad5ef617f133095b3767b4804bc7fe78df335cb53bc83f1ac055baed40979ce4c2c3e46b70280 gcc-8.4.0.tar.xz -# From ftp://gcc.gnu.org/pub/gcc/releases/gcc-9.2.0/sha512.sum -sha512 a12dff52af876aee0fd89a8d09cdc455f35ec46845e154023202392adc164848faf8ee881b59b681b696e27c69fd143a214014db4214db62f9891a1c8365c040 gcc-9.2.0.tar.xz +# From ftp://gcc.gnu.org/pub/gcc/releases/gcc-9.3.0/sha512.sum +sha512 4b9e3639eef6e623747a22c37a904b4750c93b6da77cf3958d5047e9b5ebddb7eebe091cc16ca0a227c0ecbd2bf3b984b221130f269a97ee4cc18f9cf6c444de gcc-9.3.0.tar.xz # Locally calculated (fetched from Github) sha512 84648d13f174102733e06ccdf7b351150babe06af0f2b99b8dfb2b2d3c3f13e424547349939806fe19932ad347977cad79cd8b37be9cbb03e6a4d03cdf95a72e gcc-arc-2019.09-release.tar.gz