From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 8 Apr 2019 23:22:07 +0000 (-0700)
Subject: Update CHANGELOG
X-Git-Tag: yosys-0.9~171^2~12
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f6c354c55bcba26978c8dd04c3cc4f02231aebe4;p=yosys.git

Update CHANGELOG
---

diff --git a/CHANGELOG b/CHANGELOG
index 95bbb3f33..36b64e111 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -16,7 +16,7 @@ Yosys 0.8 .. Yosys 0.8-dev
     - Added "gate2lut.v" techmap rule
     - Added "rename -src"
     - Added "equiv_opt" pass
-    - Added "shregmap -tech xilinx", used by "synth_xilinx"
+    - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
 
 
 Yosys 0.7 .. Yosys 0.8