From: Quan Nguyen <quannguyen@berkeley.edu>
Date: Tue, 4 Feb 2014 04:10:06 +0000 (-0800)
Subject: Add vfmsv instruction test, change vsetprec to vsetucfg
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f6d8b4850e6c10804059fe94489cdf9455e208af;p=riscv-tests.git

Add vfmsv instruction test, change vsetprec to vsetucfg
---

diff --git a/isa/rv64uv/Makefrag b/isa/rv64uv/Makefrag
index b251942..affbdaf 100644
--- a/isa/rv64uv/Makefrag
+++ b/isa/rv64uv/Makefrag
@@ -6,6 +6,7 @@ rv64uv_sc_tests = \
 	wakeup fence \
 	vsetcfgi vsetcfg vsetvl \
 	vmvv vmsv \
+	vfmvv vfmsv \
 	utidx \
 	lb lbu lh lhu lw lwu ld \
 	sb sh sw sd \
diff --git a/isa/rv64uv/vfmsv.S b/isa/rv64uv/vfmsv.S
new file mode 100644
index 0000000..5a8dbeb
--- /dev/null
+++ b/isa/rv64uv/vfmsv.S
@@ -0,0 +1,55 @@
+#*****************************************************************************
+# vfmsv.S
+#-----------------------------------------------------------------------------
+#
+# Test vfmsv instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UV
+RVTEST_CODE_BEGIN
+
+  vsetcfg 3,1
+  li a2,680
+  vsetvl a2,a2
+
+  li a3,-1
+  vfmsv vf0,a3
+  lui a0,%hi(vtcode)
+  vf %lo(vtcode)(a0)
+  la a4,dest
+  vsd vx2,a4
+  fence
+
+  li a1,0
+loop:
+  ld a0,0(a4)
+  addi x28,a1,2
+  bne a0,a1,fail
+  addi a4,a4,8
+  addi a1,a1,1
+  bne a1,a2,loop
+  j pass
+
+vtcode:
+  utidx x1
+  addi x1,x1,1
+  fmv.x.d x2, f0
+  add x2,x1,x2
+  stop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+dest:
+  .skip 16384
+
+RVTEST_DATA_END
diff --git a/isa/rv64uv/vvadd_packed.S b/isa/rv64uv/vvadd_packed.S
index a4ba982..5a5760d 100644
--- a/isa/rv64uv/vvadd_packed.S
+++ b/isa/rv64uv/vvadd_packed.S
@@ -13,8 +13,8 @@ RVTEST_CODE_BEGIN
 
 	li x1, 12 # number of test elements
 	move x10, x1
-	vsetcfg 3, 1
-	vsetprec 16
+	vsetucfg x2, 0x2
+	vsetcfg x2, 3, 1
 loop:
 	vsetvl x4, x1
 	la x2, addr