From: Luke Kenneth Casson Leighton Date: Fri, 17 Apr 2020 15:26:20 +0000 (+0100) Subject: rename signals X-Git-Tag: div_pipeline~1432^2~2 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f6e243e5cc2011d0ae1f4b1b65e8bcfc1b20edde;p=soc.git rename signals --- diff --git a/src/soc/scoreboard/group_picker.py b/src/soc/scoreboard/group_picker.py index 1f68b128..2f33aa3d 100644 --- a/src/soc/scoreboard/group_picker.py +++ b/src/soc/scoreboard/group_picker.py @@ -63,14 +63,14 @@ class GroupPicker(Elaboratable): ri = [] for i in range(n_src): rdr.append(Signal(wid, name="rdrel%d_i" % i, reset_less=True)) - rd.append(Signal(wid, name="gordl%d_i" % i, reset_less=True)) + rd.append(Signal(wid, name="gord%d_o" % i, reset_less=True)) ri.append(Signal(wid, name="readable%d_i" % i, reset_less=True)) wrr = [] wr = [] wi = [] for i in range(n_dst): wrr.append(Signal(wid, name="reqrel%d_i" % i, reset_less=True)) - wr.append(Signal(wid, name="gowr%d_i" % i, reset_less=True)) + wr.append(Signal(wid, name="gowr%d_o" % i, reset_less=True)) wi.append(Signal(wid, name="writable%d_i" % i, reset_less=True)) # inputs diff --git a/src/soc/scoremulti/fu_wr_pending.py b/src/soc/scoremulti/fu_wr_pending.py index d1ce2d06..6707142e 100644 --- a/src/soc/scoremulti/fu_wr_pending.py +++ b/src/soc/scoremulti/fu_wr_pending.py @@ -9,16 +9,15 @@ class FU_RW_Pend(Elaboratable): self.n_src = n_src self.n_dest = n_dest self.reg_count = reg_count - self.dest_fwd_i = Signal(reg_count, reset_less=True) dst = [] - for i in range(n_src): + for i in range(n_dest): j = i + 1 # name numbering to match dest1/dest2 - dst.append(Signal(reg_count, name="dst%d" % j, reset_less=True)) + dst.append(Signal(reg_count, name="dfwd%d_i" % j, reset_less=True)) self.dest_fwd_i = Array(dst) src = [] for i in range(n_src): j = i + 1 # name numbering to match src1/src2 - src.append(Signal(reg_count, name="src%d" % j, reset_less=True)) + src.append(Signal(reg_count, name="sfwd%d_i" % j, reset_less=True)) self.src_fwd_i = Array(src) self.reg_wr_pend_o = Signal(reset_less=True) diff --git a/src/soc/scoremulti/reg_sel.py b/src/soc/scoremulti/reg_sel.py index 9d36f3be..46b27be7 100644 --- a/src/soc/scoremulti/reg_sel.py +++ b/src/soc/scoremulti/reg_sel.py @@ -9,7 +9,6 @@ class Reg_Rsv(Elaboratable): self.n_src = n_src self.n_dest = n_dest self.fu_count = fu_count - self.dest_rsel_i = Signal(fu_count, reset_less=True) self.dest_rsel_i = Array(Signal(fu_count, name="dst_rsel_i", reset_less=True) \ for i in range(n_dest))