From: lkcl <lkcl@web>
Date: Mon, 5 Sep 2022 16:11:30 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~673
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f6e4ef2d9532fa36db387e465936017bcf18e4c3;p=libreriscv.git

---

diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn
index ca1eb1539..be9a5069d 100644
--- a/openpower/sv/normal.mdwn
+++ b/openpower/sv/normal.mdwn
@@ -129,9 +129,16 @@ ISAs, but leverages the underlying scalar Base v3.0B operations.
 Thus it is more a convention that the programmer may utilise to give
 the appearance and effect of a Horizontal Vector Reduction. Due
 to the unusual decoupling it is also possible to perform
-prefix-sum in certain circumstances. Details are in the [[svp64/appendix]]
+prefix-sum (Fibonacci Series) in certain circumstances. Details are in the [[svp64/appendix]]
 
 Reduce Mode should not be confused with Parallel Reduction [[sv/remap]].
+As explained in the [[sv/appendix]] Reduce Mode switches off the check
+which would normally stop looping if the result register is scalar.
+Thus, the result scalar register, if also used as a source scalar, 
+may be used to perform sequential accumulation.  This *deliberately*
+sets up a chain
+of Register Hazard Dependencies, whereas Parallel Reduce [[sv/remap]]
+deliberately issues a Tree-Schedule of operations that may be parallelised.
 
 # Fail-on-first