From: Clifford Wolf Date: Sun, 24 Nov 2013 16:29:11 +0000 (+0100) Subject: Remove auto_wire framework (smarter than the verilog standard) X-Git-Tag: yosys-0.2.0~316 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f71e27dbf15d063ca45378ff2eb2d8102220f199;p=yosys.git Remove auto_wire framework (smarter than the verilog standard) --- diff --git a/backends/ilang/ilang_backend.cc b/backends/ilang/ilang_backend.cc index 513e57fa7..b51b3f88b 100644 --- a/backends/ilang/ilang_backend.cc +++ b/backends/ilang/ilang_backend.cc @@ -118,8 +118,6 @@ void ILANG_BACKEND::dump_wire(FILE *f, std::string indent, const RTLIL::Wire *wi fprintf(f, "\n"); } fprintf(f, "%s" "wire ", indent.c_str()); - if (wire->auto_width) - fprintf(f, "auto "); if (wire->width != 1) fprintf(f, "width %d ", wire->width); if (wire->start_offset != 0) diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 6423cae22..ffbcf314e 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -876,44 +876,6 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, std::map auto_sizes) -{ - log_header("Executing AST frontend in update_auto_wires mode using pre-parsed AST for module `%s'.\n", name.c_str()); - - current_ast = NULL; - flag_dump_ast1 = false; - flag_dump_ast2 = false; - flag_dump_vlog = false; - flag_nolatches = nolatches; - flag_nomem2reg = nomem2reg; - flag_mem2reg = mem2reg; - flag_lib = lib; - flag_noopt = noopt; - use_internal_line_num(); - - for (auto it = auto_sizes.begin(); it != auto_sizes.end(); it++) { - log("Adding extra wire declaration to AST: wire [%d:0] %s\n", it->second - 1, it->first.c_str()); - AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, AstNode::mkconst_int(it->second - 1, true), AstNode::mkconst_int(0, true))); - wire->str = it->first; - ast->children.insert(ast->children.begin(), wire); - } - - AstModule *newmod = process_module(ast); - - delete ast; - ast = newmod->ast; - newmod->ast = NULL; - - wires.swap(newmod->wires); - cells.swap(newmod->cells); - processes.swap(newmod->processes); - connections.swap(newmod->connections); - attributes.swap(newmod->attributes); - delete newmod; -} - RTLIL::Module *AstModule::clone() const { AstModule *new_mod = new AstModule; diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index f9f47f6a4..349832256 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -228,7 +228,6 @@ namespace AST bool nolatches, nomem2reg, mem2reg, lib, noopt; virtual ~AstModule(); virtual RTLIL::IdString derive(RTLIL::Design *design, std::map parameters, std::set signed_parameters); - virtual void update_auto_wires(std::map auto_sizes); virtual RTLIL::Module *clone() const; }; @@ -239,9 +238,8 @@ namespace AST extern void (*set_line_num)(int); extern int (*get_line_num)(); - // set set_line_num and get_line_num to internal dummy functions - // (done by simplify(), AstModule::derive and AstModule::update_auto_wires to control - // the filename and linenum properties of new nodes not generated by a frontend parser) + // set set_line_num and get_line_num to internal dummy functions (done by simplify() and AstModule::derive + // to control the filename and linenum properties of new nodes not generated by a frontend parser) void use_internal_line_num(); } diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 177c1ec59..66b670c7a 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -917,15 +917,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) RTLIL::Wire *wire = new RTLIL::Wire; wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); wire->name = str; - if (width_hint >= 0) { - wire->width = width_hint; - log("Warning: Identifier `%s' is implicitly declared with width %d at %s:%d.\n", - str.c_str(), width_hint, filename.c_str(), linenum); - } else { - log("Warning: Identifier `%s' is implicitly declared at %s:%d.\n", - str.c_str(), filename.c_str(), linenum); - } - wire->auto_width = true; + log("Warning: Identifier `%s' is implicitly declared at %s:%d.\n", str.c_str(), filename.c_str(), linenum); current_module->wires[str] = wire; } else if (id2ast->type == AST_PARAMETER || id2ast->type == AST_LOCALPARAM) { diff --git a/frontends/ilang/lexer.l b/frontends/ilang/lexer.l index 73bc894b1..287f9dbf6 100644 --- a/frontends/ilang/lexer.l +++ b/frontends/ilang/lexer.l @@ -41,7 +41,6 @@ "parameter" { return TOK_PARAMETER; } "wire" { return TOK_WIRE; } "memory" { return TOK_MEMORY; } -"auto" { return TOK_AUTO; } "width" { return TOK_WIDTH; } "offset" { return TOK_OFFSET; } "size" { return TOK_SIZE; } diff --git a/frontends/ilang/parser.y b/frontends/ilang/parser.y index dc39cf93f..71c63bc44 100644 --- a/frontends/ilang/parser.y +++ b/frontends/ilang/parser.y @@ -54,7 +54,7 @@ using namespace ILANG_FRONTEND; %token TOK_CELL TOK_CONNECT TOK_SWITCH TOK_CASE TOK_ASSIGN TOK_SYNC %token TOK_LOW TOK_HIGH TOK_POSEDGE TOK_NEGEDGE TOK_EDGE TOK_ALWAYS TOK_INIT %token TOK_UPDATE TOK_PROCESS TOK_END TOK_INVALID TOK_EOL TOK_OFFSET -%token TOK_PARAMETER TOK_ATTRIBUTE TOK_AUTO TOK_MEMORY TOK_SIZE +%token TOK_PARAMETER TOK_ATTRIBUTE TOK_MEMORY TOK_SIZE %type sigspec sigspec_list %type sync_type @@ -124,9 +124,6 @@ wire_stmt: }; wire_options: - wire_options TOK_AUTO { - current_wire->auto_width = true; - } | wire_options TOK_WIDTH TOK_INT { current_wire->width = $3; } | diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index afd7ca2f1..5bfb33a2d 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -265,11 +265,6 @@ RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, std::map) -{ - log_error("Module `%s' has automatic wires bu no HDL backend to handle it!\n", id2cstr(name)); -} - size_t RTLIL::Module::count_id(RTLIL::IdString id) { return wires.count(id) + memories.count(id) + cells.count(id) + processes.count(id); @@ -779,7 +774,6 @@ RTLIL::Wire::Wire() port_id = 0; port_input = false; port_output = false; - auto_width = false; } RTLIL::Memory::Memory() diff --git a/kernel/rtlil.h b/kernel/rtlil.h index a4c3008bc..4b790cbde 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -265,7 +265,6 @@ struct RTLIL::Module { RTLIL_ATTRIBUTE_MEMBERS virtual ~Module(); virtual RTLIL::IdString derive(RTLIL::Design *design, std::map parameters, std::set signed_parameters); - virtual void update_auto_wires(std::map auto_sizes); virtual size_t count_id(RTLIL::IdString id); virtual void check(); virtual void optimize(); @@ -283,7 +282,7 @@ struct RTLIL::Module { struct RTLIL::Wire { RTLIL::IdString name; int width, start_offset, port_id; - bool port_input, port_output, auto_width; + bool port_input, port_output; RTLIL_ATTRIBUTE_MEMBERS Wire(); }; diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 291df184f..18f058973 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -155,66 +155,6 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla did_something = true; } - if (did_something) - return did_something; - - std::map auto_wires; - - for (auto &wire_it : module->wires) { - if (wire_it.second->auto_width) - auto_wires[RTLIL::SigSpec(wire_it.second)] = -1; - } - - for (auto &cell_it : module->cells) - for (auto &conn : cell_it.second->connections) - for (auto &awit : auto_wires) { - if (awit.second >= 0 || conn.second != awit.first) - continue; - if (design->modules.count(cell_it.second->type) == 0) { - log("WARNING: Module `%s' used in auto-delaration of the wire `%s.%s' cannot be found.\n", - cell_it.second->type.c_str(), module->name.c_str(), log_signal(awit.first)); - continue; - } - RTLIL::Module *mod = design->modules[cell_it.second->type]; - RTLIL::Wire *wire = NULL; - if (mod->wires.count(conn.first) == 0) { - for (auto &wire_it : mod->wires) { - if (wire_it.second->port_id == 0) - continue; - char buffer[100]; - snprintf(buffer, 100, "$%d", wire_it.second->port_id); - if (buffer == conn.first) { - wire = wire_it.second; - break; - } - } - } else - wire = mod->wires[conn.first]; - if (!wire || wire->port_id == 0) - log_error("No port `%s' found in `%s' but used by instanciation in `%s'!\n", - conn.first.c_str(), mod->name.c_str(), module->name.c_str()); - if (wire->auto_width) - log_error("Signal `%s' found in `%s' and used by instanciation in `%s' for an auto wire is an auto-wire itself!\n", - log_signal(awit.first), mod->name.c_str(), module->name.c_str()); - awit.second = wire->width; - } - - std::map auto_sizes; - for (auto &awit : auto_wires) { - if (awit.second < 0) - log("Can't further resolve auto-wire `%s.%s' (width %d) using cell ports.\n", - module->name.c_str(), awit.first.chunks[0].wire->name.c_str(), - awit.first.chunks[0].wire->width); - else - auto_sizes[awit.first.chunks[0].wire->name] = awit.second; - } - - if (auto_sizes.size() > 0) { - module->update_auto_wires(auto_sizes); - log_header("Continuing HIERARCHY pass.\n"); - did_something = true; - } - return did_something; }