From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 20 Jun 2022 20:08:40 +0000 (+0100)
Subject: mention compliancy levels not Libre-SOC
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f725927829a6ba613b110ff0b5d4f16bddd0ff7a;p=libreriscv.git

mention compliancy levels not Libre-SOC
---

diff --git a/svp64-primer/summary.tex b/svp64-primer/summary.tex
index 0b613e0c3..3c56ea286 100644
--- a/svp64-primer/summary.tex
+++ b/svp64-primer/summary.tex
@@ -134,7 +134,7 @@ Floating Point registers, similar to \acs{MMX}.
 
 Simple-V's "Vector" Registers are specifically designed to fit on top of
 the Scalar (GPR, FPR) register files, which are extended from the default
-of 32, to 128 entries in the Libre-SOC implementation.  This is a primary
+of 32, to 128 entries in the high-end Compliancy Levels.  This is a primary
 reason why Simple-V can be added on top of an existing Scalar ISA, and
 \textit{in particular} why there is no need to add Vector Registers or
 Vector instructions.