From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 20 Jun 2020 11:55:26 +0000 (+0100)
Subject: add test_sram_wishbone.py
X-Git-Tag: div_pipeline~303
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f737a8a27c245cec9fe959a6d4b76fb786626505;p=soc.git

add test_sram_wishbone.py
https://bugs.libre-soc.org/show_bug.cgi?id=382
---

diff --git a/src/soc/bus/test/test_sram_wishbone.py b/src/soc/bus/test/test_sram_wishbone.py
new file mode 100644
index 00000000..0a25314a
--- /dev/null
+++ b/src/soc/bus/test/test_sram_wishbone.py
@@ -0,0 +1,82 @@
+"""demonstration of nmigen-soc SRAM behind a wishbone bus
+Bugs:
+* https://bugs.libre-soc.org/show_bug.cgi?id=382
+"""
+from nmigen_soc.wishbone.sram import SRAM
+from nmigen import Memory, Signal, Module
+
+memory = Memory(width=32, depth=16)
+sram = SRAM(memory=memory,granularity=8)
+
+# valid wishbone signals include
+# sram.bus.adr
+# sram.bus.dat_w
+# sram.bus.dat_r
+# sram.bus.sel
+# sram.bus.cyc
+# sram.bus.stb
+# sram.bus.we
+# sram.bus.ack
+
+# setup simulation
+from nmigen.back.pysim import Simulator, Delay, Settle
+m = Module()
+m.submodules.sram = sram
+sim = Simulator(m)
+sim.add_clock(1e-6)
+
+def print_sig(sig, format=None):
+    if format == None:
+        print(f"{sig.__repr__()} = {(yield sig)}")
+    if format == "h":
+        print(f"{sig.__repr__()} = {hex((yield sig))}")
+
+def process():
+    # enable necessary signals for write
+    for en in range(4):
+        yield sram.bus.sel[en].eq(1)
+    yield sram.bus.we.eq(1)
+    yield sram.bus.cyc.eq(1)
+    yield sram.bus.stb.eq(1)
+
+    # put data and address on bus
+    yield sram.bus.adr.eq(0x4)
+    yield sram.bus.dat_w.eq(0xdeadbeef)
+    yield
+
+    # set necessary signal to read bus
+    # at address 0
+    yield sram.bus.we.eq(0)
+    yield sram.bus.adr.eq(0)
+    yield sram.bus.cyc.eq(1)
+    yield sram.bus.stb.eq(1)
+    yield
+
+    # see sync_behaviors.py
+    # for why we need Settle()
+    yield Settle()
+    yield from print_sig(sram.bus.adr)
+    yield from print_sig(sram.bus.dat_r, "h")
+
+    # set necessary signal to read bus
+    # at address 4
+    yield sram.bus.we.eq(0)
+    yield sram.bus.adr.eq(0x4)
+    yield sram.bus.cyc.eq(1)
+    yield sram.bus.stb.eq(1)
+    yield
+
+    yield Settle()
+    yield from print_sig(sram.bus.adr)
+    yield from print_sig(sram.bus.dat_r, "h")
+
+    # disable signals
+    yield sram.bus.cyc.eq(0)
+    yield sram.bus.stb.eq(0)
+    yield
+
+sim_writer = sim.write_vcd(f"{__file__[:-3]}.vcd")
+
+with sim_writer:
+    sim.add_sync_process(process)
+    sim.run()