From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 28 May 2019 15:45:10 +0000 (-0700)
Subject: read_aiger to only clean own design
X-Git-Tag: working-ls180~1208^2~256
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f745727de5af085412b2e5f8161aa1018cc5e276;p=yosys.git

read_aiger to only clean own design
---

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index e8a355671..8d7588f88 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -722,8 +722,14 @@ void AigerReader::post_process()
     module->fixup_ports();
     design->add(module);
 
+    design->selection_stack.emplace_back(false);
+    RTLIL::Selection& sel = design->selection_stack.back();
+    sel.select(module);
+
     Pass::call(design, "clean");
 
+    design->selection_stack.pop_back();
+
     for (auto cell : module->cells().to_vector()) {
         if (cell->type != "$lut") continue;
         auto y_port = cell->getPort("\\Y").as_bit();