From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 14 Jul 2020 19:31:05 +0000 (+0100)
Subject: attempting to access self.msr directly
X-Git-Tag: div_pipeline~40
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f747ad69cedf95e6154a4de141530e4ebcd48279;p=soc.git

attempting to access self.msr directly
---

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 2833e6f3..aea6d035 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -577,8 +577,9 @@ class ISACaller:
                       MicrOp.OP_MTSPR.value] and spr_msb:
             instr_is_privileged = True
 
+        print ("is priv", instr_is_privileged, self.msr[63-MSR.PR])
         # check MSR priv bit and whether op is privileged: if so, throw trap
-        if instr_is_privileged and self.namespace['MSR'][63-MSR.PR] == 1:
+        if instr_is_privileged and self.msr[63-MSR.PR] == 1:
             self.TRAP(0x700, PI.PRIV)
             return