From: Luke Kenneth Casson Leighton Date: Mon, 29 Oct 2018 02:54:16 +0000 (+0000) Subject: add example illustrative tables X-Git-Tag: convert-csv-opcode-to-binary~4877 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f74e5c10870de693b6fcebb49078bedc721d5e08;p=libreriscv.git add example illustrative tables --- diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn index 4505afa60..14c3e7c21 100644 --- a/simple_v_extension/specification.mdwn +++ b/simple_v_extension/specification.mdwn @@ -1606,7 +1606,9 @@ x8 through to half of x11. Note that whilst the memory addressing table is shown left-to-right byte order, the registers are shown in right-to-left (MSB) order. This does **not** -imply that bit or byte-reversal is carried out: it's just easier to visualise. +imply that bit or byte-reversal is carried out: it's just easier to visualise +memory as being contiguous bytes, and emphasises that registers are not +really actually "memory" as such. ## Why SV bitwidth specification is restricted to 4 entries