From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 20 Dec 2021 15:01:38 +0000 (+0000)
Subject: prefer not to invert when doing if/else.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f758de3ce617e779733e69647f3772544bb7d712;p=soc.git

prefer not to invert when doing if/else.
---

diff --git a/src/soc/experiment/mmu.py b/src/soc/experiment/mmu.py
index f139e85a..1c23e81a 100644
--- a/src/soc/experiment/mmu.py
+++ b/src/soc/experiment/mmu.py
@@ -168,12 +168,12 @@ class MMU(Elaboratable):
         rts = Signal(6)
         mbits = Signal(6)
 
-        with m.If(~l_in.addr[63]):
-            comb += pgtbl.eq(r.pgtbl0)
-            comb += pt_valid.eq(r.pt0_valid)
-        with m.Else():
+        with m.If(l_in.addr[63]):
             comb += pgtbl.eq(r.pgtbl3)
             comb += pt_valid.eq(r.pt3_valid)
+        with m.Else():
+            comb += pgtbl.eq(r.pgtbl0)
+            comb += pt_valid.eq(r.pt0_valid)
 
         # rts == radix tree size, number of address bits
         # being translated.  takes bits 5:7 and 61:63