From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 10 Nov 2021 18:43:25 +0000 (+0000)
Subject: add MSR to gtkw file for simulation output
X-Git-Tag: sv_maxu_works-initial~760
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f75aa3c5a202a68ed129a49af352df2a87aa49ce;p=openpower-isa.git

add MSR to gtkw file for simulation output
---

diff --git a/src/openpower/test/runner.py b/src/openpower/test/runner.py
index ff4ab26b..dd59e9fa 100644
--- a/src/openpower/test/runner.py
+++ b/src/openpower/test/runner.py
@@ -311,7 +311,7 @@ class TestRunnerBase(FHDLTestCase):
                 'is_last', 'dec2.no_out_vec']),
             {'comment': 'fetch and decode'},
             (None, 'dec', [
-                'cia[63:0]', 'nia[63:0]', 'pc[63:0]',
+                'cia[63:0]', 'nia[63:0]', 'pc[63:0]', 'msr[63:0]',
                 'cur_pc[63:0]', 'core_core_cia[63:0]']),
             'raw_insn_i[31:0]',
             'raw_opcode_in[31:0]', 'insn_type', 'dec2.dec2_exc_happened',