From: lkcl <lkcl@web>
Date: Mon, 22 Feb 2021 04:19:38 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~135
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f764b8083afd70f191937a25d731cda7eef4905a;p=libreriscv.git

---

diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index 39e023c97..c2018946d 100644
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -151,10 +151,6 @@ TODO.  INTs, FPs, CRs, these all increase to 128.  Welcome To Vector ISAs.
 
 At the same time the `Rc=1` CR offsets normslly CR0 and CR1 for fixed and FP scalar may also be adjusted.
 
-## Exception Handling
-
-When excceptions occur, and SRR0 and SRR1 are saved and restored, SVSTATE in SVSRR0 must now likewise be saved and restored.
-
 ## Single Predication
 
 TODO