From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 18 Jun 2022 12:38:52 +0000 (+0100)
Subject: add margin, clarify Power ISA
X-Git-Tag: opf_rfc_ls005_v1~1717
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f79ea04763ad122a0ff7996bc564cf3b71017b2f;p=libreriscv.git

add margin, clarify Power ISA
---

diff --git a/svp64-primer/summary.tex b/svp64-primer/summary.tex
index d9c8c59aa..57999a89e 100644
--- a/svp64-primer/summary.tex
+++ b/svp64-primer/summary.tex
@@ -3,7 +3,7 @@ Simple-V is a Scalable Vector Specification for a hardware for-loop that
 ONLY uses scalar instructions. Advantages:
 
 \begin{itemize}
-\item The v3.1 Specification is not altered in any way.
+\item The Power ISA v3.1 Specification is not altered in any way.
 \item Specifically designed to be easily implemented
   on top of an existing Micro-architecture (especially
   Superscalar Out-of-Order Multi-issue) without
diff --git a/svp64-primer/svp64-primer.tex b/svp64-primer/svp64-primer.tex
index 7ae6f89e8..f7d27c0be 100644
--- a/svp64-primer/svp64-primer.tex
+++ b/svp64-primer/svp64-primer.tex
@@ -2,6 +2,7 @@
 \usepackage[utf8]{inputenc}
 \usepackage[printonlyused,withpage]{acronym}
 \usepackage{graphicx}
+\usepackage[margin=1.1in]{geometry}
 \graphicspath{ {./img/} }
 
 \title{(DRAFT) SVP64 Primer - \textit{Not so short yet}}