From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 2 Jul 2022 16:59:34 +0000 (+0100)
Subject: fix setvl CTR mode
X-Git-Tag: sv_maxu_works-initial~303
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f7a0c32d38db53d628e8d72d2424b44efcfc26c6;p=openpower-isa.git

fix setvl CTR mode
---

diff --git a/openpower/isa/simplev.mdwn b/openpower/isa/simplev.mdwn
index a933fcd9..3b185c9a 100644
--- a/openpower/isa/simplev.mdwn
+++ b/openpower/isa/simplev.mdwn
@@ -32,18 +32,16 @@ Pseudo-code:
            GPR(_RT) <- [0]*57 || step
     else
         VLimm <- SVi + 1
-        if vs = 0 then
-            VL <- SVSTATE[7:13]
-        else if _RA != 0 then
-            VL <- (RA)[57:63]
-        else if _RT != 0 then
-            VL <- CTR
-        else
-            VL <- VLimm[0:6]
-        if ms = 1 then
-            MVL <- VLimm[0:6]
-        else
-            MVL <- SVSTATE[0:6]
+        # set or get MVL
+        if ms = 1 then MVL <- VLimm[0:6]
+        else           MVL <- SVSTATE[0:6]
+        # set or get VL
+        if vs = 0                then VL <- SVSTATE[7:13]
+        else if _RA != 0         then VL <- (RA)[57:63]
+        else if _RT = 0          then VL <- VLimm[0:6]
+        else if CTR >u 0b1111111 then VL = 0b1111111
+        else                          VL <- CTR[57:63]
+        # limit VL to within MVL
         if VL >u MVL then
             VL <- MVL
         SVSTATE[0:6] <- MVL