From: Claudiu Zissulescu Date: Mon, 9 Apr 2018 15:05:19 +0000 (+0200) Subject: [ARC] Add/update combiner patterns. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f7ace5d5c21d3db30d9fb87cd8a632e7509e6fef;p=gcc.git [ARC] Add/update combiner patterns. gcc/ 2018-01-26 Claudiu Zissulescu * config/arc/arc.md (add_shift): New pattern. (add_shift2): Likewise. (sub_shift): Likewise. (sub_shift_cmp0_noout): Likewise. (compare_si_ashiftsi): Likewise. (xbfu_cmp0_noout): New combine pattern. (xbfu_cmp0"): Likewise. (movsi_set_cc_insn): Place the predicable variant first. (commutative_binary_cmp0_noout): Remove clobber. (commutative_binary_cmp0): New pattern. (noncommutative_binary_cmp0): Likewise. (noncommutative_binary_cmp0_noout): Likewise. (noncommutative_binary_comparison_result_used): Removed. (rsub_cmp0): New pattern. (rsub_cmp0_noout): Likewise. (extzvsi): Changed, keep only meaningful variants. (SQH, SEZ): New iterators. (SQH_postfix): New mode attribute. (SEZ_prefix): New code attribute. (xt_cmp0_noout): New instruction pattern. (xt_cmp0): Likewise. * config/arc/predicates.md (cc_set_register): Use CC_REG instead of numerical value. (noncommutative_operator): Check the availability of barrel shifter option. From-SVN: r259237 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6d0a2692bef..2328fd78102 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,31 @@ +2018-04-09 Claudiu Zissulescu + + * config/arc/arc.md (add_shift): New pattern. + (add_shift2): Likewise. + (sub_shift): Likewise. + (sub_shift_cmp0_noout): Likewise. + (compare_si_ashiftsi): Likewise. + (xbfu_cmp0_noout): New combine pattern. + (xbfu_cmp0"): Likewise. + (movsi_set_cc_insn): Place the predicable variant first. + (commutative_binary_cmp0_noout): Remove clobber. + (commutative_binary_cmp0): New pattern. + (noncommutative_binary_cmp0): Likewise. + (noncommutative_binary_cmp0_noout): Likewise. + (noncommutative_binary_comparison_result_used): Removed. + (rsub_cmp0): New pattern. + (rsub_cmp0_noout): Likewise. + (extzvsi): Changed, keep only meaningful variants. + (SQH, SEZ): New iterators. + (SQH_postfix): New mode attribute. + (SEZ_prefix): New code attribute. + (xt_cmp0_noout): New instruction pattern. + (xt_cmp0): Likewise. + * config/arc/predicates.md (cc_set_register): Use CC_REG instead + of numerical value. + (noncommutative_operator): Check the availability of barrel + shifter option. + 2018-04-09 Richard Biener PR tree-optimization/85284 diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index 2ffd3004374..127ed8ebee9 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -794,20 +794,90 @@ "st%U0 %1,%0\;st%U0.di %1,%0" [(set_attr "type" "store")]) +;; Combiner patterns for compare with zero +(define_mode_iterator SQH [QI HI]) +(define_mode_attr SQH_postfix [(QI "b") (HI "%_")]) + +(define_code_iterator SEZ [sign_extend zero_extend]) +(define_code_attr SEZ_prefix [(sign_extend "sex") (zero_extend "ext")]) + +(define_insn "*xt_cmp0_noout" + [(set (match_operand 0 "cc_set_register" "") + (compare:CC_ZN (SEZ:SI (match_operand:SQH 1 "register_operand" "r")) + (const_int 0)))] + "" + ".f\\t0,%1" + [(set_attr "type" "compare") + (set_attr "cond" "set_zn")]) + +(define_insn "*xt_cmp0" + [(set (match_operand 0 "cc_set_register" "") + (compare:CC_ZN (SEZ:SI (match_operand:SQH 1 "register_operand" "r")) + (const_int 0))) + (set (match_operand:SI 2 "register_operand" "=r") + (SEZ:SI (match_dup 1)))] + "" + ".f\\t%2,%1" + [(set_attr "type" "compare") + (set_attr "cond" "set_zn")]) + +(define_insn "*xbfu_cmp0_noout" + [(set (match_operand 0 "cc_set_register" "") + (compare:CC_Z + (zero_extract:SI + (match_operand:SI 1 "register_operand" " r,r") + (match_operand:SI 2 "const_int_operand" "C3p,n") + (match_operand:SI 3 "const_int_operand" " n,n")) + (const_int 0)))] + "TARGET_HS && TARGET_BARREL_SHIFTER" + { + int assemble_op2 = (((INTVAL (operands[2]) - 1) & 0x1f) << 5) | (INTVAL (operands[3]) & 0x1f); + operands[2] = GEN_INT (assemble_op2); + return "xbfu%?.f\\t0,%1,%2"; + } + [(set_attr "type" "shift") + (set_attr "iscompact" "false") + (set_attr "length" "4,8") + (set_attr "predicable" "no") + (set_attr "cond" "set_zn")]) + +(define_insn "*xbfu_cmp0" + [(set (match_operand 4 "cc_set_register" "") + (compare:CC_Z + (zero_extract:SI + (match_operand:SI 1 "register_operand" "0 ,r,0") + (match_operand:SI 2 "const_int_operand" "C3p,n,n") + (match_operand:SI 3 "const_int_operand" "n ,n,n")) + (const_int 0))) + (set (match_operand:SI 0 "register_operand" "=r,r,r") + (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] + "TARGET_HS && TARGET_BARREL_SHIFTER" + { + int assemble_op2 = (((INTVAL (operands[2]) - 1) & 0x1f) << 5) | (INTVAL (operands[3]) & 0x1f); + operands[2] = GEN_INT (assemble_op2); + return "xbfu%?.f\\t%0,%1,%2"; + } + [(set_attr "type" "shift") + (set_attr "iscompact" "false") + (set_attr "length" "4,8,8") + (set_attr "predicable" "yes,no,yes") + (set_attr "cond" "set_zn")]) + +; splitting to 'tst' allows short insns and combination into brcc. (define_insn_and_split "*movsi_set_cc_insn" - [(set (match_operand:CC_ZN 2 "cc_set_register" "") - (match_operator:CC_ZN 3 "zn_compare_operator" - [(match_operand:SI 1 "nonmemory_operand" "cI,cL,Cal") (const_int 0)])) - (set (match_operand:SI 0 "register_operand" "=w,w,w") + [(set (match_operand 2 "cc_set_register" "") + (match_operator 3 "zn_compare_operator" + [(match_operand:SI 1 "nonmemory_operand" "rL,rI,Cal") + (const_int 0)])) + (set (match_operand:SI 0 "register_operand" "=r,r,r") (match_dup 1))] "" - "mov%?.f %0,%1" - ; splitting to 'tst' allows short insns and combination into brcc. + "mov%?.f\\t%0,%1" "reload_completed && operands_match_p (operands[0], operands[1])" [(set (match_dup 2) (match_dup 3))] "" [(set_attr "type" "compare") - (set_attr "predicable" "no,yes,yes") + (set_attr "predicable" "yes,no,yes") (set_attr "cond" "set_zn") (set_attr "length" "4,4,8")]) @@ -957,19 +1027,35 @@ (set_attr "cond" "set_zn") (set_attr "length" "*,4,4,4,8")]) -(define_insn "*commutative_binary_comparison" - [(set (match_operand:CC_ZN 0 "cc_set_register" "") - (match_operator:CC_ZN 5 "zn_compare_operator" +;; The next two patterns are for plos, ior, xor, and, and mult. +(define_insn "*commutative_binary_cmp0_noout" + [(set (match_operand 0 "cc_set_register" "") + (match_operator 4 "zn_compare_operator" + [(match_operator:SI 3 "commutative_operator" + [(match_operand:SI 1 "register_operand" "%r,r") + (match_operand:SI 2 "nonmemory_operand" "rL,Cal")]) + (const_int 0)]))] + "" + "%O3.f\\t0,%1,%2" + [(set_attr "type" "compare") + (set_attr "cond" "set_zn") + (set_attr "length" "4,8")]) + +(define_insn "*commutative_binary_cmp0" + [(set (match_operand 3 "cc_set_register" "") + (match_operator 5 "zn_compare_operator" [(match_operator:SI 4 "commutative_operator" - [(match_operand:SI 1 "register_operand" "%c,c") - (match_operand:SI 2 "nonmemory_operand" "cL,Cal")]) + [(match_operand:SI 1 "register_operand" "%0, 0,r,r") + (match_operand:SI 2 "nonmemory_operand" "rL,rI,r,Cal")]) (const_int 0)])) - (clobber (match_scratch:SI 3 "=X,X"))] + (set (match_operand:SI 0 "register_operand" "=r,r,r,r") + (match_dup 4))] "" - "%O4.f 0,%1,%2" + "%O4.f\\t%0,%1,%2" [(set_attr "type" "compare") (set_attr "cond" "set_zn") - (set_attr "length" "4,8")]) + (set_attr "predicable" "yes,yes,no,no") + (set_attr "length" "4,4,4,8")]) ; for flag setting 'add' instructions like if (a+b) { ...} ; the combiner needs this pattern @@ -1043,32 +1129,60 @@ (set_attr "cond" "set_zn,set_zn,set_zn") (set_attr "length" "4,4,8")]) -; this pattern is needed by combiner for cases like if (c=a<