From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 27 Jan 2024 11:57:10 +0000 (+0000)
Subject: bug 1034: yet again move crternlogi due to size of operands
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f7b10b60;p=openpower-isa.git

bug 1034: yet again move crternlogi due to size of operands
---

diff --git a/openpower/isa/bitmanip.mdwn b/openpower/isa/bitmanip.mdwn
index 1b58fc8e..c0bf722f 100644
--- a/openpower/isa/bitmanip.mdwn
+++ b/openpower/isa/bitmanip.mdwn
@@ -97,14 +97,14 @@ Special Registers Altered:
 
 # Condition Register Field Ternary Bitwise Logic Immediate
 
-CRB-Form
+TLI-Form
 
 * crternlogi BT,BA,BB,TLI
 
 Pseudo-code:
 
     idx <- CR[BT+32] || CR[BA+32] || CR[BB+32]
-    CR[4*BF+32] <- TLI[7-idx]
+    CR[4*BT+32] <- TLI[7-idx]
 
 Special Registers Altered:
 
diff --git a/openpower/isatables/minor_5.csv b/openpower/isatables/minor_5.csv
index 1f8ba13f..629d7ff8 100644
--- a/openpower/isatables/minor_5.csv
+++ b/openpower/isatables/minor_5.csv
@@ -2,7 +2,7 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 # ternlog (integer, CR and CR field)
 --------00-,SHIFT_ROT,OP_TERNLOG,RA,RB,RT,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,ternlogi,TLI,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 -----00001-,CR,OP_CRFTERNLOG,NONE,NONE,NONE,NONE,BFA_BFB_BF,BF,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,crfternlogi,CRB,,1,unofficial until submitted and approved/renumbered by the opf isa wg
------00101-,CR,OP_CRTERNLOG,NONE,NONE,NONE,NONE,BA_BB,BT,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,crternlogi,TLI,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+--------110,CR,OP_CRTERNLOG,NONE,NONE,NONE,NONE,BA_BB,BT,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,crternlogi,TLI,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 
 # integer butterfly
 -----100100,ALU,OP_MADDSUBRS,RA,CONST_SH,RB,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddsubrs,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg
diff --git a/src/openpower/test/bitmanip/bitmanip_cases.py b/src/openpower/test/bitmanip/bitmanip_cases.py
index 5df82a7f..931ba7fb 100644
--- a/src/openpower/test/bitmanip/bitmanip_cases.py
+++ b/src/openpower/test/bitmanip/bitmanip_cases.py
@@ -48,6 +48,18 @@ def ternlogi(rc, rt, ra, rb, imm):
     return expected
 
 
+def crternlogi(bt, ba, bb, imm):
+    expected = 0
+    checks = (bb, ba, bt) # LUT positions 1<<0=bb 1<<1=ba 1<<2=bt
+    lut_index = 0
+    for j, check in enumerate(checks):
+        if check & 1:
+            lut_index |= 1<<j
+    if imm & (1<<lut_index):
+        expected |= 1
+    return expected
+
+
 def crfternlogi(bf, bfa, bfb, imm, mask):
     expected = bf&~mask # start at BF, mask overwrites masked bits only
     checks = (bfb, bfa, bf) # LUT positions 1<<0=bfb 1<<1=bfa 1<<2=bf
@@ -76,6 +88,40 @@ class BitManipTestCase(TestAccumulatorBase):
 
         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 
+    def do_case_crternlogi(self, bt, ba, bb, imm):
+        lst = ["crternlogi 0,4,8,%d" % imm]
+        # set up CR to match bt bit 0, ba bit 4, bb bit 8, in MSB0 order
+        # bearing in mind that CRFields.cr is a 64-bit SelectableInt. sigh.
+        cr = CRFields()
+        cr.cr[32+0] = bt
+        cr.cr[32+4] = ba
+        cr.cr[32+8] = bb
+        initial_cr = cr.cr.asint()
+        print("initial cr", bin(initial_cr), bt, ba, bb,
+              "tli", bin(imm), lst)
+
+        lst = list(SVP64Asm(lst, bigendian))
+        e = ExpectedState(pc=4)
+        e.crregs[0] = crternlogi(bt, ba, bb, imm) << 3
+        e.crregs[1] = ba << 3
+        e.crregs[2] = bb << 3
+        self.add_case(Program(lst, bigendian), initial_regs=None, expected=e,
+                                       initial_cr=initial_cr)
+
+    def case_crternlogi_0(self):
+        self.do_case_crternlogi(0b1,
+                                0b1,
+                                0b1,
+                                0x80)
+
+    def case_crternlogi_random(self):
+        for i in range(100):
+            imm = hash_256(f"crternlogi imm {i}") & 0xFF
+            bt = hash_256(f"crternlogi bt {i}") & 1
+            ba = hash_256(f"crternlogi ba {i}") & 1
+            bb = hash_256(f"crternlogi bb {i}") & 1
+            self.do_case_crternlogi(bt, ba, bb, imm)
+
     def do_case_crfternlogi(self, bf, bfa, bfb, imm, mask):
         lst = [f"crfternlogi 3,4,5,%d,%d" % (imm, mask)]
         # set up CR