From: Cesar Strauss Date: Mon, 25 May 2020 00:40:52 +0000 (-0300) Subject: Show oper_r and oper_i in the signal list, in simulation X-Git-Tag: div_pipeline~854 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f7b1cc0b3292f4478b806dee26ca62b00c3e7e75;p=soc.git Show oper_r and oper_i in the signal list, in simulation --- diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py index 6b066031..0267d4f9 100644 --- a/src/soc/experiment/compalu_multi.py +++ b/src/soc/experiment/compalu_multi.py @@ -76,7 +76,7 @@ class CompUnitRecord(RegSpec, RecordObject): self._dest = dst # operation / data input - self.oper_i = subkls() # operand + self.oper_i = subkls(name="oper_i") # operand # create read/write and other scoreboard signalling self.rd = go_record(n_src, name="rd") # read in, req out @@ -205,7 +205,7 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable): m.d.sync += req_l.r.eq(reset_w) # create a latch/register for the operand - oper_r = self.opsubsetkls() + oper_r = self.opsubsetkls(name="oper_r") latchregister(m, self.oper_i, oper_r, self.issue_i, "oper_l") # and for each output from the ALU diff --git a/src/soc/experiment/compldst_multi.py b/src/soc/experiment/compldst_multi.py index 048e5b4c..1f2845ac 100644 --- a/src/soc/experiment/compldst_multi.py +++ b/src/soc/experiment/compldst_multi.py @@ -339,7 +339,7 @@ class LDSTCompUnit(Elaboratable): comb += rst_l.r.eq(issue_i) # create a latch/register for the operand - oper_r = CompLDSTOpSubset() # Dest register + oper_r = CompLDSTOpSubset(name="oper_r") # Dest register latchregister(m, self.oper_i, oper_r, self.issue_i, name="oper_l") # and for LD