From: Jose E. Marchesi <jose.marchesi@oracle.com>
Date: Wed, 29 Mar 2017 19:20:23 +0000 (+0200)
Subject: opcodes: sparc: support missing SPARC ASIs from UA2005, UA2007, OSA2011, & OSA2015
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f7c514a3784384215692c43d66f013d7640db277;p=binutils-gdb.git

opcodes: sparc: support missing SPARC ASIs from UA2005, UA2007, OSA2011, & OSA2015
---

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index fe6f27be7c2..c6c2ceec14e 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
+
+	Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
+	OSA2015.
+	* opcodes/sparc-opc.c (asi_table): New ASIs.
+
 2017-03-29  Alan Modra  <amodra@gmail.com>
 
 	* ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
diff --git a/opcodes/sparc-opc.c b/opcodes/sparc-opc.c
index 2473de5dc9f..c302d835e29 100644
--- a/opcodes/sparc-opc.c
+++ b/opcodes/sparc-opc.c
@@ -2420,6 +2420,34 @@ static sparc_asi asi_table[] =
   { 0xE3, "#ASI_TWINX_S", v9c },
   { 0xEA, "#ASI_TWINX_PL", v9c },
   { 0xEB, "#ASI_TWINX_SL", v9c },
+  /* These are ASIs from UA2005, UA2007, OSA2011, & OSA 2015 */
+  { 0x12, "#ASI_MAIUP", v9m },
+  { 0x13, "#ASI_MAIUS", v9m },
+  { 0x14, "#ASI_REAL", v9c },
+  { 0x15, "#ASI_REAL_IO", v9c },
+  { 0x1c, "#ASI_REAL_L", v9c },
+  { 0x1d, "#ASI_REAL_IO_L", v9c },
+  { 0x30, "#ASI_AIPP", v9d },
+  { 0x31, "#ASI_AIPS", v9d },
+  { 0x36, "#ASI_AIPN", v9d },
+  { 0x38, "#ASI_AIPP_L", v9d },
+  { 0x39, "#ASI_AIPS_L", v9d },
+  { 0x3e, "#ASI_AIPN_L", v9d },
+  { 0x42, "#ASI_INST_MASK_REG", v9d },
+  { 0x42, "#ASI_LSU_DIAG_REG", v9d },
+  { 0x43, "#ASI_ERROR_INJECT_REG", v9d },
+  { 0x48, "#ASI_IRF_ECC_REG", v9d },
+  { 0x49, "#ASI_FRF_ECC_REG", v9d },
+  { 0x4e, "#ASI_SPARC_PWR_MGMT", v9d },
+  { 0x4f, "#ASI_HYP_SCRATCHPAD", v9c },
+  { 0x59, "#ASI_SCRATCHPAD_ACCESS", v9d },
+  { 0x5a, "#ASI_TICK_ACCESS", v9d },
+  { 0x5b, "#ASI_TSA_ACCESS", v9d },
+  { 0xb0, "#ASI_PIC", v9e },
+  { 0xf2, "#ASI_STBI_PM", v9e },
+  { 0xf3, "#ASI_STBI_SM", v9e },
+  { 0xfa, "#ASI_STBI_PLM", v9e },
+  { 0xfb, "#ASI_STBI_SLM", v9e },
   { 0, 0, 0 }
 };