From: Shriya Sharma <shriya@redsemiconductor.com>
Date: Fri, 27 Oct 2023 10:40:24 +0000 (+0100)
Subject: added english language description for lwbrsx instruction
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f7c614e316dad2551e37ef012ceb06a8fd4e95f5;p=openpower-isa.git

added english language description for lwbrsx instruction
---

diff --git a/openpower/isa/fixedloadshift.mdwn b/openpower/isa/fixedloadshift.mdwn
index 3f26d430..fd9e31f2 100644
--- a/openpower/isa/fixedloadshift.mdwn
+++ b/openpower/isa/fixedloadshift.mdwn
@@ -370,6 +370,19 @@ Pseudo-code:
     RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
                     || load_data[8:15]  || load_data[0:7])
 
+Description:
+
+    Let the effective address (EA) be the sum of the contents of
+    register RB shifted by (SH+1), and (RA|0).
+
+    Bits 0:7 of the word in storage addressed
+    by EA are loaded into RT[56:63]. Bits 8:15 of the word in
+    storage addressed by EA are loaded into RT[48:55]. Bits
+    16:23 of the word in storage addressed by EA are
+    loaded into RT[40:47]. Bits 24:31 of the word in storage
+    addressed by EA are loaded into RT 32:39.
+    RT[0:31] are set to 0.
+
 Special Registers Altered:
 
     None