From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 13 Jul 2020 10:27:08 +0000 (+0100)
Subject: add extswsli unit test
X-Git-Tag: div_pipeline~69
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f7c9d276783bb8caf11d17710836f8f03be64f17;p=soc.git

add extswsli unit test
---

diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py
index 263de991..c1b20b1a 100644
--- a/src/soc/fu/shift_rot/test/test_pipe_caller.py
+++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py
@@ -141,6 +141,14 @@ class ShiftRotTestCase(FHDLTestCase):
         initial_regs[1] = random.randint(0, (1<<64)-1)
         self.run_tst_program(Program(lst, bigendian), initial_regs)
 
+    def test_extswsli(self):
+        for i in range(40):
+            sh = random.randint(0, 63)
+            lst = [f"extswsli 3, 1, {sh}"]
+            initial_regs = [0] * 32
+            initial_regs[1] = random.randint(0, (1<<64)-1)
+            self.run_tst_program(Program(lst, bigendian), initial_regs)
+
     def test_rlc(self):
         insns = ["rldic", "rldicl", "rldicr"]
         for i in range(20):