From: Gabe Black Date: Wed, 29 Mar 2017 23:14:05 +0000 (-0700) Subject: stats: Update some stats after simulated program exit behavior was changed. X-Git-Tag: v19.0.0.0~2859 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f7ddc4672a17ee4fab3011bb1b570cc7c17dff28;p=gem5.git stats: Update some stats after simulated program exit behavior was changed. The following CL delayed program exit and changed the stats for many if not most of the SE mode regressions. commit 2c1286865fc2542a0586ca4ff40b00765d17b348 Author: Brandon Potter Date: Wed Mar 1 14:52:23 2017 -0600 syscall-emul: Rewrite system call exit code Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16 Reviewed-on: https://gem5-review.googlesource.com/2656 Maintainer: Jason Lowe-Power Reviewed-by: Jason Lowe-Power --- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini index afbdccd37..e061f70cd 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -65,7 +65,7 @@ SSITSize=1024 activity=0 backComSize=5 branchPred=system.cpu.branchPred -cachePorts=200 +cacheStorePorts=200 checker=Null clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 @@ -141,6 +141,7 @@ socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -176,10 +177,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=6 @@ -193,6 +194,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=8 write_buffers=16 @@ -205,15 +207,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu.dstage2_mmu] type=ArmStage2MMU @@ -316,38 +319,52 @@ pipelined=true [system.cpu.fuPool.FUList2] type=FUDesc -children=opList +children=opList0 opList1 count=1 eventq_index=0 -opList=system.cpu.fuPool.FUList2.opList +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 -[system.cpu.fuPool.FUList2.opList] +[system.cpu.fuPool.FUList2.opList0] type=OpDesc eventq_index=0 opClass=MemRead opLat=2 pipelined=true +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=2 +pipelined=true + [system.cpu.fuPool.FUList3] type=FUDesc -children=opList +children=opList0 opList1 count=1 eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 -[system.cpu.fuPool.FUList3.opList] +[system.cpu.fuPool.FUList3.opList0] type=OpDesc eventq_index=0 opClass=MemWrite opLat=2 pipelined=true +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=2 +pipelined=true + [system.cpu.fuPool.FUList4] type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27 count=2 eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 +opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27 [system.cpu.fuPool.FUList4.opList00] type=OpDesc @@ -479,7 +496,7 @@ pipelined=true type=OpDesc eventq_index=0 opClass=SimdFloatMultAcc -opLat=1 +opLat=5 pipelined=true [system.cpu.fuPool.FUList4.opList19] @@ -531,6 +548,20 @@ opClass=FloatMult opLat=4 pipelined=true +[system.cpu.fuPool.FUList4.opList26] +type=OpDesc +eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList4.opList27] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + [system.cpu.icache] type=Cache children=tags @@ -538,10 +569,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=1 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=1 is_read_only=true max_miss_count=0 mshrs=2 @@ -555,6 +586,7 @@ response_latency=1 sequential_access=false size=32768 system=system +tag_latency=1 tags=system.cpu.icache.tags tgts_per_mshr=8 write_buffers=8 @@ -567,15 +599,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=1 default_p_state=UNDEFINED eventq_index=0 -hit_latency=1 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=1 [system.cpu.interrupts] type=ArmInterrupts @@ -594,8 +627,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -606,8 +637,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -670,10 +699,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl +data_latency=12 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=12 is_read_only=false max_miss_count=0 mshrs=16 @@ -687,6 +716,7 @@ response_latency=12 sequential_access=false size=1048576 system=system +tag_latency=12 tags=system.cpu.l2cache.tags tgts_per_mshr=8 write_buffers=8 @@ -729,15 +759,16 @@ type=RandomRepl assoc=16 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=12 default_p_state=UNDEFINED eventq_index=0 -hit_latency=12 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=1048576 +tag_latency=12 [system.cpu.toL2Bus] type=CoherentXBar @@ -773,7 +804,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=mcf mcf.in cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing drivers= @@ -782,14 +813,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/mcf +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/mcf gid=100 -input=/arm/projectscratch/randd/systems/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=55300000000 system=system uid=100 diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr index 4184e8f67..5b248e07d 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr @@ -1,4 +1,5 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4] diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout index 07887a4ce..b22552f23 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/sim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:52:57 -gem5 executing on e108600-lin, pid 17480 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/10.mcf/arm/linux/o3-timing +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 18:10:17 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 56685 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... MCF SPEC version 1.6.I by Andreas Loebel @@ -26,4 +25,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 58675371500 because target called exit() +Exiting @ tick 58521086000 because exiting with last active thread context diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 57821b2e6..7a51f9c37 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,1262 +1,1262 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058521 # Number of seconds simulated -sim_ticks 58521086000 # Number of ticks simulated -final_tick 58521086000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 243648 # Simulator instruction rate (inst/s) -host_op_rate 244862 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 157397000 # Simulator tick rate (ticks/s) -host_mem_usage 492140 # Number of bytes of host memory used -host_seconds 371.81 # Real time elapsed on the host -sim_insts 90589799 # Number of instructions simulated -sim_ops 91041030 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 44736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 220224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 921920 # Number of bytes read from this memory -system.physmem.bytes_read::total 1186880 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 44736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 44736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4736 # Number of bytes written to this memory -system.physmem.bytes_written::total 4736 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 699 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3441 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 14405 # Number of read requests responded to by this memory -system.physmem.num_reads::total 18545 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 74 # Number of write requests responded to by this memory -system.physmem.num_writes::total 74 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 764442 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3763156 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 15753638 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 20281237 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 764442 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 764442 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 80928 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 80928 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 80928 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 764442 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3763156 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 15753638 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 20362165 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 18546 # Number of read requests accepted -system.physmem.writeReqs 74 # Number of write requests accepted -system.physmem.readBursts 18546 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 74 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1183360 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 3584 # Total number of bytes read from write queue -system.physmem.bytesWritten 3328 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1186944 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4736 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 56 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 3297 # Per bank write bursts -system.physmem.perBankRdBursts::1 920 # Per bank write bursts -system.physmem.perBankRdBursts::2 949 # Per bank write bursts -system.physmem.perBankRdBursts::3 1031 # Per bank write bursts -system.physmem.perBankRdBursts::4 1067 # Per bank write bursts -system.physmem.perBankRdBursts::5 1119 # Per bank write bursts -system.physmem.perBankRdBursts::6 1093 # Per bank write bursts -system.physmem.perBankRdBursts::7 1097 # Per bank write bursts -system.physmem.perBankRdBursts::8 1024 # Per bank write bursts -system.physmem.perBankRdBursts::9 961 # Per bank write bursts -system.physmem.perBankRdBursts::10 934 # Per bank write bursts -system.physmem.perBankRdBursts::11 899 # Per bank write bursts -system.physmem.perBankRdBursts::12 902 # Per bank write bursts -system.physmem.perBankRdBursts::13 895 # Per bank write bursts -system.physmem.perBankRdBursts::14 1399 # Per bank write bursts -system.physmem.perBankRdBursts::15 903 # Per bank write bursts -system.physmem.perBankWrBursts::0 1 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 2 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 1 # Per bank write bursts -system.physmem.perBankWrBursts::5 14 # Per bank write bursts -system.physmem.perBankWrBursts::6 9 # Per bank write bursts -system.physmem.perBankWrBursts::7 3 # Per bank write bursts -system.physmem.perBankWrBursts::8 1 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 2 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 1 # Per bank write bursts -system.physmem.perBankWrBursts::13 12 # Per bank write bursts -system.physmem.perBankWrBursts::14 5 # Per bank write bursts -system.physmem.perBankWrBursts::15 1 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58521077500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 18546 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 74 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 12593 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 3390 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 500 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 409 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 319 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 301 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 297 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 299 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 279 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 3004 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 394.652463 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 214.589229 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 405.543781 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 893 29.73% 29.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 965 32.12% 61.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 89 2.96% 64.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 63 2.10% 66.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 67 2.23% 69.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 66 2.20% 71.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 53 1.76% 73.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 47 1.56% 74.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 761 25.33% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 3004 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 3 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 6161.333333 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 2123.401593 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 8586.829993 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 1 33.33% 33.33% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2559 1 33.33% 66.67% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15872-16383 1 33.33% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 3 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 3 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.333333 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.306995 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.154701 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 1 33.33% 33.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 2 66.67% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 3 # Writes before turning the bus around for reads -system.physmem.totQLat 837911216 # Total ticks spent queuing -system.physmem.totMemAccLat 1184598716 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 92450000 # Total ticks spent in databus transfers -system.physmem.avgQLat 45316.99 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 64066.99 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 20.22 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.06 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 20.28 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.08 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.16 # Data bus utilization in percentage -system.physmem.busUtilRead 0.16 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 13.38 # Average write queue length when enqueuing -system.physmem.readRowHits 15512 # Number of row buffer hits during reads -system.physmem.writeRowHits 18 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.89 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 25.71 # Row buffer hit rate for writes -system.physmem.avgGap 3142915.01 # Average gap between requests -system.physmem.pageHitRate 83.67 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 16243500 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 8614650 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 75484080 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 156600 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1895549760.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 464945010 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 99199680 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 4173482430 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 3272736480 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 9883191315 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 19894073865 # Total energy per rank (pJ) -system.physmem_0.averagePower 339.947098 # Core power per rank (mW) -system.physmem_0.totalIdleTime 57233116090 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 194944250 # Time in different power states -system.physmem_0.memoryStateTime::REF 806364000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 39558059500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 8522710566 # Time in different power states -system.physmem_0.memoryStateTime::ACT 286661660 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 9152346024 # Time in different power states -system.physmem_1.actEnergy 5255040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2785530 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 56527380 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 114840 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 247699920.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 125328180 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 13397280 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 772336890 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 242624160 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 13451278005 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 14917407225 # Total energy per rank (pJ) -system.physmem_1.averagePower 254.906533 # Core power per rank (mW) -system.physmem_1.totalIdleTime 58211272096 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 21634250 # Time in different power states -system.physmem_1.memoryStateTime::REF 105218000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 55885668250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 631842954 # Time in different power states -system.physmem_1.memoryStateTime::ACT 182961654 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 1693760892 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 28121660 # Number of BP lookups -system.cpu.branchPred.condPredicted 23134709 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 844714 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11731332 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11630363 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.139322 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 80725 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 95 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 28301 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 25845 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 2456 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 243 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 442 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 58521086000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 117042173 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 755365 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 134380549 # Number of instructions fetch has processed -system.cpu.fetch.Branches 28121660 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11736933 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 115370240 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1692793 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 848 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 1033 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 32086744 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 572 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 116973882 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.154260 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.318237 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 59688776 51.03% 51.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 13868271 11.86% 62.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9100495 7.78% 70.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 34316340 29.34% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 116973882 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.240269 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.148138 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8865418 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 65026599 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 32710680 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9589004 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 782181 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 9831266 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 64876 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 113761457 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2108425 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 782181 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15316274 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 50229704 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 114341 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 35119945 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15411437 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110456918 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1289549 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 11149602 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1576334 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2138216 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 510190 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 129202611 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 481340709 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 118978784 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 633 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 21889692 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4408 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 4400 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 21529051 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26813393 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5308956 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 540635 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 272789 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 109383305 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 8282 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 101253910 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 993650 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18350557 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 40868291 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 64 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 116973882 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.865611 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.989909 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 55502940 47.45% 47.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 31207963 26.68% 74.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 21948493 18.76% 92.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7109305 6.08% 98.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1204859 1.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 322 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 116973882 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9836731 48.84% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 51 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 19 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9605308 47.69% 96.54% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 697155 3.46% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 3 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 24 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 71822499 70.93% 70.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10678 0.01% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 77 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 184 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.94% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24343876 24.04% 94.99% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5076562 5.01% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 8 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 22 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 101253910 # Type of FU issued -system.cpu.iq.rate 0.865106 # Inst issue rate -system.cpu.iq.fu_busy_cnt 20139291 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.198899 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 340613998 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 127742533 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 99568159 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 645 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 896 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 147 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 121392865 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 336 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 289487 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4337482 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2085 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1323 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 564112 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7586 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 131115 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 782181 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8303656 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 706645 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 109404410 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26813393 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5308956 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4394 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 183005 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 362995 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1323 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 354101 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 451870 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 805971 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 100068536 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23799476 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1185374 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12823 # number of nop insts executed -system.cpu.iew.exec_refs 28747002 # number of memory reference insts executed -system.cpu.iew.exec_branches 20644390 # Number of branches executed -system.cpu.iew.exec_stores 4947526 # Number of stores executed -system.cpu.iew.exec_rate 0.854978 # Inst execution rate -system.cpu.iew.wb_sent 99653444 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 99568306 # cumulative count of insts written-back -system.cpu.iew.wb_producers 59603520 # num instructions producing a value -system.cpu.iew.wb_consumers 95472454 # num instructions consuming a value -system.cpu.iew.wb_rate 0.850705 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.624301 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 17204380 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 780499 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 114317449 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.796498 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.736161 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 77973404 68.21% 68.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18552037 16.23% 84.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 7135846 6.24% 90.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3439776 3.01% 93.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1654311 1.45% 95.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 545783 0.48% 95.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 692568 0.61% 96.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 180777 0.16% 96.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4142947 3.62% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 114317449 # Number of insts commited each cycle -system.cpu.commit.committedInsts 90602408 # Number of instructions committed -system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27220755 # Number of memory references committed -system.cpu.commit.loads 22475911 # Number of loads committed -system.cpu.commit.membars 3888 # Number of memory barriers committed -system.cpu.commit.branches 18732305 # Number of branches committed -system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu.commit.int_insts 72326352 # Number of committed integer instructions. -system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 63822387 70.09% 70.09% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 6 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 22475905 24.68% 94.79% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 4744822 5.21% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 6 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 22 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction -system.cpu.commit.bw_lim_events 4142947 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 218426787 # The number of ROB reads -system.cpu.rob.rob_writes 219173124 # The number of ROB writes -system.cpu.timesIdled 593 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 68291 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 90589799 # Number of Instructions Simulated -system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.292002 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.292002 # CPI: Total CPI of All Threads -system.cpu.ipc 0.773993 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.773993 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 108095256 # number of integer regfile reads -system.cpu.int_regfile_writes 58597145 # number of integer regfile writes -system.cpu.fp_regfile_reads 58 # number of floating regfile reads -system.cpu.fp_regfile_writes 127 # number of floating regfile writes -system.cpu.cc_regfile_reads 368871207 # number of cc regfile reads -system.cpu.cc_regfile_writes 58517884 # number of cc regfile writes -system.cpu.misc_regfile_reads 28439348 # number of misc regfile reads -system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 5470632 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.768178 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18243100 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 5471144 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 3.334421 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 38187500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.768178 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999547 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999547 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 327 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 185 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 61896540 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 61896540 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 13880582 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13880582 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4354214 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4354214 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3873 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3873 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 18234796 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18234796 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18235318 # number of overall hits -system.cpu.dcache.overall_hits::total 18235318 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9588832 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9588832 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 380767 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 380767 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 14 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 14 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9969599 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9969599 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9969606 # number of overall misses -system.cpu.dcache.overall_misses::total 9969606 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 89393317500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 89393317500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4103772083 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4103772083 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 302000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 302000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 93497089583 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 93497089583 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 93497089583 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 93497089583 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23469414 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23469414 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 529 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28204395 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28204395 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28204924 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28204924 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408567 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.408567 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080416 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.080416 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003602 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003602 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.353477 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.353477 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.353470 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.353470 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9322.649255 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9322.649255 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10777.646390 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10777.646390 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21571.428571 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21571.428571 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9378.219684 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9378.219684 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9378.213099 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9378.213099 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 331670 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 131340 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 121646 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12838 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.726518 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 10.230566 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 5470632 # number of writebacks -system.cpu.dcache.writebacks::total 5470632 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4340269 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4340269 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158185 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 158185 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 14 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4498454 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4498454 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4498454 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4498454 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248563 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5248563 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222582 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 222582 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 5471145 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 5471145 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 5471149 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 5471149 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43818706500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 43818706500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2301862483 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2301862483 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 235500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 235500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46120568983 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 46120568983 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46120804483 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 46120804483 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223634 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223634 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047008 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047008 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193982 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.193982 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193979 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.193979 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8348.705446 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8348.705446 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10341.638061 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10341.638061 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 58875 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 58875 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8429.783708 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 8429.783708 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8429.820589 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 8429.820589 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 449 # number of replacements -system.cpu.icache.tags.tagsinuse 426.857560 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 32085580 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 907 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 35375.501654 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 426.857560 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.833706 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.833706 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 458 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 22 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 333 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.894531 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 64174375 # Number of tag accesses -system.cpu.icache.tags.data_accesses 64174375 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 32085580 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 32085580 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 32085580 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 32085580 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 32085580 # number of overall hits -system.cpu.icache.overall_hits::total 32085580 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1154 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1154 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1154 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1154 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1154 # number of overall misses -system.cpu.icache.overall_misses::total 1154 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 81624480 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 81624480 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 81624480 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 81624480 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 81624480 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 81624480 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 32086734 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 32086734 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 32086734 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 32086734 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 32086734 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 32086734 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000036 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000036 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000036 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000036 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000036 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70731.785095 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 70731.785095 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 70731.785095 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 70731.785095 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 70731.785095 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 70731.785095 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 21770 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 1853 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 229 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 95.065502 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 264.714286 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 449 # number of writebacks -system.cpu.icache.writebacks::total 449 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 246 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 246 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 246 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 246 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 246 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 246 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 908 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 908 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 908 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 908 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 908 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 908 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61609984 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 61609984 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61609984 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 61609984 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61609984 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 61609984 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67852.405286 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67852.405286 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67852.405286 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 67852.405286 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67852.405286 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 67852.405286 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 4987667 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 5295978 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 268023 # number of redundant prefetches already in prefetch queue -system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped -system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 14076270 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 99 # number of replacements -system.cpu.l2cache.tags.tagsinuse 11218.637670 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 5292117 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 14656 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 361.088769 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 11151.920658 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 66.717012 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.680659 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004072 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.684731 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 67 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 14490 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 56 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 454 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3440 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9642 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 120 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 834 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.004089 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884399 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 180525307 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 180525307 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 5460197 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 5460197 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 7956 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 7956 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 225753 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 225753 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 207 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 207 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5241769 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 5241769 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 207 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 5467522 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 5467729 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 207 # number of overall hits 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-system.cpu.l2cache.demand_misses::total 4323 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 701 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3622 # number of overall misses -system.cpu.l2cache.overall_misses::total 4323 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 105500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 105500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 66196000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 66196000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 59307500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 59307500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 617300000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 617300000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 59307500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 683496000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 742803500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 59307500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 683496000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 742803500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 5460197 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 5460197 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 7956 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 7956 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 5 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 5 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 226252 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 226252 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 908 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 908 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 5244892 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 5244892 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 908 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 5471144 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 5472052 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 908 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 5471144 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 5472052 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002206 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.002206 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.772026 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.772026 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000595 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000595 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.772026 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.000662 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.000790 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.772026 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.000662 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.000790 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21100 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21100 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 132657.314629 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 132657.314629 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84604.136947 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84604.136947 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 197662.504003 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 197662.504003 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84604.136947 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 188706.791828 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 171825.931066 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84604.136947 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 188706.791828 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 171825.931066 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.unused_prefetches 1 # number of HardPF blocks evicted w/o reference -system.cpu.l2cache.writebacks::writebacks 74 # number of writebacks -system.cpu.l2cache.writebacks::total 74 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 158 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 158 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 22 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 22 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 180 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 181 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 180 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 181 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 316332 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 316332 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 341 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 341 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 700 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 700 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 3101 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 3101 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 700 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3442 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 4142 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 700 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3442 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 316332 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 320474 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1095451507 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1095451507 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 75500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 75500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 46761500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 46761500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 55046500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 55046500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 590692000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 590692000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 55046500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 637453500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 692500000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 55046500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 637453500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1095451507 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1787951507 # number of overall MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001507 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001507 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.770925 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.770925 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000591 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000591 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.770925 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000629 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.000757 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.770925 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000629 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.058566 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3462.980372 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3462.980372 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15100 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15100 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 137130.498534 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 137130.498534 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 78637.857143 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 78637.857143 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 190484.359884 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 190484.359884 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 78637.857143 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 185198.576409 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167189.763399 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 78637.857143 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 185198.576409 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3462.980372 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 5579.084441 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 10943138 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471099 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2928 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 301927 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 301926 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 5245799 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 5460271 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 10884 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 25 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 318221 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFResp 6 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 226252 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 226252 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 908 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244892 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2264 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412936 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16415200 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700274048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 700360832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 318326 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 5120 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 5790377 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.052651 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.223337 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5485509 94.73% 94.73% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 304867 5.27% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5790377 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10942650026 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 18.7 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 9032 # Layer occupancy (ticks) -system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1362995 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 8206721993 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 14.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 18651 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 3037 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 18205 # Transaction distribution -system.membus.trans_dist::WritebackDirty 74 # Transaction distribution -system.membus.trans_dist::CleanEvict 25 # Transaction distribution -system.membus.trans_dist::UpgradeReq 6 # Transaction distribution -system.membus.trans_dist::ReadExReq 340 # Transaction distribution -system.membus.trans_dist::ReadExResp 340 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 18206 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 37196 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 37196 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1191616 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1191616 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 18552 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 18552 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 18552 # Request fanout histogram -system.membus.reqLayer0.occupancy 29380556 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 97369032 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +sim_seconds 0.058521 +sim_ticks 58521086000 +final_tick 58521086000 +sim_freq 1000000000000 +host_inst_rate 103970 +host_op_rate 104488 +host_tick_rate 67164623 +host_mem_usage 503044 +host_seconds 871.31 +sim_insts 90589799 +sim_ops 91041030 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 58521086000 +system.physmem.bytes_read::cpu.inst 44736 +system.physmem.bytes_read::cpu.data 220224 +system.physmem.bytes_read::cpu.l2cache.prefetcher 921920 +system.physmem.bytes_read::total 1186880 +system.physmem.bytes_inst_read::cpu.inst 44736 +system.physmem.bytes_inst_read::total 44736 +system.physmem.bytes_written::writebacks 4736 +system.physmem.bytes_written::total 4736 +system.physmem.num_reads::cpu.inst 699 +system.physmem.num_reads::cpu.data 3441 +system.physmem.num_reads::cpu.l2cache.prefetcher 14405 +system.physmem.num_reads::total 18545 +system.physmem.num_writes::writebacks 74 +system.physmem.num_writes::total 74 +system.physmem.bw_read::cpu.inst 764442 +system.physmem.bw_read::cpu.data 3763156 +system.physmem.bw_read::cpu.l2cache.prefetcher 15753638 +system.physmem.bw_read::total 20281237 +system.physmem.bw_inst_read::cpu.inst 764442 +system.physmem.bw_inst_read::total 764442 +system.physmem.bw_write::writebacks 80928 +system.physmem.bw_write::total 80928 +system.physmem.bw_total::writebacks 80928 +system.physmem.bw_total::cpu.inst 764442 +system.physmem.bw_total::cpu.data 3763156 +system.physmem.bw_total::cpu.l2cache.prefetcher 15753638 +system.physmem.bw_total::total 20362165 +system.physmem.readReqs 18546 +system.physmem.writeReqs 74 +system.physmem.readBursts 18546 +system.physmem.writeBursts 74 +system.physmem.bytesReadDRAM 1183360 +system.physmem.bytesReadWrQ 3584 +system.physmem.bytesWritten 3328 +system.physmem.bytesReadSys 1186944 +system.physmem.bytesWrittenSys 4736 +system.physmem.servicedByWrQ 56 +system.physmem.mergedWrBursts 4 +system.physmem.neitherReadNorWriteReqs 0 +system.physmem.perBankRdBursts::0 3297 +system.physmem.perBankRdBursts::1 920 +system.physmem.perBankRdBursts::2 949 +system.physmem.perBankRdBursts::3 1031 +system.physmem.perBankRdBursts::4 1067 +system.physmem.perBankRdBursts::5 1119 +system.physmem.perBankRdBursts::6 1093 +system.physmem.perBankRdBursts::7 1097 +system.physmem.perBankRdBursts::8 1024 +system.physmem.perBankRdBursts::9 961 +system.physmem.perBankRdBursts::10 934 +system.physmem.perBankRdBursts::11 899 +system.physmem.perBankRdBursts::12 902 +system.physmem.perBankRdBursts::13 895 +system.physmem.perBankRdBursts::14 1399 +system.physmem.perBankRdBursts::15 903 +system.physmem.perBankWrBursts::0 1 +system.physmem.perBankWrBursts::1 0 +system.physmem.perBankWrBursts::2 2 +system.physmem.perBankWrBursts::3 0 +system.physmem.perBankWrBursts::4 1 +system.physmem.perBankWrBursts::5 14 +system.physmem.perBankWrBursts::6 9 +system.physmem.perBankWrBursts::7 3 +system.physmem.perBankWrBursts::8 1 +system.physmem.perBankWrBursts::9 0 +system.physmem.perBankWrBursts::10 2 +system.physmem.perBankWrBursts::11 0 +system.physmem.perBankWrBursts::12 1 +system.physmem.perBankWrBursts::13 12 +system.physmem.perBankWrBursts::14 5 +system.physmem.perBankWrBursts::15 1 +system.physmem.numRdRetry 0 +system.physmem.numWrRetry 0 +system.physmem.totGap 58521077500 +system.physmem.readPktSize::0 0 +system.physmem.readPktSize::1 0 +system.physmem.readPktSize::2 0 +system.physmem.readPktSize::3 0 +system.physmem.readPktSize::4 0 +system.physmem.readPktSize::5 0 +system.physmem.readPktSize::6 18546 +system.physmem.writePktSize::0 0 +system.physmem.writePktSize::1 0 +system.physmem.writePktSize::2 0 +system.physmem.writePktSize::3 0 +system.physmem.writePktSize::4 0 +system.physmem.writePktSize::5 0 +system.physmem.writePktSize::6 74 +system.physmem.rdQLenPdf::0 12593 +system.physmem.rdQLenPdf::1 3390 +system.physmem.rdQLenPdf::2 500 +system.physmem.rdQLenPdf::3 409 +system.physmem.rdQLenPdf::4 319 +system.physmem.rdQLenPdf::5 301 +system.physmem.rdQLenPdf::6 297 +system.physmem.rdQLenPdf::7 299 +system.physmem.rdQLenPdf::8 279 +system.physmem.rdQLenPdf::9 103 +system.physmem.rdQLenPdf::10 0 +system.physmem.rdQLenPdf::11 0 +system.physmem.rdQLenPdf::12 0 +system.physmem.rdQLenPdf::13 0 +system.physmem.rdQLenPdf::14 0 +system.physmem.rdQLenPdf::15 0 +system.physmem.rdQLenPdf::16 0 +system.physmem.rdQLenPdf::17 0 +system.physmem.rdQLenPdf::18 0 +system.physmem.rdQLenPdf::19 0 +system.physmem.rdQLenPdf::20 0 +system.physmem.rdQLenPdf::21 0 +system.physmem.rdQLenPdf::22 0 +system.physmem.rdQLenPdf::23 0 +system.physmem.rdQLenPdf::24 0 +system.physmem.rdQLenPdf::25 0 +system.physmem.rdQLenPdf::26 0 +system.physmem.rdQLenPdf::27 0 +system.physmem.rdQLenPdf::28 0 +system.physmem.rdQLenPdf::29 0 +system.physmem.rdQLenPdf::30 0 +system.physmem.rdQLenPdf::31 0 +system.physmem.wrQLenPdf::0 1 +system.physmem.wrQLenPdf::1 1 +system.physmem.wrQLenPdf::2 1 +system.physmem.wrQLenPdf::3 1 +system.physmem.wrQLenPdf::4 1 +system.physmem.wrQLenPdf::5 1 +system.physmem.wrQLenPdf::6 1 +system.physmem.wrQLenPdf::7 1 +system.physmem.wrQLenPdf::8 1 +system.physmem.wrQLenPdf::9 1 +system.physmem.wrQLenPdf::10 1 +system.physmem.wrQLenPdf::11 1 +system.physmem.wrQLenPdf::12 1 +system.physmem.wrQLenPdf::13 1 +system.physmem.wrQLenPdf::14 1 +system.physmem.wrQLenPdf::15 3 +system.physmem.wrQLenPdf::16 3 +system.physmem.wrQLenPdf::17 4 +system.physmem.wrQLenPdf::18 3 +system.physmem.wrQLenPdf::19 3 +system.physmem.wrQLenPdf::20 3 +system.physmem.wrQLenPdf::21 3 +system.physmem.wrQLenPdf::22 3 +system.physmem.wrQLenPdf::23 3 +system.physmem.wrQLenPdf::24 3 +system.physmem.wrQLenPdf::25 3 +system.physmem.wrQLenPdf::26 3 +system.physmem.wrQLenPdf::27 3 +system.physmem.wrQLenPdf::28 3 +system.physmem.wrQLenPdf::29 3 +system.physmem.wrQLenPdf::30 3 +system.physmem.wrQLenPdf::31 3 +system.physmem.wrQLenPdf::32 3 +system.physmem.wrQLenPdf::33 0 +system.physmem.wrQLenPdf::34 0 +system.physmem.wrQLenPdf::35 0 +system.physmem.wrQLenPdf::36 0 +system.physmem.wrQLenPdf::37 0 +system.physmem.wrQLenPdf::38 0 +system.physmem.wrQLenPdf::39 0 +system.physmem.wrQLenPdf::40 0 +system.physmem.wrQLenPdf::41 0 +system.physmem.wrQLenPdf::42 0 +system.physmem.wrQLenPdf::43 0 +system.physmem.wrQLenPdf::44 0 +system.physmem.wrQLenPdf::45 0 +system.physmem.wrQLenPdf::46 0 +system.physmem.wrQLenPdf::47 0 +system.physmem.wrQLenPdf::48 0 +system.physmem.wrQLenPdf::49 0 +system.physmem.wrQLenPdf::50 0 +system.physmem.wrQLenPdf::51 0 +system.physmem.wrQLenPdf::52 0 +system.physmem.wrQLenPdf::53 0 +system.physmem.wrQLenPdf::54 0 +system.physmem.wrQLenPdf::55 0 +system.physmem.wrQLenPdf::56 0 +system.physmem.wrQLenPdf::57 0 +system.physmem.wrQLenPdf::58 0 +system.physmem.wrQLenPdf::59 0 +system.physmem.wrQLenPdf::60 0 +system.physmem.wrQLenPdf::61 0 +system.physmem.wrQLenPdf::62 0 +system.physmem.wrQLenPdf::63 0 +system.physmem.bytesPerActivate::samples 3004 +system.physmem.bytesPerActivate::mean 394.652463 +system.physmem.bytesPerActivate::gmean 214.589229 +system.physmem.bytesPerActivate::stdev 405.543781 +system.physmem.bytesPerActivate::0-127 893 29.73% 29.73% +system.physmem.bytesPerActivate::128-255 965 32.12% 61.85% +system.physmem.bytesPerActivate::256-383 89 2.96% 64.81% +system.physmem.bytesPerActivate::384-511 63 2.10% 66.91% +system.physmem.bytesPerActivate::512-639 67 2.23% 69.14% +system.physmem.bytesPerActivate::640-767 66 2.20% 71.34% +system.physmem.bytesPerActivate::768-895 53 1.76% 73.10% +system.physmem.bytesPerActivate::896-1023 47 1.56% 74.67% +system.physmem.bytesPerActivate::1024-1151 761 25.33% 100.00% +system.physmem.bytesPerActivate::total 3004 +system.physmem.rdPerTurnAround::samples 3 +system.physmem.rdPerTurnAround::mean 6161.333333 +system.physmem.rdPerTurnAround::gmean 2123.401593 +system.physmem.rdPerTurnAround::stdev 8586.829993 +system.physmem.rdPerTurnAround::0-511 1 33.33% 33.33% +system.physmem.rdPerTurnAround::2048-2559 1 33.33% 66.67% +system.physmem.rdPerTurnAround::15872-16383 1 33.33% 100.00% +system.physmem.rdPerTurnAround::total 3 +system.physmem.wrPerTurnAround::samples 3 +system.physmem.wrPerTurnAround::mean 17.333333 +system.physmem.wrPerTurnAround::gmean 17.306995 +system.physmem.wrPerTurnAround::stdev 1.154701 +system.physmem.wrPerTurnAround::16 1 33.33% 33.33% +system.physmem.wrPerTurnAround::18 2 66.67% 100.00% +system.physmem.wrPerTurnAround::total 3 +system.physmem.totQLat 837911216 +system.physmem.totMemAccLat 1184598716 +system.physmem.totBusLat 92450000 +system.physmem.avgQLat 45316.99 +system.physmem.avgBusLat 5000.00 +system.physmem.avgMemAccLat 64066.99 +system.physmem.avgRdBW 20.22 +system.physmem.avgWrBW 0.06 +system.physmem.avgRdBWSys 20.28 +system.physmem.avgWrBWSys 0.08 +system.physmem.peakBW 12800.00 +system.physmem.busUtil 0.16 +system.physmem.busUtilRead 0.16 +system.physmem.busUtilWrite 0.00 +system.physmem.avgRdQLen 1.04 +system.physmem.avgWrQLen 13.38 +system.physmem.readRowHits 15512 +system.physmem.writeRowHits 18 +system.physmem.readRowHitRate 83.89 +system.physmem.writeRowHitRate 25.71 +system.physmem.avgGap 3142915.01 +system.physmem.pageHitRate 83.67 +system.physmem_0.actEnergy 16243500 +system.physmem_0.preEnergy 8614650 +system.physmem_0.readEnergy 75484080 +system.physmem_0.writeEnergy 156600 +system.physmem_0.refreshEnergy 1895549760.000000 +system.physmem_0.actBackEnergy 464945010 +system.physmem_0.preBackEnergy 99199680 +system.physmem_0.actPowerDownEnergy 4173482430 +system.physmem_0.prePowerDownEnergy 3272736480 +system.physmem_0.selfRefreshEnergy 9883191315 +system.physmem_0.totalEnergy 19894073865 +system.physmem_0.averagePower 339.947098 +system.physmem_0.totalIdleTime 57233116090 +system.physmem_0.memoryStateTime::IDLE 194944250 +system.physmem_0.memoryStateTime::REF 806364000 +system.physmem_0.memoryStateTime::SREF 39558059500 +system.physmem_0.memoryStateTime::PRE_PDN 8522710566 +system.physmem_0.memoryStateTime::ACT 286661660 +system.physmem_0.memoryStateTime::ACT_PDN 9152346024 +system.physmem_1.actEnergy 5255040 +system.physmem_1.preEnergy 2785530 +system.physmem_1.readEnergy 56527380 +system.physmem_1.writeEnergy 114840 +system.physmem_1.refreshEnergy 247699920.000000 +system.physmem_1.actBackEnergy 125328180 +system.physmem_1.preBackEnergy 13397280 +system.physmem_1.actPowerDownEnergy 772336890 +system.physmem_1.prePowerDownEnergy 242624160 +system.physmem_1.selfRefreshEnergy 13451278005 +system.physmem_1.totalEnergy 14917407225 +system.physmem_1.averagePower 254.906533 +system.physmem_1.totalIdleTime 58211272096 +system.physmem_1.memoryStateTime::IDLE 21634250 +system.physmem_1.memoryStateTime::REF 105218000 +system.physmem_1.memoryStateTime::SREF 55885668250 +system.physmem_1.memoryStateTime::PRE_PDN 631842954 +system.physmem_1.memoryStateTime::ACT 182961654 +system.physmem_1.memoryStateTime::ACT_PDN 1693760892 +system.pwrStateResidencyTicks::UNDEFINED 58521086000 +system.cpu.branchPred.lookups 28121660 +system.cpu.branchPred.condPredicted 23134709 +system.cpu.branchPred.condIncorrect 844714 +system.cpu.branchPred.BTBLookups 11731332 +system.cpu.branchPred.BTBHits 11630363 +system.cpu.branchPred.BTBCorrect 0 +system.cpu.branchPred.BTBHitPct 99.139322 +system.cpu.branchPred.usedRAS 80725 +system.cpu.branchPred.RASInCorrect 95 +system.cpu.branchPred.indirectLookups 28301 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---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini index c6db85421..d6f970870 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini @@ -85,6 +85,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -94,14 +95,14 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -115,6 +116,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -127,15 +129,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dtb] type=SparcTLB @@ -145,14 +148,14 @@ size=64 [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -166,6 +169,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -178,15 +182,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=SparcInterrupts @@ -204,14 +209,14 @@ size=64 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -225,6 +230,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -237,15 +243,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -281,7 +288,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=mcf mcf.in cwd=build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing drivers= @@ -290,14 +297,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/sparc/linux/mcf +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/sparc/linux/mcf gid=100 -input=/arm/projectscratch/randd/systems/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=55300000000 system=system uid=100 @@ -321,6 +329,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -332,7 +341,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -340,6 +349,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -348,6 +364,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -355,7 +372,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:268435455 +range=0:268435455:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr index aadc3d011..c0b55d123 100755 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout index 8bd59a796..1f1ba7a8d 100755 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-ti gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:30:06 -gem5 started Jul 21 2016 14:30:36 -gem5 executing on e108600-lin, pid 38669 -command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/10.mcf/sparc/linux/simple-timing +gem5 compiled Apr 3 2017 18:41:19 +gem5 started Apr 3 2017 18:43:33 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 66471 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/10.mcf/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... MCF SPEC version 1.6.I by Andreas Loebel @@ -26,4 +25,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 361597758500 because target called exit() +Exiting @ tick 361613361500 because exiting with last active thread context diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index 33d560709..7f71ad751 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -1,541 +1,541 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.361613 # Number of seconds simulated -sim_ticks 361613361500 # Number of ticks simulated -final_tick 361613361500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1844871 # Simulator instruction rate (inst/s) -host_op_rate 1844948 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2736100211 # Simulator tick rate (ticks/s) -host_mem_usage 385448 # Number of bytes of host memory used -host_seconds 132.16 # Real time elapsed on the host -sim_insts 243825150 # Number of instructions simulated -sim_ops 243835265 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory -system.physmem.bytes_read::total 998592 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 56256 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 155569 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2605921 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2761491 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 155569 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 155569 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 155569 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2605921 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2761491 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.numSyscalls 443 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 361613361500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 723226723 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 243825150 # Number of instructions committed -system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses -system.cpu.num_func_calls 4252956 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls -system.cpu.num_int_insts 194726494 # number of integer instructions -system.cpu.num_fp_insts 11630 # number of float instructions -system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read -system.cpu.num_int_register_writes 215451553 # number of times the integer registers were written -system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read -system.cpu.num_fp_register_writes 90 # number of times the floating registers were written -system.cpu.num_mem_refs 105711441 # number of memory refs -system.cpu.num_load_insts 82803521 # Number of load instructions -system.cpu.num_store_insts 22907920 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 723226722.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 29302884 # Number of branches fetched -system.cpu.op_class::No_OpClass 28877736 11.81% 11.81% # Class of executed instruction -system.cpu.op_class::IntAlu 109842388 44.94% 56.75% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatAdd 42 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::MemRead 82803516 33.88% 90.63% # Class of executed instruction -system.cpu.op_class::MemWrite 22896343 9.37% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 11 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 11577 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 244431613 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 935475 # number of replacements -system.cpu.dcache.tags.tagsinuse 3562.404243 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 134415942500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3562.404243 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.869728 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.869728 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1416 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2526 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits -system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits -system.cpu.dcache.overall_hits::total 104182817 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses -system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses -system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses -system.cpu.dcache.overall_misses::total 939567 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11614992000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11614992000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1335530000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1335530000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 102000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 102000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12950522000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12950522000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12950522000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12950522000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13008.793121 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13008.793121 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28591.950332 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28591.950332 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 25500 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 25500 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13783.500272 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13783.500272 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13783.500272 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13783.500272 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks -system.cpu.dcache.writebacks::total 935266 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10722135000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10722135000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1288820000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1288820000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 98000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 98000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12010955000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12010955000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12010955000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12010955000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12008.793121 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12008.793121 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27591.950332 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27591.950332 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 24500 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 24500 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12783.500272 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12783.500272 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12783.500272 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12783.500272 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 25 # number of replacements -system.cpu.icache.tags.tagsinuse 725.403723 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 725.403723 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.354201 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.354201 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 781 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.418457 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 488843880 # Number of tag accesses -system.cpu.icache.tags.data_accesses 488843880 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 244420617 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 244420617 # number of overall hits -system.cpu.icache.overall_hits::total 244420617 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 882 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 882 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 882 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses -system.cpu.icache.overall_misses::total 882 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 55422500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 55422500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 55422500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 55422500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 55422500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 55422500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 244421499 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 244421499 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 244421499 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62837.301587 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 62837.301587 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 62837.301587 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 62837.301587 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 62837.301587 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 62837.301587 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 25 # number of writebacks -system.cpu.icache.writebacks::total 25 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 882 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 882 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54540500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 54540500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54540500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 54540500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54540500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 54540500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61837.301587 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61837.301587 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61837.301587 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 61837.301587 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61837.301587 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 61837.301587 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 10855.563013 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1860349 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 15603 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 119.230212 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.626846 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 10116.936167 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.308744 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.331285 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15603 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15465 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.476166 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 15023219 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 15023219 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 935266 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 935266 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 25 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 25 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 32147 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 32147 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 892700 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 892700 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 924847 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 924850 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 924847 # number of overall hits -system.cpu.l2cache.overall_hits::total 924850 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 14567 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 14567 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 879 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 879 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 157 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 157 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 879 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 14724 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 15603 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 14724 # number of overall misses -system.cpu.l2cache.overall_misses::total 15603 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 881303500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 881303500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 53183000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 53183000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9498500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 9498500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 53183000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 890802000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 943985000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 53183000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 890802000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 943985000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 935266 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 935266 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 25 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 25 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 46714 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 882 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 882 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 892857 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 892857 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 882 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 939571 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 940453 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 882 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 939571 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 940453 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.311834 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996599 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000176 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000176 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.015671 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.016591 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.015671 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.016591 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60503.981797 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60503.981797 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60503.981797 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60500.224316 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60503.981797 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60500.224316 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 14567 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 879 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 879 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 157 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 157 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 879 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 14724 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 14724 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 15603 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 735633500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 735633500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 44393000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 44393000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7928500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7928500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44393000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 743562000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 787955000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44393000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 743562000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 787955000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996599 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000176 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000176 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50503.981797 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50503.981797 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50503.981797 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.224316 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50503.981797 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.224316 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1875953 # Total number of requests made to the snoop filter. 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-system.cpu.toL2Bus.trans_dist::WritebackClean 25 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 209 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 882 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 892857 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1789 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814617 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2816406 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 120047616 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 940453 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000001 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.001031 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 940452 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 940453 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1873267500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1323000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 15603 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1036 # Transaction distribution -system.membus.trans_dist::ReadExReq 14567 # Transaction distribution -system.membus.trans_dist::ReadExResp 14567 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1036 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave 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+system.cpu.toL2Bus.snoop_fanout::samples 940453 +system.cpu.toL2Bus.snoop_fanout::mean 0.000001 +system.cpu.toL2Bus.snoop_fanout::stdev 0.001031 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 940452 100.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::1 1 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 1 +system.cpu.toL2Bus.snoop_fanout::total 940453 +system.cpu.toL2Bus.reqLayer0.occupancy 1873267500 +system.cpu.toL2Bus.reqLayer0.utilization 0.5 +system.cpu.toL2Bus.respLayer0.occupancy 1323000 +system.cpu.toL2Bus.respLayer0.utilization 0.0 +system.cpu.toL2Bus.respLayer1.occupancy 1409356500 +system.cpu.toL2Bus.respLayer1.utilization 0.4 +system.membus.snoop_filter.tot_requests 15603 +system.membus.snoop_filter.hit_single_requests 0 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+system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 15603 +system.membus.reqLayer0.occupancy 15606500 +system.membus.reqLayer0.utilization 0.0 +system.membus.respLayer1.occupancy 78015000 +system.membus.respLayer1.utilization 0.0 ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini index e54b7db9f..ebb274721 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=timing @@ -65,7 +66,7 @@ SSITSize=1024 activity=0 backComSize=5 branchPred=system.cpu.branchPred -cachePorts=200 +cacheStorePorts=200 checker=Null clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 @@ -139,6 +140,7 @@ socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -183,10 +185,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -200,6 +202,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -212,15 +215,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dtb] type=X86TLB @@ -313,10 +317,10 @@ pipelined=true [system.cpu.fuPool.FUList3] type=FUDesc -children=opList0 opList1 opList2 +children=opList0 opList1 opList2 opList3 opList4 count=2 eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 [system.cpu.fuPool.FUList3.opList0] type=OpDesc @@ -328,11 +332,25 @@ pipelined=true [system.cpu.fuPool.FUList3.opList1] type=OpDesc eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 opClass=FloatDiv opLat=12 pipelined=false -[system.cpu.fuPool.FUList3.opList2] +[system.cpu.fuPool.FUList3.opList4] type=OpDesc eventq_index=0 opClass=FloatSqrt @@ -341,18 +359,25 @@ pipelined=false [system.cpu.fuPool.FUList4] type=FUDesc -children=opList +children=opList0 opList1 count=0 eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList +opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 -[system.cpu.fuPool.FUList4.opList] +[system.cpu.fuPool.FUList4.opList0] type=OpDesc eventq_index=0 opClass=MemRead opLat=1 pipelined=true +[system.cpu.fuPool.FUList4.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList5] type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 @@ -502,24 +527,31 @@ pipelined=true [system.cpu.fuPool.FUList6] type=FUDesc -children=opList +children=opList0 opList1 count=0 eventq_index=0 -opList=system.cpu.fuPool.FUList6.opList +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 -[system.cpu.fuPool.FUList6.opList] +[system.cpu.fuPool.FUList6.opList0] type=OpDesc eventq_index=0 opClass=MemWrite opLat=1 pipelined=true +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList7] type=FUDesc -children=opList0 opList1 +children=opList0 opList1 opList2 opList3 count=4 eventq_index=0 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 [system.cpu.fuPool.FUList7.opList0] type=OpDesc @@ -535,6 +567,20 @@ opClass=MemWrite opLat=1 pipelined=true +[system.cpu.fuPool.FUList7.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList8] type=FUDesc children=opList @@ -556,10 +602,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -573,6 +619,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -585,15 +632,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=X86LocalApic @@ -643,10 +691,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -660,6 +708,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -672,15 +721,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -716,7 +766,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=mcf mcf.in cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing drivers= @@ -725,14 +775,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/mcf +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/mcf gid=100 -input=/arm/projectscratch/randd/systems/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=55300000000 system=system uid=100 diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr index 36f24465c..5d01a7eba 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr @@ -1,3 +1,6 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout index 9e929c5a5..fa6158a9b 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/sim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 21:08:11 -gem5 executing on e108600-lin, pid 17630 -command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/10.mcf/x86/linux/o3-timing +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:21 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87177 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/10.mcf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... MCF SPEC version 1.6.I by Andreas Loebel @@ -19,13 +18,11 @@ All Rights Reserved. nodes : 500 active arcs : 1905 simplex iterations : 1502 -info: Increasing stack size by one page. flow value : 4990014995 -info: Increasing stack size by one page. new implicit arcs : 23867 active arcs : 25772 simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 66079350000 because target called exit() +Exiting @ tick 65721494500 because exiting with last active thread context diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 492625dc5..b9b8eb4c6 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,1055 +1,1055 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.065721 # Number of seconds simulated -sim_ticks 65721494500 # Number of ticks simulated -final_tick 65721494500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 191999 # Simulator instruction rate (inst/s) -host_op_rate 338080 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 79869594 # Simulator tick rate (ticks/s) -host_mem_usage 415448 # Number of bytes of host memory used -host_seconds 822.86 # Real time elapsed on the host -sim_insts 157988547 # Number of instructions simulated -sim_ops 278192464 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 68800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1892544 # Number of bytes read from this memory -system.physmem.bytes_read::total 1961344 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 68800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 68800 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 19136 # Number of bytes written to this memory -system.physmem.bytes_written::total 19136 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1075 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29571 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30646 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 299 # Number of write requests responded to by this memory -system.physmem.num_writes::total 299 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1046842 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 28796424 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 29843265 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1046842 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1046842 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 291168 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 291168 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 291168 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1046842 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 28796424 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 30134433 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30646 # Number of read requests accepted -system.physmem.writeReqs 299 # Number of write requests accepted -system.physmem.readBursts 30646 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 299 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1952832 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8512 # Total number of bytes read from write queue -system.physmem.bytesWritten 17216 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1961344 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 19136 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 133 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1937 # Per bank write bursts -system.physmem.perBankRdBursts::1 2081 # Per bank write bursts -system.physmem.perBankRdBursts::2 2039 # Per bank write bursts -system.physmem.perBankRdBursts::3 1941 # Per bank write bursts -system.physmem.perBankRdBursts::4 2068 # Per bank write bursts -system.physmem.perBankRdBursts::5 1911 # Per bank write bursts -system.physmem.perBankRdBursts::6 1977 # Per bank write bursts -system.physmem.perBankRdBursts::7 1878 # Per bank write bursts -system.physmem.perBankRdBursts::8 1945 # Per bank write bursts -system.physmem.perBankRdBursts::9 1939 # Per bank write bursts -system.physmem.perBankRdBursts::10 1805 # Per bank write bursts -system.physmem.perBankRdBursts::11 1794 # Per bank write bursts -system.physmem.perBankRdBursts::12 1792 # Per bank write bursts -system.physmem.perBankRdBursts::13 1800 # Per bank write bursts -system.physmem.perBankRdBursts::14 1827 # Per bank write bursts -system.physmem.perBankRdBursts::15 1779 # Per bank write bursts -system.physmem.perBankWrBursts::0 8 # Per bank write bursts -system.physmem.perBankWrBursts::1 125 # Per bank write bursts -system.physmem.perBankWrBursts::2 25 # Per bank write bursts -system.physmem.perBankWrBursts::3 26 # Per bank write bursts -system.physmem.perBankWrBursts::4 54 # Per bank write bursts -system.physmem.perBankWrBursts::5 8 # Per bank write bursts -system.physmem.perBankWrBursts::6 14 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 6 # Per bank write bursts -system.physmem.perBankWrBursts::10 3 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 65721290500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 30646 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 299 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 29942 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 423 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # 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incoming req see -system.physmem.bytesPerActivate::samples 2852 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 690.064516 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 482.522488 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 397.377699 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 418 14.66% 14.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 289 10.13% 24.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 128 4.49% 29.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 119 4.17% 33.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 133 4.66% 38.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 123 4.31% 42.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 83 2.91% 45.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 90 3.16% 48.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 1469 51.51% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2852 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 15 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2030.466667 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 23.801531 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 7801.447410 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 14 93.33% 93.33% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::29696-30719 1 6.67% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 15 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 15 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.933333 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.931540 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.258199 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1 6.67% 6.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 14 93.33% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 15 # Writes before turning the bus around for reads -system.physmem.totQLat 402617750 # Total ticks spent queuing -system.physmem.totMemAccLat 974736500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 152565000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13194.96 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31944.96 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 29.71 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.26 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 29.84 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.29 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.23 # Data bus utilization in percentage -system.physmem.busUtilRead 0.23 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.51 # Average write queue length when enqueuing -system.physmem.readRowHits 27734 # Number of row buffer hits during reads -system.physmem.writeRowHits 187 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.89 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 62.54 # Row buffer hit rate for writes -system.physmem.avgGap 2123809.68 # Average gap between requests -system.physmem.pageHitRate 90.62 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 11052720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 5855685 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 113040480 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 1357200 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 309163920.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 263324610 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 16569120 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 979073610 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 268447200 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 14975920920 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 16943805465 # Total energy per rank (pJ) -system.physmem_0.averagePower 257.812234 # Core power per rank (mW) -system.physmem_0.totalIdleTime 65100637750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 22061500 # Time in different power states -system.physmem_0.memoryStateTime::REF 131194000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 62254705500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 699065250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 467433500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 2147034750 # Time in different power states -system.physmem_1.actEnergy 9374820 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 4967655 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 104822340 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 46980 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 372471840.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 249536310 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 19488480 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 1119740490 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 403290240 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 14835337125 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 17119488570 # Total energy per rank (pJ) -system.physmem_1.averagePower 260.485370 # Core power per rank (mW) -system.physmem_1.totalIdleTime 65120969250 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 28589000 # Time in different power states -system.physmem_1.memoryStateTime::REF 158136000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 61616793750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 1050209250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 412212500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 2455554000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 40406290 # Number of BP lookups -system.cpu.branchPred.condPredicted 40406290 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1431845 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 26031629 # Number of BTB lookups -system.cpu.branchPred.BTBHits 0 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6025963 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 91921 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 26031629 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 20992529 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5039100 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 530263 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 444 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 65721494500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 131442990 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30464048 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 219898668 # Number of instructions fetch has processed -system.cpu.fetch.Branches 40406290 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 27018492 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 99269738 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2979935 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 465 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 7592 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 128961 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 50 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 174 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 29660171 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 359072 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 17 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 131360995 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.946103 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.409063 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 65827184 50.11% 50.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4032527 3.07% 53.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3600376 2.74% 55.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6081929 4.63% 60.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7728911 5.88% 66.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5535416 4.21% 70.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3331669 2.54% 73.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2842658 2.16% 75.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 32380325 24.65% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 131360995 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.307405 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.672959 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15255907 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 64520496 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 40208811 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9885814 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1489967 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 362265652 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1489967 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 20796133 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 11129664 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 23832 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 44255424 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 53665975 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 352608748 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 23342 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 777450 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 46732943 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5205031 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 354925639 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 934456502 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 575559102 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 21159 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 75712892 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 482 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 483 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 64647332 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 112313472 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 38475522 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 51426374 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8868395 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 343765046 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3883 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 317634440 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 163759 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 65576465 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 101836454 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3438 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 131360995 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.418027 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.167913 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 35651981 27.14% 27.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 20061286 15.27% 42.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17078933 13.00% 55.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17586289 13.39% 68.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 15273572 11.63% 80.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 12870930 9.80% 90.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 6718617 5.11% 95.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4059315 3.09% 98.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2060072 1.57% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 131360995 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 367555 8.92% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.92% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 3559749 86.40% 95.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 191317 4.64% 99.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 13 0.00% 99.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 1395 0.03% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 33339 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 181647745 57.19% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11501 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 497 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 296 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101245285 31.87% 89.08% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 34690277 10.92% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 508 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 4992 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 317634440 # Type of FU issued -system.cpu.iq.rate 2.416519 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4120029 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012971 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 770896978 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 409373525 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 313389776 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 16685 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 31480 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 3775 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 321713926 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7204 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 57497351 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 21534087 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 66072 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 62227 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 7035770 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4204 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 141777 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1489967 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8057522 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2987683 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 343768929 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 139556 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 112313472 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 38475522 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1604 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2862 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2991864 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 62227 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 520614 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1090823 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1611437 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 315197484 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 100490397 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2436956 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 134782236 # number of memory reference insts executed -system.cpu.iew.exec_branches 32089039 # Number of branches executed -system.cpu.iew.exec_stores 34291839 # Number of stores executed -system.cpu.iew.exec_rate 2.397979 # Inst execution rate -system.cpu.iew.wb_sent 314036708 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 313393551 # cumulative count of insts written-back -system.cpu.iew.wb_producers 237399400 # num instructions producing a value -system.cpu.iew.wb_consumers 342887037 # num instructions consuming a value -system.cpu.iew.wb_rate 2.384255 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692355 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 65692241 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1439325 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 121896437 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.282203 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.051706 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 56939574 46.71% 46.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16454719 13.50% 60.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 11025665 9.05% 69.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8756483 7.18% 76.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2109912 1.73% 78.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1768746 1.45% 79.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 935268 0.77% 80.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 726580 0.60% 80.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 23179490 19.02% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 121896437 # Number of insts commited each cycle -system.cpu.commit.committedInsts 157988547 # Number of instructions committed -system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 122219137 # Number of memory references committed -system.cpu.commit.loads 90779385 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 29309705 # Number of branches committed -system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. -system.cpu.commit.int_insts 278169481 # Number of committed integer instructions. -system.cpu.commit.function_calls 4237596 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 16695 0.01% 0.01% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 155945353 56.06% 56.06% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 10938 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 329 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 12 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.07% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 90779371 32.63% 88.70% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 31439738 11.30% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 14 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 14 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction -system.cpu.commit.bw_lim_events 23179490 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 442601652 # The number of ROB reads -system.cpu.rob.rob_writes 697313320 # The number of ROB writes -system.cpu.timesIdled 909 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 81995 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 157988547 # Number of Instructions Simulated -system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.831978 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.831978 # CPI: Total CPI of All Threads -system.cpu.ipc 1.201955 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.201955 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 502529726 # number of integer regfile reads -system.cpu.int_regfile_writes 247564665 # number of integer regfile writes -system.cpu.fp_regfile_reads 3566 # number of floating regfile reads -system.cpu.fp_regfile_writes 731 # number of floating regfile writes -system.cpu.cc_regfile_reads 108994485 # number of cc regfile reads -system.cpu.cc_regfile_writes 65428204 # number of cc regfile writes -system.cpu.misc_regfile_reads 201784346 # number of misc regfile reads -system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2073509 # number of replacements -system.cpu.dcache.tags.tagsinuse 4067.268199 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 71482624 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2077605 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 34.406263 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 21075173500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4067.268199 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.992985 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.992985 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 504 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 3445 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 147 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 150633517 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 150633517 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 40136683 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 40136683 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31345941 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31345941 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 71482624 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 71482624 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 71482624 # number of overall hits -system.cpu.dcache.overall_hits::total 71482624 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2701521 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2701521 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 93811 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 93811 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2795332 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2795332 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2795332 # number of overall misses -system.cpu.dcache.overall_misses::total 2795332 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32454671000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32454671000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3177582491 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3177582491 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35632253491 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35632253491 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35632253491 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35632253491 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 42838204 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 42838204 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 74277956 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 74277956 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 74277956 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 74277956 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.063063 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.063063 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002984 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002984 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12013.480924 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12013.480924 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33872.173743 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33872.173743 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12747.055982 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12747.055982 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12747.055982 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12747.055982 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 219709 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 682 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 43158 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 6 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.090806 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 113.666667 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2066902 # number of writebacks -system.cpu.dcache.writebacks::total 2066902 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 705827 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 705827 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11900 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 11900 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 717727 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 717727 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 717727 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 717727 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1995694 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1995694 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81911 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 81911 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2077605 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2077605 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2077605 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2077605 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24272933500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24272933500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3020316491 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3020316491 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27293249991 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 27293249991 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27293249991 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 27293249991 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046587 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046587 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002605 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002605 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027971 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.027971 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027971 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027971 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12162.652942 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12162.652942 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36873.148796 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36873.148796 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13136.881164 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13136.881164 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13136.881164 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13136.881164 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 86 # number of replacements -system.cpu.icache.tags.tagsinuse 865.699388 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 29658716 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1101 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 26937.980018 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 865.699388 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.422705 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.422705 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1015 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 900 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.495605 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 59321439 # Number of tag accesses -system.cpu.icache.tags.data_accesses 59321439 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 29658716 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 29658716 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 29658716 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 29658716 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 29658716 # number of overall hits -system.cpu.icache.overall_hits::total 29658716 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1453 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1453 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1453 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1453 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1453 # number of overall misses -system.cpu.icache.overall_misses::total 1453 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 154504998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 154504998 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 154504998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 154504998 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 154504998 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 154504998 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 29660169 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 29660169 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 29660169 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 29660169 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 29660169 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 29660169 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000049 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000049 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000049 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000049 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000049 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000049 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 106335.167240 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 106335.167240 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 106335.167240 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 106335.167240 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 106335.167240 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 106335.167240 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4008 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 235.764706 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 86 # number of writebacks -system.cpu.icache.writebacks::total 86 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 352 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 352 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 352 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 352 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 352 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 352 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1101 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1101 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1101 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1101 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1101 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1101 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 113239998 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 113239998 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 113239998 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 113239998 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 113239998 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 113239998 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000037 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000037 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000037 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 102851.950954 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 102851.950954 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 102851.950954 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 102851.950954 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 102851.950954 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 102851.950954 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 680 # number of replacements -system.cpu.l2cache.tags.tagsinuse 21650.115816 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4121613 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 30665 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 134.407729 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 3.138386 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 704.921194 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 20942.056236 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000096 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.021512 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.639101 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.660709 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 29985 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 172 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 54 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29640 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.915070 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 33248889 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 33248889 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 2066902 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2066902 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 86 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 86 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 52946 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 52946 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 26 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 26 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1995088 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1995088 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 26 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2048034 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2048060 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 26 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2048034 # number of overall hits -system.cpu.l2cache.overall_hits::total 2048060 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 28996 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 28996 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1075 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 1075 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 575 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 575 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1075 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 29571 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 30646 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1075 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 29571 # number of overall misses -system.cpu.l2cache.overall_misses::total 30646 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2341147500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2341147500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 111300000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 111300000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 88414500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 88414500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 111300000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 2429562000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 2540862000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 111300000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 2429562000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 2540862000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 2066902 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 2066902 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 86 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 86 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 81942 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 81942 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1101 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1101 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1995663 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1995663 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1101 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2077605 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2078706 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1101 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2077605 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2078706 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.353860 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.353860 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.976385 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.976385 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000288 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000288 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.976385 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.014233 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.014743 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.976385 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.014233 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.014743 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80740.360739 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80740.360739 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 103534.883721 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 103534.883721 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 153764.347826 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 153764.347826 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 103534.883721 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82160.292178 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 82910.069830 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 103534.883721 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82160.292178 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82910.069830 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 299 # number of writebacks -system.cpu.l2cache.writebacks::total 299 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28996 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 28996 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1075 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1075 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 575 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 575 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1075 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 29571 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 30646 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1075 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 29571 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 30646 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2051187500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2051187500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 100550000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 100550000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 82664500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 82664500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 100550000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2133852000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 2234402000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 100550000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2133852000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 2234402000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353860 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353860 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.976385 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.976385 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000288 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000288 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.976385 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014233 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014743 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.976385 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014233 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014743 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70740.360739 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70740.360739 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 93534.883721 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 93534.883721 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 143764.347826 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 143764.347826 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 93534.883721 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72160.292178 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72910.069830 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 93534.883721 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72160.292178 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72910.069830 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4152301 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2073596 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 330 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 330 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1996764 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2067201 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 86 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6988 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 81942 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 81942 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1101 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1995663 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2288 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6228719 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6231007 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 75968 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265248448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 265324416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 680 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 19136 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2079386 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000170 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.013047 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2079032 99.98% 99.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 354 0.02% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2079386 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4143138500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1652498 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3116407500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 4.7 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 30996 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 350 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1650 # Transaction distribution -system.membus.trans_dist::WritebackDirty 299 # Transaction distribution -system.membus.trans_dist::CleanEvict 51 # Transaction distribution -system.membus.trans_dist::ReadExReq 28996 # Transaction distribution -system.membus.trans_dist::ReadExResp 28996 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1650 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61642 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61642 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 61642 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1980480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1980480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1980480 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 30646 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 30646 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 30646 # Request fanout histogram -system.membus.reqLayer0.occupancy 43591500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 161486250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +sim_seconds 0.065721 +sim_ticks 65721494500 +final_tick 65721494500 +sim_freq 1000000000000 +host_inst_rate 83517 +host_op_rate 147060 +host_tick_rate 34742064 +host_mem_usage 427260 +host_seconds 1891.70 +sim_insts 157988547 +sim_ops 278192464 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 65721494500 +system.physmem.bytes_read::cpu.inst 68800 +system.physmem.bytes_read::cpu.data 1892544 +system.physmem.bytes_read::total 1961344 +system.physmem.bytes_inst_read::cpu.inst 68800 +system.physmem.bytes_inst_read::total 68800 +system.physmem.bytes_written::writebacks 19136 +system.physmem.bytes_written::total 19136 +system.physmem.num_reads::cpu.inst 1075 +system.physmem.num_reads::cpu.data 29571 +system.physmem.num_reads::total 30646 +system.physmem.num_writes::writebacks 299 +system.physmem.num_writes::total 299 +system.physmem.bw_read::cpu.inst 1046842 +system.physmem.bw_read::cpu.data 28796424 +system.physmem.bw_read::total 29843265 +system.physmem.bw_inst_read::cpu.inst 1046842 +system.physmem.bw_inst_read::total 1046842 +system.physmem.bw_write::writebacks 291168 +system.physmem.bw_write::total 291168 +system.physmem.bw_total::writebacks 291168 +system.physmem.bw_total::cpu.inst 1046842 +system.physmem.bw_total::cpu.data 28796424 +system.physmem.bw_total::total 30134433 +system.physmem.readReqs 30646 +system.physmem.writeReqs 299 +system.physmem.readBursts 30646 +system.physmem.writeBursts 299 +system.physmem.bytesReadDRAM 1952832 +system.physmem.bytesReadWrQ 8512 +system.physmem.bytesWritten 17216 +system.physmem.bytesReadSys 1961344 +system.physmem.bytesWrittenSys 19136 +system.physmem.servicedByWrQ 133 +system.physmem.mergedWrBursts 0 +system.physmem.neitherReadNorWriteReqs 0 +system.physmem.perBankRdBursts::0 1937 +system.physmem.perBankRdBursts::1 2081 +system.physmem.perBankRdBursts::2 2039 +system.physmem.perBankRdBursts::3 1941 +system.physmem.perBankRdBursts::4 2068 +system.physmem.perBankRdBursts::5 1911 +system.physmem.perBankRdBursts::6 1977 +system.physmem.perBankRdBursts::7 1878 +system.physmem.perBankRdBursts::8 1945 +system.physmem.perBankRdBursts::9 1939 +system.physmem.perBankRdBursts::10 1805 +system.physmem.perBankRdBursts::11 1794 +system.physmem.perBankRdBursts::12 1792 +system.physmem.perBankRdBursts::13 1800 +system.physmem.perBankRdBursts::14 1827 +system.physmem.perBankRdBursts::15 1779 +system.physmem.perBankWrBursts::0 8 +system.physmem.perBankWrBursts::1 125 +system.physmem.perBankWrBursts::2 25 +system.physmem.perBankWrBursts::3 26 +system.physmem.perBankWrBursts::4 54 +system.physmem.perBankWrBursts::5 8 +system.physmem.perBankWrBursts::6 14 +system.physmem.perBankWrBursts::7 0 +system.physmem.perBankWrBursts::8 0 +system.physmem.perBankWrBursts::9 6 +system.physmem.perBankWrBursts::10 3 +system.physmem.perBankWrBursts::11 0 +system.physmem.perBankWrBursts::12 0 +system.physmem.perBankWrBursts::13 0 +system.physmem.perBankWrBursts::14 0 +system.physmem.perBankWrBursts::15 0 +system.physmem.numRdRetry 0 +system.physmem.numWrRetry 0 +system.physmem.totGap 65721290500 +system.physmem.readPktSize::0 0 +system.physmem.readPktSize::1 0 +system.physmem.readPktSize::2 0 +system.physmem.readPktSize::3 0 +system.physmem.readPktSize::4 0 +system.physmem.readPktSize::5 0 +system.physmem.readPktSize::6 30646 +system.physmem.writePktSize::0 0 +system.physmem.writePktSize::1 0 +system.physmem.writePktSize::2 0 +system.physmem.writePktSize::3 0 +system.physmem.writePktSize::4 0 +system.physmem.writePktSize::5 0 +system.physmem.writePktSize::6 299 +system.physmem.rdQLenPdf::0 29942 +system.physmem.rdQLenPdf::1 423 +system.physmem.rdQLenPdf::2 106 +system.physmem.rdQLenPdf::3 36 +system.physmem.rdQLenPdf::4 5 +system.physmem.rdQLenPdf::5 1 +system.physmem.rdQLenPdf::6 0 +system.physmem.rdQLenPdf::7 0 +system.physmem.rdQLenPdf::8 0 +system.physmem.rdQLenPdf::9 0 +system.physmem.rdQLenPdf::10 0 +system.physmem.rdQLenPdf::11 0 +system.physmem.rdQLenPdf::12 0 +system.physmem.rdQLenPdf::13 0 +system.physmem.rdQLenPdf::14 0 +system.physmem.rdQLenPdf::15 0 +system.physmem.rdQLenPdf::16 0 +system.physmem.rdQLenPdf::17 0 +system.physmem.rdQLenPdf::18 0 +system.physmem.rdQLenPdf::19 0 +system.physmem.rdQLenPdf::20 0 +system.physmem.rdQLenPdf::21 0 +system.physmem.rdQLenPdf::22 0 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+system.physmem.wrQLenPdf::22 16 +system.physmem.wrQLenPdf::23 16 +system.physmem.wrQLenPdf::24 16 +system.physmem.wrQLenPdf::25 16 +system.physmem.wrQLenPdf::26 16 +system.physmem.wrQLenPdf::27 16 +system.physmem.wrQLenPdf::28 16 +system.physmem.wrQLenPdf::29 16 +system.physmem.wrQLenPdf::30 15 +system.physmem.wrQLenPdf::31 15 +system.physmem.wrQLenPdf::32 15 +system.physmem.wrQLenPdf::33 0 +system.physmem.wrQLenPdf::34 0 +system.physmem.wrQLenPdf::35 0 +system.physmem.wrQLenPdf::36 0 +system.physmem.wrQLenPdf::37 0 +system.physmem.wrQLenPdf::38 0 +system.physmem.wrQLenPdf::39 0 +system.physmem.wrQLenPdf::40 0 +system.physmem.wrQLenPdf::41 0 +system.physmem.wrQLenPdf::42 0 +system.physmem.wrQLenPdf::43 0 +system.physmem.wrQLenPdf::44 0 +system.physmem.wrQLenPdf::45 0 +system.physmem.wrQLenPdf::46 0 +system.physmem.wrQLenPdf::47 0 +system.physmem.wrQLenPdf::48 0 +system.physmem.wrQLenPdf::49 0 +system.physmem.wrQLenPdf::50 0 +system.physmem.wrQLenPdf::51 0 +system.physmem.wrQLenPdf::52 0 +system.physmem.wrQLenPdf::53 0 +system.physmem.wrQLenPdf::54 0 +system.physmem.wrQLenPdf::55 0 +system.physmem.wrQLenPdf::56 0 +system.physmem.wrQLenPdf::57 0 +system.physmem.wrQLenPdf::58 0 +system.physmem.wrQLenPdf::59 0 +system.physmem.wrQLenPdf::60 0 +system.physmem.wrQLenPdf::61 0 +system.physmem.wrQLenPdf::62 0 +system.physmem.wrQLenPdf::63 0 +system.physmem.bytesPerActivate::samples 2852 +system.physmem.bytesPerActivate::mean 690.064516 +system.physmem.bytesPerActivate::gmean 482.522488 +system.physmem.bytesPerActivate::stdev 397.377699 +system.physmem.bytesPerActivate::0-127 418 14.66% 14.66% +system.physmem.bytesPerActivate::128-255 289 10.13% 24.79% +system.physmem.bytesPerActivate::256-383 128 4.49% 29.28% +system.physmem.bytesPerActivate::384-511 119 4.17% 33.45% +system.physmem.bytesPerActivate::512-639 133 4.66% 38.11% +system.physmem.bytesPerActivate::640-767 123 4.31% 42.43% +system.physmem.bytesPerActivate::768-895 83 2.91% 45.34% +system.physmem.bytesPerActivate::896-1023 90 3.16% 48.49% +system.physmem.bytesPerActivate::1024-1151 1469 51.51% 100.00% +system.physmem.bytesPerActivate::total 2852 +system.physmem.rdPerTurnAround::samples 15 +system.physmem.rdPerTurnAround::mean 2030.466667 +system.physmem.rdPerTurnAround::gmean 23.801531 +system.physmem.rdPerTurnAround::stdev 7801.447410 +system.physmem.rdPerTurnAround::0-1023 14 93.33% 93.33% +system.physmem.rdPerTurnAround::29696-30719 1 6.67% 100.00% +system.physmem.rdPerTurnAround::total 15 +system.physmem.wrPerTurnAround::samples 15 +system.physmem.wrPerTurnAround::mean 17.933333 +system.physmem.wrPerTurnAround::gmean 17.931540 +system.physmem.wrPerTurnAround::stdev 0.258199 +system.physmem.wrPerTurnAround::17 1 6.67% 6.67% +system.physmem.wrPerTurnAround::18 14 93.33% 100.00% +system.physmem.wrPerTurnAround::total 15 +system.physmem.totQLat 402617750 +system.physmem.totMemAccLat 974736500 +system.physmem.totBusLat 152565000 +system.physmem.avgQLat 13194.96 +system.physmem.avgBusLat 5000.00 +system.physmem.avgMemAccLat 31944.96 +system.physmem.avgRdBW 29.71 +system.physmem.avgWrBW 0.26 +system.physmem.avgRdBWSys 29.84 +system.physmem.avgWrBWSys 0.29 +system.physmem.peakBW 12800.00 +system.physmem.busUtil 0.23 +system.physmem.busUtilRead 0.23 +system.physmem.busUtilWrite 0.00 +system.physmem.avgRdQLen 1.00 +system.physmem.avgWrQLen 12.51 +system.physmem.readRowHits 27734 +system.physmem.writeRowHits 187 +system.physmem.readRowHitRate 90.89 +system.physmem.writeRowHitRate 62.54 +system.physmem.avgGap 2123809.68 +system.physmem.pageHitRate 90.62 +system.physmem_0.actEnergy 11052720 +system.physmem_0.preEnergy 5855685 +system.physmem_0.readEnergy 113040480 +system.physmem_0.writeEnergy 1357200 +system.physmem_0.refreshEnergy 309163920.000000 +system.physmem_0.actBackEnergy 263324610 +system.physmem_0.preBackEnergy 16569120 +system.physmem_0.actPowerDownEnergy 979073610 +system.physmem_0.prePowerDownEnergy 268447200 +system.physmem_0.selfRefreshEnergy 14975920920 +system.physmem_0.totalEnergy 16943805465 +system.physmem_0.averagePower 257.812234 +system.physmem_0.totalIdleTime 65100637750 +system.physmem_0.memoryStateTime::IDLE 22061500 +system.physmem_0.memoryStateTime::REF 131194000 +system.physmem_0.memoryStateTime::SREF 62254705500 +system.physmem_0.memoryStateTime::PRE_PDN 699065250 +system.physmem_0.memoryStateTime::ACT 467433500 +system.physmem_0.memoryStateTime::ACT_PDN 2147034750 +system.physmem_1.actEnergy 9374820 +system.physmem_1.preEnergy 4967655 +system.physmem_1.readEnergy 104822340 +system.physmem_1.writeEnergy 46980 +system.physmem_1.refreshEnergy 372471840.000000 +system.physmem_1.actBackEnergy 249536310 +system.physmem_1.preBackEnergy 19488480 +system.physmem_1.actPowerDownEnergy 1119740490 +system.physmem_1.prePowerDownEnergy 403290240 +system.physmem_1.selfRefreshEnergy 14835337125 +system.physmem_1.totalEnergy 17119488570 +system.physmem_1.averagePower 260.485370 +system.physmem_1.totalIdleTime 65120969250 +system.physmem_1.memoryStateTime::IDLE 28589000 +system.physmem_1.memoryStateTime::REF 158136000 +system.physmem_1.memoryStateTime::SREF 61616793750 +system.physmem_1.memoryStateTime::PRE_PDN 1050209250 +system.physmem_1.memoryStateTime::ACT 412212500 +system.physmem_1.memoryStateTime::ACT_PDN 2455554000 +system.pwrStateResidencyTicks::UNDEFINED 65721494500 +system.cpu.branchPred.lookups 40406290 +system.cpu.branchPred.condPredicted 40406290 +system.cpu.branchPred.condIncorrect 1431845 +system.cpu.branchPred.BTBLookups 26031629 +system.cpu.branchPred.BTBHits 0 +system.cpu.branchPred.BTBCorrect 0 +system.cpu.branchPred.BTBHitPct 0.000000 +system.cpu.branchPred.usedRAS 6025963 +system.cpu.branchPred.RASInCorrect 91921 +system.cpu.branchPred.indirectLookups 26031629 +system.cpu.branchPred.indirectHits 20992529 +system.cpu.branchPred.indirectMisses 5039100 +system.cpu.branchPredindirectMispredicted 530263 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 65721494500 +system.cpu.apic_clk_domain.clock 8000 +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 65721494500 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 65721494500 +system.cpu.workload.numSyscalls 444 +system.cpu.pwrStateResidencyTicks::ON 65721494500 +system.cpu.numCycles 131442990 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.fetch.icacheStallCycles 30464048 +system.cpu.fetch.Insts 219898668 +system.cpu.fetch.Branches 40406290 +system.cpu.fetch.predictedBranches 27018492 +system.cpu.fetch.Cycles 99269738 +system.cpu.fetch.SquashCycles 2979934 +system.cpu.fetch.TlbCycles 465 +system.cpu.fetch.MiscStallCycles 7592 +system.cpu.fetch.PendingTrapStallCycles 128961 +system.cpu.fetch.PendingQuiesceStallCycles 50 +system.cpu.fetch.IcacheWaitRetryStallCycles 174 +system.cpu.fetch.CacheLines 29660171 +system.cpu.fetch.IcacheSquashes 359072 +system.cpu.fetch.ItlbSquashes 17 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+system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 30646 +system.membus.reqLayer0.occupancy 43591500 +system.membus.reqLayer0.utilization 0.1 +system.membus.respLayer1.occupancy 161486250 +system.membus.respLayer1.utilization 0.2 ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini index 420cd8ed8..03e352749 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=timing @@ -85,6 +86,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -100,14 +102,14 @@ eventq_index=0 [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -121,6 +123,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -133,15 +136,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dtb] type=X86TLB @@ -166,14 +170,14 @@ port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -187,6 +191,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -199,15 +204,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=X86LocalApic @@ -253,14 +259,14 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -274,6 +280,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -286,15 +293,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -330,7 +338,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=mcf mcf.in cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing drivers= @@ -339,14 +347,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/mcf +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/mcf gid=100 -input=/arm/projectscratch/randd/systems/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=55300000000 system=system uid=100 @@ -370,6 +379,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -381,7 +391,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -389,6 +399,13 @@ width=16 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -397,6 +414,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -404,7 +422,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:268435455 +range=0:268435455:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr index aadc3d011..c0b55d123 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout index 657298ab6..712b4d61b 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:35:23 -gem5 started Jul 21 2016 14:36:18 -gem5 executing on e108600-lin, pid 18549 -command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/10.mcf/x86/linux/simple-timing +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:08:56 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 90898 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/10.mcf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... MCF SPEC version 1.6.I by Andreas Loebel @@ -26,4 +25,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 366199170500 because target called exit() +Exiting @ tick 366229314500 because exiting with last active thread context diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index 957a0aa1f..275d179a2 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,541 +1,541 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.366229 # Number of seconds simulated -sim_ticks 366229314500 # Number of ticks simulated -final_tick 366229314500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1002365 # Simulator instruction rate (inst/s) -host_op_rate 1765004 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2323557450 # Simulator tick rate (ticks/s) -host_mem_usage 412036 # Number of bytes of host memory used -host_seconds 157.62 # Real time elapsed on the host -sim_insts 157988548 # Number of instructions simulated -sim_ops 278192465 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1871552 # Number of bytes read from this memory -system.physmem.bytes_read::total 1922944 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 51392 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 51392 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6656 # Number of bytes written to this memory -system.physmem.bytes_written::total 6656 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 803 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29243 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30046 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 104 # Number of write requests responded to by this memory -system.physmem.num_writes::total 104 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 140327 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5110328 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 5250656 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 140327 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 140327 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 18174 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 18174 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 18174 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 140327 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5110328 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5268830 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 444 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 366229314500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 732458629 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 157988548 # Number of instructions committed -system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 278169482 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses -system.cpu.num_func_calls 8475189 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls -system.cpu.num_int_insts 278169482 # number of integer instructions -system.cpu.num_fp_insts 40 # number of float instructions -system.cpu.num_int_register_reads 635379407 # number of times the integer registers were read -system.cpu.num_int_register_writes 217447860 # number of times the integer registers were written -system.cpu.num_fp_register_reads 40 # number of times the floating registers were read -system.cpu.num_fp_register_writes 26 # number of times the floating registers were written -system.cpu.num_cc_register_reads 104140596 # number of times the CC registers were read -system.cpu.num_cc_register_writes 61764861 # number of times the CC registers were written -system.cpu.num_mem_refs 122219137 # number of memory refs -system.cpu.num_load_insts 90779385 # Number of load instructions -system.cpu.num_store_insts 31439752 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 732458628.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 29309705 # Number of branches fetched -system.cpu.op_class::No_OpClass 16695 0.01% 0.01% # Class of executed instruction -system.cpu.op_class::IntAlu 155945354 56.06% 56.06% # Class of executed instruction -system.cpu.op_class::IntMult 10938 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::IntDiv 329 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatAdd 12 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::MemRead 90779371 32.63% 88.70% # Class of executed instruction -system.cpu.op_class::MemWrite 31439738 11.30% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 14 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 14 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 278192465 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2062733 # number of replacements -system.cpu.dcache.tags.tagsinuse 4076.272883 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 126128435500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4076.272883 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995184 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995184 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1776 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2198 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 246505227 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 246505227 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31333643 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 120152370 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 120152370 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 120152370 # number of overall hits -system.cpu.dcache.overall_hits::total 120152370 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses -system.cpu.dcache.overall_misses::total 2066829 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 25500310500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 25500310500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2830649000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2830649000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28330959500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28330959500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28330959500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28330959500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 90779447 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 90779447 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 122219199 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 122219199 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 122219199 # number of overall (read+write) accesses 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-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26676.804041 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 26676.804041 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13707.452092 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13707.452092 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13707.452092 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13707.452092 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access 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-system.cpu.icache.tags.data_accesses 435393136 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 217695356 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 217695356 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 217695356 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 217695356 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 217695356 # number of overall hits -system.cpu.icache.overall_hits::total 217695356 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 808 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 808 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses 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-system.cpu.icache.demand_avg_miss_latency::cpu.inst 62698.019802 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 62698.019802 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 62698.019802 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 62698.019802 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 24 # number of writebacks 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blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 45 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29568 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.907349 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 33073199 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 33073199 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 2062482 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2062482 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 24 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 24 # number of WritebackClean hits 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-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.993812 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.993812 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000112 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000112 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993812 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.014149 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.014532 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993812 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.014149 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.014532 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60501.068082 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60501.068082 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60504.358655 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60504.358655 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60504.358655 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60501.060083 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60501.148239 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60504.358655 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60501.060083 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60501.148239 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 104 # number of writebacks -system.cpu.l2cache.writebacks::total 104 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29024 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 29024 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 803 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 803 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 219 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 219 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 29243 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 30046 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 29243 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 30046 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1465743000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1465743000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 40555000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 40555000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11059500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11059500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40555000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1476802500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1517357500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40555000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1476802500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1517357500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273530 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273530 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.993812 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000112 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000112 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014149 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014532 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014149 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014532 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50501.068082 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50501.068082 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50504.358655 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50504.358655 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50504.358655 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.060083 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.148239 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50504.358655 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.060083 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.148239 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4130394 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2062757 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 197 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 197 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2062586 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 24 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 462 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 106109 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 106109 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 808 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1960720 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1640 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6196391 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6198031 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 53248 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264275904 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 264329152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 315 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 6656 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2067952 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000095 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.009760 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2067755 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 197 0.01% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2067952 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4127703000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1212000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3100243500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 30164 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 118 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1022 # Transaction distribution -system.membus.trans_dist::WritebackDirty 104 # Transaction distribution -system.membus.trans_dist::CleanEvict 14 # Transaction distribution -system.membus.trans_dist::ReadExReq 29024 # Transaction distribution -system.membus.trans_dist::ReadExResp 29024 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1022 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60210 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60210 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 60210 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1929600 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 30046 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 30046 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 30046 # Request fanout histogram -system.membus.reqLayer0.occupancy 30614500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 150230000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +sim_seconds 0.366229 +sim_ticks 366229314500 +final_tick 366229314500 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8475189 +system.cpu.num_conditional_control_insts 18628007 +system.cpu.num_int_insts 278169482 +system.cpu.num_fp_insts 40 +system.cpu.num_int_register_reads 635379407 +system.cpu.num_int_register_writes 217447860 +system.cpu.num_fp_register_reads 40 +system.cpu.num_fp_register_writes 26 +system.cpu.num_cc_register_reads 104140596 +system.cpu.num_cc_register_writes 61764861 +system.cpu.num_mem_refs 122219137 +system.cpu.num_load_insts 90779385 +system.cpu.num_store_insts 31439752 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 732458629 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 29309705 +system.cpu.op_class::No_OpClass 16695 0.01% 0.01% +system.cpu.op_class::IntAlu 155945354 56.06% 56.06% +system.cpu.op_class::IntMult 10938 0.00% 56.07% +system.cpu.op_class::IntDiv 329 0.00% 56.07% +system.cpu.op_class::FloatAdd 12 0.00% 56.07% +system.cpu.op_class::FloatCmp 0 0.00% 56.07% +system.cpu.op_class::FloatCvt 0 0.00% 56.07% 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+system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 1 +system.cpu.toL2Bus.snoop_fanout::total 2067952 +system.cpu.toL2Bus.reqLayer0.occupancy 4127703000 +system.cpu.toL2Bus.reqLayer0.utilization 1.1 +system.cpu.toL2Bus.respLayer0.occupancy 1212000 +system.cpu.toL2Bus.respLayer0.utilization 0.0 +system.cpu.toL2Bus.respLayer1.occupancy 3100243500 +system.cpu.toL2Bus.respLayer1.utilization 0.8 +system.membus.snoop_filter.tot_requests 30164 +system.membus.snoop_filter.hit_single_requests 118 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 366229314500 +system.membus.trans_dist::ReadResp 1022 +system.membus.trans_dist::WritebackDirty 104 +system.membus.trans_dist::CleanEvict 14 +system.membus.trans_dist::ReadExReq 29024 +system.membus.trans_dist::ReadExResp 29024 +system.membus.trans_dist::ReadSharedReq 1022 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60210 +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60210 +system.membus.pkt_count::total 60210 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929600 +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929600 +system.membus.pkt_size::total 1929600 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 30046 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 30046 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 30046 +system.membus.reqLayer0.occupancy 30614500 +system.membus.reqLayer0.utilization 0.0 +system.membus.respLayer1.occupancy 150230000 +system.membus.respLayer1.utilization 0.0 ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini index 4329f3215..e92ae69a2 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini @@ -65,7 +65,7 @@ SSITSize=1024 activity=0 backComSize=5 branchPred=system.cpu.branchPred -cachePorts=200 +cacheStorePorts=200 checker=Null clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 @@ -141,6 +141,7 @@ socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -176,10 +177,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=6 @@ -193,6 +194,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=8 write_buffers=16 @@ -205,15 +207,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu.dstage2_mmu] type=ArmStage2MMU @@ -316,38 +319,52 @@ pipelined=true [system.cpu.fuPool.FUList2] type=FUDesc -children=opList +children=opList0 opList1 count=1 eventq_index=0 -opList=system.cpu.fuPool.FUList2.opList +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 -[system.cpu.fuPool.FUList2.opList] +[system.cpu.fuPool.FUList2.opList0] type=OpDesc eventq_index=0 opClass=MemRead opLat=2 pipelined=true +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=2 +pipelined=true + [system.cpu.fuPool.FUList3] type=FUDesc -children=opList +children=opList0 opList1 count=1 eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 -[system.cpu.fuPool.FUList3.opList] +[system.cpu.fuPool.FUList3.opList0] type=OpDesc eventq_index=0 opClass=MemWrite opLat=2 pipelined=true +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=2 +pipelined=true + [system.cpu.fuPool.FUList4] type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27 count=2 eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 +opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27 [system.cpu.fuPool.FUList4.opList00] type=OpDesc @@ -479,7 +496,7 @@ pipelined=true type=OpDesc eventq_index=0 opClass=SimdFloatMultAcc -opLat=1 +opLat=5 pipelined=true [system.cpu.fuPool.FUList4.opList19] @@ -531,6 +548,20 @@ opClass=FloatMult opLat=4 pipelined=true +[system.cpu.fuPool.FUList4.opList26] +type=OpDesc +eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList4.opList27] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + [system.cpu.icache] type=Cache children=tags @@ -538,10 +569,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=1 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=1 is_read_only=true max_miss_count=0 mshrs=2 @@ -555,6 +586,7 @@ response_latency=1 sequential_access=false size=32768 system=system +tag_latency=1 tags=system.cpu.icache.tags tgts_per_mshr=8 write_buffers=8 @@ -567,15 +599,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=1 default_p_state=UNDEFINED eventq_index=0 -hit_latency=1 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=1 [system.cpu.interrupts] type=ArmInterrupts @@ -594,8 +627,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -606,8 +637,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -670,10 +699,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl +data_latency=12 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=12 is_read_only=false max_miss_count=0 mshrs=16 @@ -687,6 +716,7 @@ response_latency=12 sequential_access=false size=1048576 system=system +tag_latency=12 tags=system.cpu.l2cache.tags tgts_per_mshr=8 write_buffers=8 @@ -729,15 +759,16 @@ type=RandomRepl assoc=16 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=12 default_p_state=UNDEFINED eventq_index=0 -hit_latency=12 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=1048576 +tag_latency=12 [system.cpu.toL2Bus] type=CoherentXBar @@ -773,7 +804,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=parser 2.1.dict -batch cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing drivers= @@ -782,14 +813,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/parser +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/parser gid=100 -input=/arm/projectscratch/randd/systems/dist/cpu2000/data/parser/mdred/input/parser.in +input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/parser/mdred/input/parser.in kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=114600000000 system=system uid=100 diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr index caeab8324..edc1e135d 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr @@ -1,4 +1,7 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4] +info: Increasing stack size by one page. +info: Increasing stack size by one page. diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout index 87601728e..9e9d8d4ce 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:43:00 -gem5 executing on e108600-lin, pid 17328 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/arm/linux/o3-timing +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 18:14:44 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 57363 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Reading the dictionary files: ************************************************* @@ -20,12 +19,10 @@ Welcome to the Link Parser -- Version 2.1 Processing sentences in batch mode -info: Increasing stack size by one page. Echoing of input sentence turned on. * as had expected the party to be a success , it was a success * do you know where John 's * he said that , finding that it was impossible to get work as a waiter , he would work as a janitor -info: Increasing stack size by one page. * how fast the program is it * I am wondering whether to invite to the party * I gave him for his birthday it @@ -70,4 +67,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 236034256000 because target called exit() +Exiting @ tick 235850129000 because exiting with last active thread context diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 774d0b356..90cdb7653 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,1276 +1,1276 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.235850 # Number of seconds simulated -sim_ticks 235850129000 # Number of ticks simulated -final_tick 235850129000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 254127 # Simulator instruction rate (inst/s) -host_op_rate 275309 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 118629630 # Simulator tick rate (ticks/s) -host_mem_usage 302132 # Number of bytes of host memory used -host_seconds 1988.12 # Real time elapsed on the host -sim_insts 505234934 # Number of instructions simulated -sim_ops 547348155 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 651264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10497792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 16410048 # Number of bytes read from this memory -system.physmem.bytes_read::total 27559104 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 651264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 651264 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18653440 # Number of bytes written to this memory -system.physmem.bytes_written::total 18653440 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 10176 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 164028 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 256407 # Number of read requests responded to by this memory -system.physmem.num_reads::total 430611 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 291460 # Number of write requests responded to by this memory -system.physmem.num_writes::total 291460 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2761347 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 44510436 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 69578287 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 116850070 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2761347 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2761347 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 79090226 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 79090226 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 79090226 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2761347 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 44510436 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 69578287 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 195940296 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 430611 # Number of read requests accepted -system.physmem.writeReqs 291460 # Number of write requests accepted -system.physmem.readBursts 430611 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 291460 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 27396288 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 162816 # Total number of bytes read from write queue -system.physmem.bytesWritten 18651392 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 27559104 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18653440 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2544 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 9 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 27102 # Per bank write bursts -system.physmem.perBankRdBursts::1 26174 # Per bank write bursts -system.physmem.perBankRdBursts::2 25664 # Per bank write bursts -system.physmem.perBankRdBursts::3 33006 # Per bank write bursts -system.physmem.perBankRdBursts::4 27996 # Per bank write bursts -system.physmem.perBankRdBursts::5 29984 # Per bank write bursts -system.physmem.perBankRdBursts::6 25487 # Per bank write bursts -system.physmem.perBankRdBursts::7 24586 # Per bank write bursts -system.physmem.perBankRdBursts::8 25526 # Per bank write bursts -system.physmem.perBankRdBursts::9 25681 # Per bank write bursts -system.physmem.perBankRdBursts::10 25862 # Per bank write bursts -system.physmem.perBankRdBursts::11 26092 # Per bank write bursts -system.physmem.perBankRdBursts::12 27614 # Per bank write bursts -system.physmem.perBankRdBursts::13 26106 # Per bank write bursts -system.physmem.perBankRdBursts::14 25123 # Per bank write bursts -system.physmem.perBankRdBursts::15 26064 # Per bank write bursts -system.physmem.perBankWrBursts::0 18530 # Per bank write bursts -system.physmem.perBankWrBursts::1 18172 # Per bank write bursts -system.physmem.perBankWrBursts::2 17960 # Per bank write bursts -system.physmem.perBankWrBursts::3 17946 # Per bank write bursts -system.physmem.perBankWrBursts::4 18535 # Per bank write bursts -system.physmem.perBankWrBursts::5 18092 # Per bank write bursts -system.physmem.perBankWrBursts::6 17937 # Per bank write bursts -system.physmem.perBankWrBursts::7 17864 # Per bank write bursts -system.physmem.perBankWrBursts::8 17881 # Per bank write bursts -system.physmem.perBankWrBursts::9 17814 # Per bank write bursts -system.physmem.perBankWrBursts::10 18253 # Per bank write bursts -system.physmem.perBankWrBursts::11 18685 # Per bank write bursts -system.physmem.perBankWrBursts::12 18794 # Per bank write bursts -system.physmem.perBankWrBursts::13 18180 # Per bank write bursts -system.physmem.perBankWrBursts::14 18427 # Per bank write bursts -system.physmem.perBankWrBursts::15 18358 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 235850076500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 430611 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 291460 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 318665 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 60579 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13349 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9026 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7328 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5231 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4311 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3288 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 74 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 37 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6820 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 12035 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 14838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 16182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 16933 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17637 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17893 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 18126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 18306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 18426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 18598 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 18683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 18906 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 18563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17444 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 329170 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 139.885214 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 98.537517 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 178.782393 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 210239 63.87% 63.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 79533 24.16% 88.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 14816 4.50% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7238 2.20% 94.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4909 1.49% 96.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2469 0.75% 96.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1818 0.55% 97.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1563 0.47% 98.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6585 2.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 329170 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17054 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.096224 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 145.074041 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17052 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::18432-19455 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17054 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17054 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.088542 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.022727 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.689258 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 9980 58.52% 58.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 6296 36.92% 95.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 558 3.27% 98.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 128 0.75% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 50 0.29% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 15 0.09% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 10 0.06% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 6 0.04% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 2 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42-43 3 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46-47 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::62-63 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::74-75 2 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17054 # Writes before turning the bus around for reads -system.physmem.totQLat 14249250266 # Total ticks spent queuing -system.physmem.totMemAccLat 22275506516 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2140335000 # Total ticks spent in databus transfers -system.physmem.avgQLat 33287.43 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 52037.43 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 116.16 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 79.08 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 116.85 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 79.09 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.53 # Data bus utilization in percentage -system.physmem.busUtilRead 0.91 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.62 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.13 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.62 # Average write queue length when enqueuing -system.physmem.readRowHits 308139 # Number of row buffer hits during reads -system.physmem.writeRowHits 82177 # Number of row buffer hits during writes -system.physmem.readRowHitRate 71.98 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 28.20 # Row buffer hit rate for writes -system.physmem.avgGap 326630.04 # Average gap between requests -system.physmem.pageHitRate 54.25 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1195207440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 635245050 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1570792860 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 757087920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 15735398640.000004 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 13510945980 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 615046560 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 46117601610 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 17430135360 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 15587831640 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 113161874670 # Total energy per rank (pJ) -system.physmem_0.averagePower 479.804155 # Core power per rank (mW) -system.physmem_0.totalIdleTime 204603400415 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 912794276 # Time in different power states -system.physmem_0.memoryStateTime::REF 6674692000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 58078463500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 45390268663 # Time in different power states -system.physmem_0.memoryStateTime::ACT 23659127059 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 101134783502 # Time in different power states -system.physmem_1.actEnergy 1155130620 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 613955100 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1485605520 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 764166240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 15039011520.000004 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 13474802850 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 604322400 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 42537889890 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 17081497440 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 17718944700 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 110481339780 # Total energy per rank (pJ) -system.physmem_1.averagePower 468.438739 # Core power per rank (mW) -system.physmem_1.totalIdleTime 204713337667 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 914400899 # Time in different power states -system.physmem_1.memoryStateTime::REF 6380142000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 66945121250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 44482448304 # Time in different power states -system.physmem_1.memoryStateTime::ACT 23842248434 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 93285768113 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 174426540 # Number of BP lookups -system.cpu.branchPred.condPredicted 130958868 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7258964 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 89936054 # Number of BTB lookups -system.cpu.branchPred.BTBHits 78903188 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.732544 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12071651 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104612 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 4685817 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 4672093 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 13724 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 53795 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 548 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 235850129000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 471700259 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7689412 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 726848478 # Number of instructions fetch has processed -system.cpu.fetch.Branches 174426540 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 95646932 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 455559849 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14571167 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 7088 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 169 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 15067 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 235109896 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 36736 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 470557168 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.672087 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.189865 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 101222144 21.51% 21.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 131885544 28.03% 49.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 57421464 12.20% 61.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 180028016 38.26% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 470557168 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.369783 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.540912 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32637512 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 125886415 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 282414401 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 22855437 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6763403 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 71909343 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 530427 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 710086582 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 29127059 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6763403 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 63488458 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 61155779 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 40463668 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 273022741 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 25663119 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 681926435 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 12775010 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 10060236 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2531231 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1813266 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 2373970 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 826391408 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2997146717 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 717894841 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 88 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 654095674 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 172295734 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1545774 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1536126 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 43961162 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 142203026 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 67513624 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12913434 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11193544 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 664083030 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2979301 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 608560988 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5743597 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 119714176 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 304959820 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1669 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 470557168 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.293277 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.104886 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 154355830 32.80% 32.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 100909501 21.44% 54.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 145256303 30.87% 85.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 63003898 13.39% 98.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 7030993 1.49% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 643 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 470557168 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 71776446 52.99% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 30 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44249945 32.67% 85.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19436717 14.35% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 9 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 22 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 412327933 67.75% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 351836 0.06% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 133457436 21.93% 89.74% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 62423748 10.26% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 16 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 16 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 608560988 # Type of FU issued -system.cpu.iq.rate 1.290143 # Inst issue rate -system.cpu.iq.fu_busy_cnt 135463169 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.222596 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1828885813 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 786805257 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 593918713 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 97 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 70 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 744024094 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 63 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 7272380 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 26319743 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 24134 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29234 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10653404 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 224604 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 23301 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6763403 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 23756716 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 981361 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 668554311 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 142203026 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 67513624 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1490759 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 256987 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 586437 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29234 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3560929 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3767464 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7328393 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 598121332 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 128978812 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10439656 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1491980 # number of nop insts executed -system.cpu.iew.exec_refs 189925083 # number of memory reference insts executed -system.cpu.iew.exec_branches 131214447 # Number of branches executed -system.cpu.iew.exec_stores 60946271 # Number of stores executed -system.cpu.iew.exec_rate 1.268011 # Inst execution rate -system.cpu.iew.wb_sent 595160432 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 593918729 # cumulative count of insts written-back -system.cpu.iew.wb_producers 349300209 # num instructions producing a value -system.cpu.iew.wb_consumers 571006140 # num instructions consuming a value -system.cpu.iew.wb_rate 1.259102 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611728 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 106531473 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6736784 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 453954004 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.208695 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.885174 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 225266208 49.62% 49.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 116316093 25.62% 75.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43463338 9.57% 84.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 23021553 5.07% 89.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 11663985 2.57% 92.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7751412 1.71% 94.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8276330 1.82% 95.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4247049 0.94% 96.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 13948036 3.07% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 453954004 # Number of insts commited each cycle -system.cpu.commit.committedInsts 506578818 # Number of instructions committed -system.cpu.commit.committedOps 548692039 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 172743503 # Number of memory references committed -system.cpu.commit.loads 115883283 # Number of loads committed -system.cpu.commit.membars 1488542 # Number of memory barriers committed -system.cpu.commit.branches 121552863 # Number of branches committed -system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 448447003 # Number of committed integer instructions. -system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 375609314 68.46% 68.46% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 115883283 21.12% 89.64% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 56860204 10.36% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 16 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 548692039 # Class of committed instruction -system.cpu.commit.bw_lim_events 13948036 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1095222342 # The number of ROB reads -system.cpu.rob.rob_writes 1327086117 # The number of ROB writes -system.cpu.timesIdled 14782 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1143091 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 505234934 # Number of Instructions Simulated -system.cpu.committedOps 547348155 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.933626 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.933626 # CPI: Total CPI of All Threads -system.cpu.ipc 1.071093 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.071093 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 609897818 # number of integer regfile reads -system.cpu.int_regfile_writes 327085541 # number of integer regfile writes -system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 2165040622 # number of cc regfile reads -system.cpu.cc_regfile_writes 376344417 # number of cc regfile writes -system.cpu.misc_regfile_reads 217537377 # number of misc regfile reads -system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2817480 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.627959 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168773991 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2817992 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 59.891579 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 504701000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.627959 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999273 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999273 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 355076080 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 355076080 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 114071383 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114071383 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 51722665 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 51722665 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2778 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2778 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488556 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488556 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 165794048 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 165794048 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 165796826 # number of overall hits -system.cpu.dcache.overall_hits::total 165796826 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4838662 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4838662 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2516384 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2516384 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 10 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 10 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 65 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 65 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 7355046 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7355046 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7355056 # number of overall misses -system.cpu.dcache.overall_misses::total 7355056 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 63735397500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 63735397500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19938555937 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19938555937 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 846000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 846000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 83673953437 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 83673953437 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 83673953437 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 83673953437 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 118910045 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 118910045 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2788 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2788 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488621 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488621 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 173149094 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 173149094 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 173151882 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 173151882 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040692 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040692 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046394 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.046394 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003587 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.003587 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.042478 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.042478 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.042477 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.042477 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13172.111939 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13172.111939 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7923.494958 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 7923.494958 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13015.384615 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13015.384615 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 11376.401104 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 11376.401104 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 11376.385637 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 11376.385637 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 14 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1100252 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 221126 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4.666667 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 4.975679 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2817480 # number of writebacks -system.cpu.dcache.writebacks::total 2817480 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2540507 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2540507 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1996523 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1996523 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 65 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 65 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4537030 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4537030 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4537030 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4537030 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2298155 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2298155 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519861 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 519861 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 9 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 9 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2818016 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2818016 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2818025 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2818025 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32727255000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 32727255000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4791332496 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4791332496 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1174000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1174000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37518587496 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 37518587496 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37519761496 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 37519761496 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019327 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019327 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009585 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009585 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003228 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003228 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016275 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016275 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016275 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.016275 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14240.664794 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14240.664794 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9216.564612 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9216.564612 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 130444.444444 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 130444.444444 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13313.830545 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13313.830545 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13314.204628 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13314.204628 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 76537 # number of replacements -system.cpu.icache.tags.tagsinuse 465.899675 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 235023805 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 77049 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3050.316098 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 116553680500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 465.899675 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.909960 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.909960 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 263 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 14 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 470296624 # Number of tag accesses -system.cpu.icache.tags.data_accesses 470296624 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 235023805 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 235023805 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 235023805 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 235023805 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 235023805 # number of overall hits -system.cpu.icache.overall_hits::total 235023805 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 85967 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 85967 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 85967 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 85967 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 85967 # number of overall misses -system.cpu.icache.overall_misses::total 85967 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1954653197 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1954653197 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1954653197 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1954653197 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1954653197 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1954653197 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 235109772 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 235109772 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 235109772 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 235109772 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 235109772 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 235109772 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000366 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000366 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000366 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000366 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000366 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000366 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22737.250305 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22737.250305 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22737.250305 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22737.250305 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22737.250305 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22737.250305 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 201943 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 336 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 7203 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 28.035957 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 42 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 76537 # number of writebacks -system.cpu.icache.writebacks::total 76537 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8885 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 8885 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 8885 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 8885 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 8885 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 8885 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 77082 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 77082 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 77082 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 77082 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 77082 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 77082 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1551815800 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1551815800 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1551815800 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1551815800 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1551815800 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1551815800 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000328 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000328 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000328 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20132.012662 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20132.012662 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20132.012662 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20132.012662 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20132.012662 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20132.012662 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 8513754 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 8515198 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 454 # number of redundant prefetches already in prefetch queue -system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped -system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 744250 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 390446 # number of replacements -system.cpu.l2cache.tags.tagsinuse 15006.522104 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2698185 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 406039 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 6.645138 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14933.160754 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 73.361350 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.911448 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004478 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.915925 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 107 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15486 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 5 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 51 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 51 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 239 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 675 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5453 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6496 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2623 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.006531 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.945190 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 95374967 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 95374967 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 2350430 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2350430 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 520007 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 520007 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 516734 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 516734 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 66859 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 66859 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2131098 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 2131098 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 66859 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2647832 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2714691 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 66859 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2647832 # number of overall hits -system.cpu.l2cache.overall_hits::total 2714691 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 33 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 33 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 5281 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 5281 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10187 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 10187 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 164879 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 164879 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 10187 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 170160 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 180347 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 10187 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 170160 # number of overall misses -system.cpu.l2cache.overall_misses::total 180347 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 87000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 87000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 674041000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 674041000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1035576000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 1035576000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 15320195500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 15320195500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1035576000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 15994236500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 17029812500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1035576000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 15994236500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 17029812500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 2350430 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 2350430 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 520007 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 520007 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 33 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 33 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 522015 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 522015 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 77046 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 77046 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2295977 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 2295977 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 77046 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2817992 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2895038 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 77046 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2817992 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2895038 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.010117 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.010117 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.132220 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.132220 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.071812 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.071812 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.132220 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.060383 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.062295 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.132220 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.060383 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.062295 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 2636.363636 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 2636.363636 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127635.106987 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127635.106987 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 101656.621184 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 101656.621184 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92917.809424 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92917.809424 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 101656.621184 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93995.277974 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 94428.033180 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 101656.621184 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93995.277974 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 94428.033180 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 349 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 349 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.unused_prefetches 1991 # number of HardPF blocks evicted w/o reference -system.cpu.l2cache.writebacks::writebacks 291460 # number of writebacks -system.cpu.l2cache.writebacks::total 291460 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1597 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 1597 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 11 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4534 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4534 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 6131 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 6142 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 6131 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 6142 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 356126 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 356126 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 33 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 33 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3684 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 3684 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10176 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10176 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 160345 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 160345 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 10176 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 164029 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 174205 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 10176 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 164029 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 356126 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 530331 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 21400232213 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 21400232213 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 517000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 517000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 462922500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 462922500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 973097500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 973097500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 13944331500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 13944331500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 973097500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14407254000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15380351500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 973097500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14407254000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 21400232213 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 36780583713 # number of overall MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007057 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007057 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.132077 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.132077 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.069837 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.069837 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.132077 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058208 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.060174 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.132077 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058208 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.183186 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 60091.743408 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 60091.743408 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15666.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15666.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 125657.573290 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 125657.573290 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 95626.719733 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 95626.719733 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 86964.554554 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 86964.554554 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 95626.719733 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 87833.578209 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88288.806291 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 95626.719733 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 87833.578209 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 60091.743408 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69354.014216 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5789124 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2894045 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 26043 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 99823 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 99226 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 597 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 2373057 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2641890 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 543587 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 98986 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 403295 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 33 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 33 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 522015 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 522015 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 77082 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2295977 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 230663 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8453531 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8684194 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9829184 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360670272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 370499456 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 793778 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 18655808 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 3688848 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.034290 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.182859 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3562956 96.59% 96.59% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 125295 3.40% 99.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 597 0.02% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3688848 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5788579005 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1506 # Layer occupancy (ticks) -system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 115655928 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4227026456 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 821093 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 414041 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 426929 # Transaction distribution -system.membus.trans_dist::WritebackDirty 291460 # Transaction distribution -system.membus.trans_dist::CleanEvict 98986 # Transaction distribution -system.membus.trans_dist::UpgradeReq 36 # Transaction distribution -system.membus.trans_dist::ReadExReq 3681 # Transaction distribution -system.membus.trans_dist::ReadExResp 3681 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 426930 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1251703 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1251703 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46212480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 46212480 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 430647 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 430647 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 430647 # Request fanout histogram -system.membus.reqLayer0.occupancy 2213026745 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2279181090 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.0 # Layer utilization (%) +sim_seconds 0.235850 +sim_ticks 235850129000 +final_tick 235850129000 +sim_freq 1000000000000 +host_inst_rate 106785 +host_op_rate 115686 +host_tick_rate 49848699 +host_mem_usage 313808 +host_seconds 4731.32 +sim_insts 505234934 +sim_ops 547348155 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 235850129000 +system.physmem.bytes_read::cpu.inst 651264 +system.physmem.bytes_read::cpu.data 10497792 +system.physmem.bytes_read::cpu.l2cache.prefetcher 16410048 +system.physmem.bytes_read::total 27559104 +system.physmem.bytes_inst_read::cpu.inst 651264 +system.physmem.bytes_inst_read::total 651264 +system.physmem.bytes_written::writebacks 18653440 +system.physmem.bytes_written::total 18653440 +system.physmem.num_reads::cpu.inst 10176 +system.physmem.num_reads::cpu.data 164028 +system.physmem.num_reads::cpu.l2cache.prefetcher 256407 +system.physmem.num_reads::total 430611 +system.physmem.num_writes::writebacks 291460 +system.physmem.num_writes::total 291460 +system.physmem.bw_read::cpu.inst 2761347 +system.physmem.bw_read::cpu.data 44510436 +system.physmem.bw_read::cpu.l2cache.prefetcher 69578287 +system.physmem.bw_read::total 116850070 +system.physmem.bw_inst_read::cpu.inst 2761347 +system.physmem.bw_inst_read::total 2761347 +system.physmem.bw_write::writebacks 79090226 +system.physmem.bw_write::total 79090226 +system.physmem.bw_total::writebacks 79090226 +system.physmem.bw_total::cpu.inst 2761347 +system.physmem.bw_total::cpu.data 44510436 +system.physmem.bw_total::cpu.l2cache.prefetcher 69578287 +system.physmem.bw_total::total 195940296 +system.physmem.readReqs 430611 +system.physmem.writeReqs 291460 +system.physmem.readBursts 430611 +system.physmem.writeBursts 291460 +system.physmem.bytesReadDRAM 27396288 +system.physmem.bytesReadWrQ 162816 +system.physmem.bytesWritten 18651392 +system.physmem.bytesReadSys 27559104 +system.physmem.bytesWrittenSys 18653440 +system.physmem.servicedByWrQ 2544 +system.physmem.mergedWrBursts 9 +system.physmem.neitherReadNorWriteReqs 0 +system.physmem.perBankRdBursts::0 27102 +system.physmem.perBankRdBursts::1 26174 +system.physmem.perBankRdBursts::2 25664 +system.physmem.perBankRdBursts::3 33006 +system.physmem.perBankRdBursts::4 27996 +system.physmem.perBankRdBursts::5 29984 +system.physmem.perBankRdBursts::6 25487 +system.physmem.perBankRdBursts::7 24586 +system.physmem.perBankRdBursts::8 25526 +system.physmem.perBankRdBursts::9 25681 +system.physmem.perBankRdBursts::10 25862 +system.physmem.perBankRdBursts::11 26092 +system.physmem.perBankRdBursts::12 27614 +system.physmem.perBankRdBursts::13 26106 +system.physmem.perBankRdBursts::14 25123 +system.physmem.perBankRdBursts::15 26064 +system.physmem.perBankWrBursts::0 18530 +system.physmem.perBankWrBursts::1 18172 +system.physmem.perBankWrBursts::2 17960 +system.physmem.perBankWrBursts::3 17946 +system.physmem.perBankWrBursts::4 18535 +system.physmem.perBankWrBursts::5 18092 +system.physmem.perBankWrBursts::6 17937 +system.physmem.perBankWrBursts::7 17864 +system.physmem.perBankWrBursts::8 17881 +system.physmem.perBankWrBursts::9 17814 +system.physmem.perBankWrBursts::10 18253 +system.physmem.perBankWrBursts::11 18685 +system.physmem.perBankWrBursts::12 18794 +system.physmem.perBankWrBursts::13 18180 +system.physmem.perBankWrBursts::14 18427 +system.physmem.perBankWrBursts::15 18358 +system.physmem.numRdRetry 0 +system.physmem.numWrRetry 0 +system.physmem.totGap 235850076500 +system.physmem.readPktSize::0 0 +system.physmem.readPktSize::1 0 +system.physmem.readPktSize::2 0 +system.physmem.readPktSize::3 0 +system.physmem.readPktSize::4 0 +system.physmem.readPktSize::5 0 +system.physmem.readPktSize::6 430611 +system.physmem.writePktSize::0 0 +system.physmem.writePktSize::1 0 +system.physmem.writePktSize::2 0 +system.physmem.writePktSize::3 0 +system.physmem.writePktSize::4 0 +system.physmem.writePktSize::5 0 +system.physmem.writePktSize::6 291460 +system.physmem.rdQLenPdf::0 318665 +system.physmem.rdQLenPdf::1 60579 +system.physmem.rdQLenPdf::2 13349 +system.physmem.rdQLenPdf::3 9026 +system.physmem.rdQLenPdf::4 7328 +system.physmem.rdQLenPdf::5 6151 +system.physmem.rdQLenPdf::6 5231 +system.physmem.rdQLenPdf::7 4311 +system.physmem.rdQLenPdf::8 3288 +system.physmem.rdQLenPdf::9 74 +system.physmem.rdQLenPdf::10 37 +system.physmem.rdQLenPdf::11 14 +system.physmem.rdQLenPdf::12 8 +system.physmem.rdQLenPdf::13 3 +system.physmem.rdQLenPdf::14 2 +system.physmem.rdQLenPdf::15 1 +system.physmem.rdQLenPdf::16 0 +system.physmem.rdQLenPdf::17 0 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+system.cpu.toL2Bus.snoop_fanout::stdev 0.182859 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 3562956 96.59% 96.59% +system.cpu.toL2Bus.snoop_fanout::1 125295 3.40% 99.98% +system.cpu.toL2Bus.snoop_fanout::2 597 0.02% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 2 +system.cpu.toL2Bus.snoop_fanout::total 3688848 +system.cpu.toL2Bus.reqLayer0.occupancy 5788579005 +system.cpu.toL2Bus.reqLayer0.utilization 2.5 +system.cpu.toL2Bus.snoopLayer0.occupancy 1506 +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 +system.cpu.toL2Bus.respLayer0.occupancy 115655928 +system.cpu.toL2Bus.respLayer0.utilization 0.0 +system.cpu.toL2Bus.respLayer1.occupancy 4227026456 +system.cpu.toL2Bus.respLayer1.utilization 1.8 +system.membus.snoop_filter.tot_requests 821093 +system.membus.snoop_filter.hit_single_requests 414041 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 235850129000 +system.membus.trans_dist::ReadResp 426929 +system.membus.trans_dist::WritebackDirty 291460 +system.membus.trans_dist::CleanEvict 98986 +system.membus.trans_dist::UpgradeReq 36 +system.membus.trans_dist::ReadExReq 3681 +system.membus.trans_dist::ReadExResp 3681 +system.membus.trans_dist::ReadSharedReq 426930 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1251703 +system.membus.pkt_count::total 1251703 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46212480 +system.membus.pkt_size::total 46212480 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 430647 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 430647 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 430647 +system.membus.reqLayer0.occupancy 2213026745 +system.membus.reqLayer0.utilization 0.9 +system.membus.respLayer1.occupancy 2279181090 +system.membus.respLayer1.utilization 1.0 ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini index 719526a91..bd579b4cb 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini @@ -90,6 +90,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -165,8 +166,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -177,8 +176,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -239,7 +236,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=parser 2.1.dict -batch cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic drivers= @@ -248,14 +245,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/parser +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/parser gid=100 -input=/arm/projectscratch/randd/systems/dist/cpu2000/data/parser/mdred/input/parser.in +input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/parser/mdred/input/parser.in kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=114600000000 system=system uid=100 @@ -279,6 +277,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -290,7 +289,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -298,6 +297,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -306,6 +312,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -313,7 +320,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr index aadc3d011..094173d40 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr @@ -1,2 +1,5 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout index 6f63d3022..a36e35467 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-ato gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:38:22 -gem5 executing on e108600-lin, pid 23082 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/arm/linux/simple-atomic +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 17:56:13 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54223 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/20.parser/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Reading the dictionary files: ************************************************* @@ -20,12 +19,10 @@ Welcome to the Link Parser -- Version 2.1 Processing sentences in batch mode -info: Increasing stack size by one page. Echoing of input sentence turned on. * as had expected the party to be a success , it was a success * do you know where John 's * he said that , finding that it was impossible to get work as a waiter , he would work as a janitor -info: Increasing stack size by one page. * how fast the program is it * I am wondering whether to invite to the party * I gave him for his birthday it @@ -70,4 +67,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 279360903000 because target called exit() +Exiting @ tick 279360903000 because exiting with last active thread context diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt index f22db7f03..30c0da648 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -1,262 +1,262 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.279361 # Number of seconds simulated -sim_ticks 279360903000 # Number of ticks simulated -final_tick 279360903000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2213544 # Simulator instruction rate (inst/s) -host_op_rate 2397561 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1220693561 # Simulator tick rate (ticks/s) -host_mem_usage 263256 # Number of bytes of host memory used -host_seconds 228.85 # Real time elapsed on the host -sim_insts 506578818 # Number of instructions simulated -sim_ops 548692039 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 2066434344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 422848347 # Number of bytes read from this memory -system.physmem.bytes_read::total 2489282691 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 2066434344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 2066434344 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 216066596 # Number of bytes written to this memory -system.physmem.bytes_written::total 216066596 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 516608586 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 115590054 # Number of read requests responded to by this memory -system.physmem.num_reads::total 632198640 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 55727590 # Number of write requests responded to by this memory -system.physmem.num_writes::total 55727590 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7397006245 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1513627506 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8910633751 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7397006245 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7397006245 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 773431764 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 773431764 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7397006245 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2287059270 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9684065515 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 548 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 279360903000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 558721807 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 506578818 # Number of instructions committed -system.cpu.committedOps 548692039 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 448447005 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses -system.cpu.num_func_calls 19311615 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 90670594 # number of instructions that are conditional controls -system.cpu.num_int_insts 448447005 # number of integer instructions -system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 749023721 # number of times the integer registers were read -system.cpu.num_int_register_writes 289993515 # number of times the integer registers were written -system.cpu.num_fp_register_reads 16 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 1634221880 # number of times the CC registers were read -system.cpu.num_cc_register_writes 344062197 # number of times the CC registers were written -system.cpu.num_mem_refs 172743505 # number of memory refs -system.cpu.num_load_insts 115883283 # Number of load instructions -system.cpu.num_store_insts 56860222 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 558721806.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 121552863 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 375609862 68.46% 68.46% # Class of executed instruction -system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::MemRead 115883283 21.12% 89.64% # Class of executed instruction -system.cpu.op_class::MemWrite 56860206 10.36% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 16 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 548692589 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 630707528 # Transaction distribution -system.membus.trans_dist::ReadResp 632196069 # Transaction distribution -system.membus.trans_dist::WriteReq 54239049 # Transaction distribution -system.membus.trans_dist::WriteResp 54239049 # Transaction distribution -system.membus.trans_dist::SoftPFReq 2571 # Transaction distribution -system.membus.trans_dist::SoftPFResp 2571 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 1488541 # Transaction distribution -system.membus.trans_dist::StoreCondReq 1488541 # Transaction distribution -system.membus.trans_dist::StoreCondResp 1488541 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1033217172 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 342635288 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1375852460 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2066434344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638914943 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 2705349287 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 687926230 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 687926230 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 687926230 # Request fanout histogram +sim_seconds 0.279361 +sim_ticks 279360903000 +final_tick 279360903000 +sim_freq 1000000000000 +host_inst_rate 937755 +host_op_rate 1015713 +host_tick_rate 517139598 +host_mem_usage 274756 +host_seconds 540.20 +sim_insts 506578818 +sim_ops 548692039 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 279360903000 +system.physmem.bytes_read::cpu.inst 2066434344 +system.physmem.bytes_read::cpu.data 422848347 +system.physmem.bytes_read::total 2489282691 +system.physmem.bytes_inst_read::cpu.inst 2066434344 +system.physmem.bytes_inst_read::total 2066434344 +system.physmem.bytes_written::cpu.data 216066596 +system.physmem.bytes_written::total 216066596 +system.physmem.num_reads::cpu.inst 516608586 +system.physmem.num_reads::cpu.data 115590054 +system.physmem.num_reads::total 632198640 +system.physmem.num_writes::cpu.data 55727590 +system.physmem.num_writes::total 55727590 +system.physmem.bw_read::cpu.inst 7397006245 +system.physmem.bw_read::cpu.data 1513627506 +system.physmem.bw_read::total 8910633751 +system.physmem.bw_inst_read::cpu.inst 7397006245 +system.physmem.bw_inst_read::total 7397006245 +system.physmem.bw_write::cpu.data 773431764 +system.physmem.bw_write::total 773431764 +system.physmem.bw_total::cpu.inst 7397006245 +system.physmem.bw_total::cpu.data 2287059270 +system.physmem.bw_total::total 9684065515 +system.pwrStateResidencyTicks::UNDEFINED 279360903000 +system.cpu_clk_domain.clock 500 +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.hits 0 +system.cpu.dstage2_mmu.stage2_tlb.misses 0 +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 +system.cpu.dtb.walker.walks 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dtb.walker.walkRequestOrigin::total 0 +system.cpu.dtb.inst_hits 0 +system.cpu.dtb.inst_misses 0 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.flush_tlb 0 +system.cpu.dtb.flush_tlb_mva 0 +system.cpu.dtb.flush_tlb_mva_asid 0 +system.cpu.dtb.flush_tlb_asid 0 +system.cpu.dtb.flush_entries 0 +system.cpu.dtb.align_faults 0 +system.cpu.dtb.prefetch_faults 0 +system.cpu.dtb.domain_faults 0 +system.cpu.dtb.perms_faults 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.inst_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.hits 0 +system.cpu.istage2_mmu.stage2_tlb.misses 0 +system.cpu.istage2_mmu.stage2_tlb.accesses 0 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 +system.cpu.itb.walker.walks 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.itb.walker.walkRequestOrigin::total 0 +system.cpu.itb.inst_hits 0 +system.cpu.itb.inst_misses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.flush_tlb 0 +system.cpu.itb.flush_tlb_mva 0 +system.cpu.itb.flush_tlb_mva_asid 0 +system.cpu.itb.flush_tlb_asid 0 +system.cpu.itb.flush_entries 0 +system.cpu.itb.align_faults 0 +system.cpu.itb.prefetch_faults 0 +system.cpu.itb.domain_faults 0 +system.cpu.itb.perms_faults 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.inst_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 548 +system.cpu.pwrStateResidencyTicks::ON 279360903000 +system.cpu.numCycles 558721807 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 506578818 +system.cpu.committedOps 548692039 +system.cpu.num_int_alu_accesses 448447005 +system.cpu.num_fp_alu_accesses 16 +system.cpu.num_func_calls 19311615 +system.cpu.num_conditional_control_insts 90670594 +system.cpu.num_int_insts 448447005 +system.cpu.num_fp_insts 16 +system.cpu.num_int_register_reads 749023721 +system.cpu.num_int_register_writes 289993515 +system.cpu.num_fp_register_reads 16 +system.cpu.num_fp_register_writes 0 +system.cpu.num_cc_register_reads 1634221880 +system.cpu.num_cc_register_writes 344062197 +system.cpu.num_mem_refs 172743505 +system.cpu.num_load_insts 115883283 +system.cpu.num_store_insts 56860222 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 558721807 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 121552863 +system.cpu.op_class::No_OpClass 0 0.00% 0.00% +system.cpu.op_class::IntAlu 375609862 68.46% 68.46% +system.cpu.op_class::IntMult 339219 0.06% 68.52% +system.cpu.op_class::IntDiv 0 0.00% 68.52% +system.cpu.op_class::FloatAdd 0 0.00% 68.52% +system.cpu.op_class::FloatCmp 0 0.00% 68.52% +system.cpu.op_class::FloatCvt 0 0.00% 68.52% +system.cpu.op_class::FloatMult 0 0.00% 68.52% +system.cpu.op_class::FloatMultAcc 0 0.00% 68.52% +system.cpu.op_class::FloatDiv 0 0.00% 68.52% +system.cpu.op_class::FloatMisc 0 0.00% 68.52% +system.cpu.op_class::FloatSqrt 0 0.00% 68.52% +system.cpu.op_class::SimdAdd 0 0.00% 68.52% +system.cpu.op_class::SimdAddAcc 0 0.00% 68.52% +system.cpu.op_class::SimdAlu 0 0.00% 68.52% +system.cpu.op_class::SimdCmp 0 0.00% 68.52% +system.cpu.op_class::SimdCvt 0 0.00% 68.52% +system.cpu.op_class::SimdMisc 0 0.00% 68.52% +system.cpu.op_class::SimdMult 0 0.00% 68.52% +system.cpu.op_class::SimdMultAcc 0 0.00% 68.52% +system.cpu.op_class::SimdShift 0 0.00% 68.52% +system.cpu.op_class::SimdShiftAcc 0 0.00% 68.52% +system.cpu.op_class::SimdSqrt 0 0.00% 68.52% +system.cpu.op_class::SimdFloatAdd 0 0.00% 68.52% +system.cpu.op_class::SimdFloatAlu 0 0.00% 68.52% +system.cpu.op_class::SimdFloatCmp 0 0.00% 68.52% +system.cpu.op_class::SimdFloatCvt 0 0.00% 68.52% +system.cpu.op_class::SimdFloatDiv 0 0.00% 68.52% +system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% +system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% +system.cpu.op_class::MemRead 115883283 21.12% 89.64% +system.cpu.op_class::MemWrite 56860206 10.36% 100.00% +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 16 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 548692589 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 279360903000 +system.membus.trans_dist::ReadReq 630707528 +system.membus.trans_dist::ReadResp 632196069 +system.membus.trans_dist::WriteReq 54239049 +system.membus.trans_dist::WriteResp 54239049 +system.membus.trans_dist::SoftPFReq 2571 +system.membus.trans_dist::SoftPFResp 2571 +system.membus.trans_dist::LoadLockedReq 1488541 +system.membus.trans_dist::StoreCondReq 1488541 +system.membus.trans_dist::StoreCondResp 1488541 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1033217172 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 342635288 +system.membus.pkt_count::total 1375852460 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2066434344 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638914943 +system.membus.pkt_size::total 2705349287 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 687926230 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 687926230 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 687926230 ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini index cc618b726..cd5fa2511 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini @@ -87,6 +87,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -96,14 +97,14 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -117,6 +118,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -129,15 +131,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dstage2_mmu] type=ArmStage2MMU @@ -193,14 +196,14 @@ port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -214,6 +217,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -226,15 +230,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=ArmInterrupts @@ -253,8 +258,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -265,8 +268,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -325,14 +326,14 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -346,6 +347,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -358,15 +360,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -402,7 +405,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=parser 2.1.dict -batch cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing drivers= @@ -411,14 +414,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/parser +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/parser gid=100 -input=/arm/projectscratch/randd/systems/dist/cpu2000/data/parser/mdred/input/parser.in +input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/parser/mdred/input/parser.in kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=114600000000 system=system uid=100 @@ -442,6 +446,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -453,7 +458,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -461,6 +466,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -469,6 +481,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -476,7 +489,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr index aadc3d011..094173d40 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr @@ -1,2 +1,5 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout index 1889b3430..e4542abd6 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:38:21 -gem5 executing on e108600-lin, pid 23071 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/arm/linux/simple-timing +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 18:35:18 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 61430 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/20.parser/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Reading the dictionary files: ************************************************* @@ -20,12 +19,10 @@ Welcome to the Link Parser -- Version 2.1 Processing sentences in batch mode -info: Increasing stack size by one page. Echoing of input sentence turned on. * as had expected the party to be a success , it was a success * do you know where John 's * he said that , finding that it was impossible to get work as a waiter , he would work as a janitor -info: Increasing stack size by one page. * how fast the program is it * I am wondering whether to invite to the party * I gave him for his birthday it @@ -70,4 +67,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 708539449500 because target called exit() +Exiting @ tick 708700329500 because exiting with last active thread context diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index 072f29102..78d65a20d 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -1,685 +1,685 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.708700 # Number of seconds simulated -sim_ticks 708700329500 # Number of ticks simulated -final_tick 708700329500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1580290 # Simulator instruction rate (inst/s) -host_op_rate 1711383 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2217795996 # Simulator tick rate (ticks/s) -host_mem_usage 275040 # Number of bytes of host memory used -host_seconds 319.55 # Real time elapsed on the host -sim_insts 504984064 # Number of instructions simulated -sim_ops 546875315 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 147392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8988096 # Number of bytes read from this memory -system.physmem.bytes_read::total 9135488 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 147392 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 147392 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6185472 # Number of bytes written to this memory -system.physmem.bytes_written::total 6185472 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2303 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140439 # Number of read requests responded to by this memory -system.physmem.num_reads::total 142742 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 96648 # Number of write requests responded to by this memory -system.physmem.num_writes::total 96648 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 207975 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12682506 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12890481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 207975 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 207975 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 8727909 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8727909 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 8727909 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 207975 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12682506 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 21618390 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 548 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 708700329500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1417400659 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 504984064 # Number of instructions committed -system.cpu.committedOps 546875315 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 448447005 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses -system.cpu.num_func_calls 19311615 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 90670594 # number of instructions that are conditional controls -system.cpu.num_int_insts 448447005 # number of integer instructions -system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 748339627 # number of times the integer registers were read -system.cpu.num_int_register_writes 289993515 # number of times the integer registers were written -system.cpu.num_fp_register_reads 16 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 1984285070 # number of times the CC registers were read -system.cpu.num_cc_register_writes 344062197 # number of times the CC registers were written -system.cpu.num_mem_refs 172743505 # number of memory refs -system.cpu.num_load_insts 115883283 # Number of load instructions -system.cpu.num_store_insts 56860222 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1417400658.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 121552863 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 375609862 68.46% 68.46% # Class of executed instruction -system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::MemRead 115883283 21.12% 89.64% # Class of executed instruction -system.cpu.op_class::MemWrite 56860206 10.36% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 16 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 548692589 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1136276 # number of replacements -system.cpu.dcache.tags.tagsinuse 4065.253828 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 170177272 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1140372 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 149.229613 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 11754931500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4065.253828 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.992494 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.992494 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 343 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3546 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 343775660 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 343775660 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 113315079 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 113315079 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 53882541 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 53882541 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2570 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2570 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 167197620 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 167197620 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 167200190 # number of overall hits -system.cpu.dcache.overall_hits::total 167200190 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 783863 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 783863 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 356508 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 356508 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1140371 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1140371 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1140372 # number of overall misses -system.cpu.dcache.overall_misses::total 1140372 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12176129500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12176129500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9680337500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9680337500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 21856467000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 21856467000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 21856467000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 21856467000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 114098942 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 114098942 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2571 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2571 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168337991 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168337991 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168340562 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168340562 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006870 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.006870 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006573 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006573 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000389 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.000389 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.006774 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.006774 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.006774 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.006774 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15533.491822 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15533.491822 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27153.212551 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27153.212551 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19166.102084 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19166.102084 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19166.085277 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19166.085277 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 1065429 # number of writebacks -system.cpu.dcache.writebacks::total 1065429 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 783863 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 783863 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356508 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 356508 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1140371 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1140371 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1140372 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1140372 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11392266500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11392266500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9323829500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9323829500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 62000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 62000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20716096000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 20716096000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20716158000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 20716158000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006870 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006870 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006573 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006573 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000389 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000389 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006774 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006774 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006774 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006774 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14533.491822 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14533.491822 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26153.212551 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26153.212551 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18166.102084 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18166.102084 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18166.140523 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18166.140523 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 9788 # number of replacements -system.cpu.icache.tags.tagsinuse 983.167360 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 516597066 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 44839.602986 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 983.167360 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.480062 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.480062 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 256 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1402 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.846191 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1033228695 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1033228695 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 516597066 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 516597066 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 516597066 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 516597066 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 516597066 # number of overall hits -system.cpu.icache.overall_hits::total 516597066 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11521 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11521 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11521 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses -system.cpu.icache.overall_misses::total 11521 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 265513000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 265513000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 265513000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 265513000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 265513000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 265513000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 516608587 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 516608587 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 516608587 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 516608587 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 516608587 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 516608587 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23046.002951 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23046.002951 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23046.002951 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23046.002951 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23046.002951 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23046.002951 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 9788 # number of writebacks -system.cpu.icache.writebacks::total 9788 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11521 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 11521 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 11521 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 253992000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 253992000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 253992000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 253992000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 253992000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 253992000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22046.002951 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22046.002951 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22046.002951 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22046.002951 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22046.002951 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 22046.002951 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 110813 # number of replacements -system.cpu.l2cache.tags.tagsinuse 28700.010798 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2150809 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 143581 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 14.979761 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 210357436000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 80.467975 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 239.840136 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28379.702687 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.002456 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007319 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.866080 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.875855 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 111 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 661 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31936 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 18498717 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 18498717 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 1065429 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 1065429 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 9751 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 9751 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 255675 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 255675 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 9218 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 9218 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 744258 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 744258 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 9218 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 999933 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1009151 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 9218 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 999933 # number of overall hits -system.cpu.l2cache.overall_hits::total 1009151 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 100833 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 100833 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2303 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2303 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 39606 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 39606 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2303 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 140439 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 142742 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2303 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 140439 # number of overall misses -system.cpu.l2cache.overall_misses::total 142742 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6104447000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6104447000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 139534000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 139534000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2398500500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 2398500500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 139534000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8502947500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8642481500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 139534000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8502947500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8642481500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 1065429 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 1065429 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 9751 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 9751 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 356508 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 356508 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 11521 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 11521 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 783864 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 783864 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 11521 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1140372 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1151893 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 11521 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1140372 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1151893 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282835 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.282835 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.199896 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.199896 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050527 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050527 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.199896 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.123152 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.123919 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.199896 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.123152 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.123919 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60540.170381 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60540.170381 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60587.928789 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60587.928789 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60559.018836 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60559.018836 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60587.928789 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60545.485941 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60546.170714 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60587.928789 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60545.485941 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60546.170714 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 96648 # number of writebacks -system.cpu.l2cache.writebacks::total 96648 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 2 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100833 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 100833 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2303 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2303 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 39606 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 39606 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2303 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 140439 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 142742 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2303 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 140439 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 142742 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5096117000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5096117000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 116504000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 116504000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2002440500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2002440500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 116504000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7098557500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 7215061500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 116504000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7098557500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 7215061500 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282835 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282835 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.199896 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050527 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050527 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123152 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.123919 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123152 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.123919 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50540.170381 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50540.170381 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50587.928789 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50587.928789 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50559.018836 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50559.018836 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50587.928789 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50545.485941 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50546.170714 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50587.928789 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50545.485941 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50546.170714 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 2297957 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 1146116 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3565 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2153 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2152 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 795385 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 1162077 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 9788 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 85012 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 356508 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 356508 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 11521 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 783864 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32830 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3417020 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3449850 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1363776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141171264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 142535040 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 110813 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 6185472 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1262706 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.004570 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.067461 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1256936 99.54% 99.54% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5769 0.46% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1262706 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2224195500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1710558000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 251405 # Total number of requests made to the snoop filter. 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-system.membus.trans_dist::ReadExReq 100833 # Transaction distribution -system.membus.trans_dist::ReadExResp 100833 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 41909 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394146 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 394146 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15320960 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15320960 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 142743 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram 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96648 +system.membus.trans_dist::CleanEvict 12014 +system.membus.trans_dist::ReadExReq 100833 +system.membus.trans_dist::ReadExResp 100833 +system.membus.trans_dist::ReadSharedReq 41909 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394146 +system.membus.pkt_count::total 394146 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15320960 +system.membus.pkt_size::total 15320960 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 142743 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 142743 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 142743 +system.membus.reqLayer0.occupancy 644372828 +system.membus.reqLayer0.utilization 0.1 +system.membus.respLayer1.occupancy 713710000 +system.membus.respLayer1.utilization 0.1 ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini index 246d6b579..a38a74511 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=timing @@ -65,7 +66,7 @@ SSITSize=1024 activity=0 backComSize=5 branchPred=system.cpu.branchPred -cachePorts=200 +cacheStorePorts=200 checker=Null clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 @@ -139,6 +140,7 @@ socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -183,10 +185,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -200,6 +202,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -212,15 +215,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dtb] type=X86TLB @@ -313,10 +317,10 @@ pipelined=true [system.cpu.fuPool.FUList3] type=FUDesc -children=opList0 opList1 opList2 +children=opList0 opList1 opList2 opList3 opList4 count=2 eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 [system.cpu.fuPool.FUList3.opList0] type=OpDesc @@ -328,11 +332,25 @@ pipelined=true [system.cpu.fuPool.FUList3.opList1] type=OpDesc eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 opClass=FloatDiv opLat=12 pipelined=false -[system.cpu.fuPool.FUList3.opList2] +[system.cpu.fuPool.FUList3.opList4] type=OpDesc eventq_index=0 opClass=FloatSqrt @@ -341,18 +359,25 @@ pipelined=false [system.cpu.fuPool.FUList4] type=FUDesc -children=opList +children=opList0 opList1 count=0 eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList +opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 -[system.cpu.fuPool.FUList4.opList] +[system.cpu.fuPool.FUList4.opList0] type=OpDesc eventq_index=0 opClass=MemRead opLat=1 pipelined=true +[system.cpu.fuPool.FUList4.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList5] type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 @@ -502,24 +527,31 @@ pipelined=true [system.cpu.fuPool.FUList6] type=FUDesc -children=opList +children=opList0 opList1 count=0 eventq_index=0 -opList=system.cpu.fuPool.FUList6.opList +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 -[system.cpu.fuPool.FUList6.opList] +[system.cpu.fuPool.FUList6.opList0] type=OpDesc eventq_index=0 opClass=MemWrite opLat=1 pipelined=true +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList7] type=FUDesc -children=opList0 opList1 +children=opList0 opList1 opList2 opList3 count=4 eventq_index=0 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 [system.cpu.fuPool.FUList7.opList0] type=OpDesc @@ -535,6 +567,20 @@ opClass=MemWrite opLat=1 pipelined=true +[system.cpu.fuPool.FUList7.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList8] type=FUDesc children=opList @@ -556,10 +602,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -573,6 +619,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -585,15 +632,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=X86LocalApic @@ -643,10 +691,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -660,6 +708,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -672,15 +721,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -716,7 +766,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=parser 2.1.dict -batch cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing drivers= @@ -725,14 +775,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/parser +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 -input=/arm/projectscratch/randd/systems/dist/cpu2000/data/parser/mdred/input/parser.in +input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/parser/mdred/input/parser.in kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=114600000000 system=system uid=100 diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr index bbcd9d751..630e657e6 100755 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr @@ -1,3 +1,18 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout index 94b6c45b2..e7ed8f409 100755 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout @@ -3,17 +3,13 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 21:09:23 -gem5 executing on e108600-lin, pid 17649 -command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/x86/linux/o3-timing +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:22 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87198 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. Reading the dictionary files: ************************************************* 58924 words stored in 3784810 bytes @@ -72,4 +68,4 @@ Echoing of input sentence turned on. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 487015166000 because target called exit() +Exiting @ tick 487050729500 because exiting with last active thread context diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 699c09a91..72edf9459 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,1092 +1,1092 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.487051 # Number of seconds simulated -sim_ticks 487050729500 # Number of ticks simulated -final_tick 487050729500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 151835 # Simulator instruction rate (inst/s) -host_op_rate 280970 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 89437473 # Simulator tick rate (ticks/s) -host_mem_usage 318556 # Number of bytes of host memory used -host_seconds 5445.71 # Real time elapsed on the host -sim_insts 826847303 # Number of instructions simulated -sim_ops 1530082520 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 156352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24658560 # Number of bytes read from this memory -system.physmem.bytes_read::total 24814912 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 156352 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 156352 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18911424 # Number of bytes written to this memory -system.physmem.bytes_written::total 18911424 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2443 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 385290 # Number of read requests responded to by this memory -system.physmem.num_reads::total 387733 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 295491 # Number of write requests responded to by this memory -system.physmem.num_writes::total 295491 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 321018 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 50628320 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50949338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 321018 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 321018 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 38828448 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 38828448 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 38828448 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 321018 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 50628320 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 89777786 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 387733 # Number of read requests accepted -system.physmem.writeReqs 295491 # Number of write requests accepted -system.physmem.readBursts 387733 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 295491 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24795072 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19840 # Total number of bytes read from write queue -system.physmem.bytesWritten 18909504 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24814912 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18911424 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 310 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24612 # Per bank write bursts -system.physmem.perBankRdBursts::1 26389 # Per bank write bursts -system.physmem.perBankRdBursts::2 24828 # Per bank write bursts -system.physmem.perBankRdBursts::3 24571 # Per bank write bursts -system.physmem.perBankRdBursts::4 23534 # Per bank write bursts -system.physmem.perBankRdBursts::5 23661 # Per bank write bursts -system.physmem.perBankRdBursts::6 24754 # Per bank write bursts -system.physmem.perBankRdBursts::7 24509 # Per bank write bursts -system.physmem.perBankRdBursts::8 23888 # Per bank write bursts -system.physmem.perBankRdBursts::9 23557 # Per bank write bursts -system.physmem.perBankRdBursts::10 24834 # Per bank write bursts -system.physmem.perBankRdBursts::11 24002 # Per bank write bursts -system.physmem.perBankRdBursts::12 23243 # Per bank write bursts -system.physmem.perBankRdBursts::13 22894 # Per bank write bursts -system.physmem.perBankRdBursts::14 23905 # Per bank write bursts -system.physmem.perBankRdBursts::15 24242 # Per bank write bursts -system.physmem.perBankWrBursts::0 18972 # Per bank write bursts -system.physmem.perBankWrBursts::1 19954 # Per bank write bursts -system.physmem.perBankWrBursts::2 19038 # Per bank write bursts -system.physmem.perBankWrBursts::3 19006 # Per bank write bursts -system.physmem.perBankWrBursts::4 18208 # Per bank write bursts -system.physmem.perBankWrBursts::5 18444 # Per bank write bursts -system.physmem.perBankWrBursts::6 19174 # Per bank write bursts -system.physmem.perBankWrBursts::7 19116 # Per bank write bursts -system.physmem.perBankWrBursts::8 18744 # Per bank write bursts -system.physmem.perBankWrBursts::9 17955 # Per bank write bursts -system.physmem.perBankWrBursts::10 18923 # Per bank write bursts -system.physmem.perBankWrBursts::11 17774 # Per bank write bursts -system.physmem.perBankWrBursts::12 17399 # Per bank write bursts -system.physmem.perBankWrBursts::13 16985 # Per bank write bursts -system.physmem.perBankWrBursts::14 17804 # Per bank write bursts -system.physmem.perBankWrBursts::15 17965 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 487050613500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 387733 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 295491 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 381263 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 5754 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 361 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 34 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6088 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 17482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17661 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17686 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17712 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 146416 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 298.484100 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 176.719176 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 324.748192 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 52816 36.07% 36.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 41066 28.05% 64.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13865 9.47% 73.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7498 5.12% 78.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4985 3.40% 82.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3806 2.60% 84.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2894 1.98% 86.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2818 1.92% 88.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16668 11.38% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 146416 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17678 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.914866 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 18.161180 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 216.039339 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17672 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17678 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17678 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.713486 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.686282 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.965426 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 11315 64.01% 64.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 269 1.52% 65.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 5957 33.70% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 123 0.70% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 10 0.06% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 3 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17678 # Writes before turning the bus around for reads -system.physmem.totQLat 9794922250 # Total ticks spent queuing -system.physmem.totMemAccLat 17059103500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1937115000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25282.24 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44032.24 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 50.91 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 38.82 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 50.95 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 38.83 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.70 # Data bus utilization in percentage -system.physmem.busUtilRead 0.40 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.30 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.96 # Average write queue length when enqueuing -system.physmem.readRowHits 316322 # Number of row buffer hits during reads -system.physmem.writeRowHits 220133 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.65 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.50 # Row buffer hit rate for writes -system.physmem.avgGap 712871.05 # Average gap between requests -system.physmem.pageHitRate 78.55 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 538191780 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 286032945 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1405566120 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 792980640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 13571251200.000004 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 8851881120 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 742850400 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 36305173020 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 16998972000 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 84070895340 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 163568832135 # Total energy per rank (pJ) -system.physmem_0.averagePower 335.835307 # Core power per rank (mW) -system.physmem_0.totalIdleTime 465691902250 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 1184996500 # Time in different power states -system.physmem_0.memoryStateTime::REF 5763492000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 341808238000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 44268234250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 14409717250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 79616051500 # Time in different power states -system.physmem_1.actEnergy 507311280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 269615775 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1360634100 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 749325780 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 13094905200.000004 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 8819547870 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 717418080 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 34208424030 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 16648938720 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 85396744800 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 161777173725 # Total energy per rank (pJ) -system.physmem_1.averagePower 332.156722 # Core power per rank (mW) -system.physmem_1.totalIdleTime 465831856000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 1145526000 # Time in different power states -system.physmem_1.memoryStateTime::REF 5561926000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 347456670000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 43356567250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14511269750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 75018770500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 299198029 # Number of BP lookups -system.cpu.branchPred.condPredicted 299198029 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 24258277 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 226066805 # Number of BTB lookups -system.cpu.branchPred.BTBHits 0 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 40193400 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 4437789 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 226066805 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 118144411 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 107922394 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 11883156 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 551 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 487050729500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 974101460 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 230169557 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1594277830 # Number of instructions fetch has processed -system.cpu.fetch.Branches 299198029 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 158337811 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 718471067 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 49469999 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 2698 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 34945 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 480096 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 4714 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 69 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 216546560 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6526632 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 8 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 973898145 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.063667 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.497102 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 481357803 49.43% 49.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 36544666 3.75% 53.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 36285723 3.73% 56.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 32866211 3.37% 60.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 28367371 2.91% 63.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 29577354 3.04% 66.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 39843150 4.09% 70.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 36876934 3.79% 74.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 252178933 25.89% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 973898145 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.307153 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.636665 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 166490369 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 388298779 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 313723542 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 80650456 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 24734999 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2751923456 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 24734999 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 202899221 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 199700520 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14210 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 351959746 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 194589449 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2631585273 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 503822 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 119585114 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 21729790 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 44646970 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2710512651 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6600728549 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4213051781 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1976674 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1616961572 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1093551079 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 884 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 794 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 367177164 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 608809294 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 243550763 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 252688912 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 75518257 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2418516015 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 104540 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1999668107 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3656750 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 888538035 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1505526254 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 103988 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 973898145 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.053262 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.107501 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 345655298 35.49% 35.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 135232191 13.89% 49.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 129689064 13.32% 62.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 119012847 12.22% 74.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 97852872 10.05% 84.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 66913699 6.87% 91.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 45825912 4.71% 96.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 22646304 2.33% 98.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 11069958 1.14% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 973898145 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11137608 43.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11929198 46.06% 89.06% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2740827 10.58% 99.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 92541 0.36% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2900375 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1333719780 66.70% 66.84% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 357536 0.02% 66.86% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 4798411 0.24% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 4 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 471767183 23.59% 90.69% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 185670018 9.29% 99.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 6 0.00% 99.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 454793 0.02% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1999668107 # Type of FU issued -system.cpu.iq.rate 2.052833 # Inst issue rate -system.cpu.iq.fu_busy_cnt 25900174 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012952 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5001578236 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3304560217 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1922724831 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1213047 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 3212370 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 280288 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2022120560 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 547346 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 180407023 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 224726218 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 356451 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 693943 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 94392568 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 33314 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 814 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 24734999 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 149663879 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6607902 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2418620555 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1417513 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 608809531 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 243550763 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 36150 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1478128 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4302509 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 693943 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8551096 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 21778410 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 30329506 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1944942401 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 457167604 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 54725706 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 635670117 # number of memory reference insts executed -system.cpu.iew.exec_branches 185387955 # Number of branches executed -system.cpu.iew.exec_stores 178502513 # Number of stores executed -system.cpu.iew.exec_rate 1.996653 # Inst execution rate -system.cpu.iew.wb_sent 1933639401 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1923005119 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1456045504 # num instructions producing a value -system.cpu.iew.wb_consumers 2200626785 # num instructions consuming a value -system.cpu.iew.wb_rate 1.974132 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.661650 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 888612801 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 24293835 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 840170563 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.821157 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.461954 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 361187525 42.99% 42.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 184077910 21.91% 64.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 57677028 6.86% 71.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 87256558 10.39% 82.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 30345133 3.61% 85.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26488854 3.15% 88.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 10500866 1.25% 90.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9042630 1.08% 91.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 73594059 8.76% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 840170563 # Number of insts commited each cycle -system.cpu.commit.committedInsts 826847303 # Number of instructions committed -system.cpu.commit.committedOps 1530082520 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 533241508 # Number of memory references committed -system.cpu.commit.loads 384083313 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 149981740 # Number of branches committed -system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1527470225 # Number of committed integer instructions. -system.cpu.commit.function_calls 17673145 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 2048202 0.13% 0.13% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 989691028 64.68% 64.82% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 306834 0.02% 64.84% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 4794948 0.31% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 384083313 25.10% 90.25% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 149158195 9.75% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1530082520 # Class of committed instruction -system.cpu.commit.bw_lim_events 73594059 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3185271825 # The number of ROB reads -system.cpu.rob.rob_writes 4972894886 # The number of ROB writes -system.cpu.timesIdled 2025 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 203315 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 826847303 # Number of Instructions Simulated -system.cpu.committedOps 1530082520 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.178091 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.178091 # CPI: Total CPI of All Threads -system.cpu.ipc 0.848831 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.848831 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2927263565 # number of integer regfile reads -system.cpu.int_regfile_writes 1575987355 # number of integer regfile writes -system.cpu.fp_regfile_reads 281295 # number of floating regfile reads -system.cpu.fp_regfile_writes 5 # number of floating regfile writes -system.cpu.cc_regfile_reads 617980900 # number of cc regfile reads -system.cpu.cc_regfile_writes 419571241 # number of cc regfile writes -system.cpu.misc_regfile_reads 1064489388 # number of misc regfile reads -system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2545571 # number of replacements -system.cpu.dcache.tags.tagsinuse 4088.077195 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 420813077 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2549667 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.046289 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1863239500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4088.077195 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998066 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998066 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 606 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3449 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 850870799 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 850870799 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 272443625 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 272443625 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148366897 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148366897 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 420810522 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 420810522 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 420810522 # number of overall hits -system.cpu.dcache.overall_hits::total 420810522 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2558730 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2558730 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 791314 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 791314 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3350044 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3350044 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3350044 # number of overall misses -system.cpu.dcache.overall_misses::total 3350044 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 62817542000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 62817542000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 26367570500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 26367570500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 89185112500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 89185112500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 89185112500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 89185112500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 275002355 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 275002355 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 149158211 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 424160566 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 424160566 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 424160566 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 424160566 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009304 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009304 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005305 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005305 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.007898 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.007898 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007898 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007898 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24550.281585 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24550.281585 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33321.248581 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33321.248581 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26622.071979 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26622.071979 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26622.071979 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26622.071979 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 9991 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 13057 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 901 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.088790 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 1004.384615 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2337865 # number of writebacks -system.cpu.dcache.writebacks::total 2337865 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 792851 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 792851 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 5950 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 5950 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 798801 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 798801 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 798801 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 798801 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1765879 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1765879 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 785364 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 785364 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2551243 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2551243 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2551243 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2551243 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37626062000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 37626062000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25475564000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 25475564000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63101626000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 63101626000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63101626000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 63101626000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006421 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006421 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005265 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005265 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006015 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006015 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006015 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006015 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21307.270770 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21307.270770 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32437.906499 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32437.906499 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24733.679230 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24733.679230 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24733.679230 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24733.679230 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 3942 # number of replacements -system.cpu.icache.tags.tagsinuse 1083.391017 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 216536709 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5668 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 38203.371383 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1083.391017 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.529000 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.529000 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1726 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 80 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1564 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.842773 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 433100363 # Number of tag accesses -system.cpu.icache.tags.data_accesses 433100363 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 216536917 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 216536917 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 216536917 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 216536917 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 216536917 # number of overall hits -system.cpu.icache.overall_hits::total 216536917 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 9643 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 9643 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 9643 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 9643 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 9643 # number of overall misses -system.cpu.icache.overall_misses::total 9643 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 597021000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 597021000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 597021000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 597021000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 597021000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 597021000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 216546560 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 216546560 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 216546560 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 216546560 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 216546560 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 216546560 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61912.371669 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61912.371669 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61912.371669 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61912.371669 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61912.371669 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61912.371669 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1205 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 100.416667 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 3942 # number of writebacks -system.cpu.icache.writebacks::total 3942 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2400 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2400 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2400 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2400 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2400 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2400 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7243 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 7243 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 7243 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 7243 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 7243 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 7243 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 398397500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 398397500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 398397500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 398397500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 398397500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 398397500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000033 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000033 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000033 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000033 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000033 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000033 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55004.487091 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55004.487091 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55004.487091 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 55004.487091 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55004.487091 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 55004.487091 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 356141 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30645.512705 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4711567 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 388909 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.114831 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 82679985000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 70.320646 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 194.041770 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 30381.150290 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.002146 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005922 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.927159 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.935227 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 176 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1392 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31134 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 41192837 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 41192837 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 2337865 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2337865 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 3849 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 3849 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1570 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1570 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 577208 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 577208 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3147 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 3147 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1587166 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1587166 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3147 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2164374 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2167521 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3147 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2164374 # number of overall hits -system.cpu.l2cache.overall_hits::total 2167521 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 206826 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206826 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2443 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2443 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 178467 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 178467 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2443 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 385293 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 387736 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2443 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 385293 # number of overall misses -system.cpu.l2cache.overall_misses::total 387736 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 30500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 30500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 18217457500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 18217457500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 351826000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 351826000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 18259810000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 18259810000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 351826000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 36477267500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 36829093500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 351826000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 36477267500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 36829093500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 2337865 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 2337865 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 3849 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 3849 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1576 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1576 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 784034 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 784034 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5590 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 5590 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1765633 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1765633 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 5590 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2549667 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2555257 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 5590 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2549667 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2555257 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.003807 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.003807 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.263797 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.263797 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.437030 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.437030 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.101078 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.101078 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.437030 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.151115 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.151741 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.437030 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.151115 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.151741 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 5083.333333 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 5083.333333 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88081.080232 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88081.080232 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 144013.917315 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 144013.917315 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 102314.769677 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 102314.769677 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 144013.917315 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94674.098673 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 94984.973023 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 144013.917315 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94674.098673 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 94984.973023 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 295491 # number of writebacks -system.cpu.l2cache.writebacks::total 295491 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 10 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 10 # number of CleanEvict MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206826 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206826 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2443 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2443 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 178467 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 178467 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2443 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 385293 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 387736 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2443 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 385293 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 387736 # number of overall MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 120000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 120000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16149197500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16149197500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 327396000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 327396000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16475140000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16475140000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 327396000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 32624337500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 32951733500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 327396000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 32624337500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 32951733500 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.003807 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.003807 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.263797 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.263797 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.437030 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.437030 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.101078 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.101078 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.437030 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151115 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151741 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.437030 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151115 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151741 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78081.080232 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78081.080232 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 134013.917315 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 134013.917315 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 92314.769677 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 92314.769677 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 134013.917315 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84674.098673 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84984.973023 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 134013.917315 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84674.098673 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84984.973023 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5107999 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2549734 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 19983 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 3565 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3558 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1772876 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2633356 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 3942 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 268356 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 1576 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 1576 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 784034 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 784034 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 7243 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1765633 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16775 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7648057 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7664832 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 610048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312802048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 313412096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 357794 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 19017216 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2914627 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.008154 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.089959 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2890867 99.18% 99.18% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 23753 0.81% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 7 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2914627 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4895855901 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 10867494 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3825288599 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 740964 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 353722 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 180910 # Transaction distribution -system.membus.trans_dist::WritebackDirty 295491 # Transaction distribution -system.membus.trans_dist::CleanEvict 57731 # Transaction distribution -system.membus.trans_dist::UpgradeReq 9 # Transaction distribution -system.membus.trans_dist::ReadExReq 206823 # Transaction distribution -system.membus.trans_dist::ReadExResp 206823 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 180910 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1128697 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1128697 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1128697 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43726336 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43726336 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43726336 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 387742 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 387742 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 387742 # Request fanout histogram -system.membus.reqLayer0.occupancy 1998138500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 2051606500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.4 # Layer utilization (%) +sim_seconds 0.487051 +sim_ticks 487050729500 +final_tick 487050729500 +sim_freq 1000000000000 +host_inst_rate 109718 +host_op_rate 203033 +host_tick_rate 64628655 +host_mem_usage 330116 +host_seconds 7536.14 +sim_insts 826847303 +sim_ops 1530082520 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 487050729500 +system.physmem.bytes_read::cpu.inst 156352 +system.physmem.bytes_read::cpu.data 24658560 +system.physmem.bytes_read::total 24814912 +system.physmem.bytes_inst_read::cpu.inst 156352 +system.physmem.bytes_inst_read::total 156352 +system.physmem.bytes_written::writebacks 18911424 +system.physmem.bytes_written::total 18911424 +system.physmem.num_reads::cpu.inst 2443 +system.physmem.num_reads::cpu.data 385290 +system.physmem.num_reads::total 387733 +system.physmem.num_writes::writebacks 295491 +system.physmem.num_writes::total 295491 +system.physmem.bw_read::cpu.inst 321018 +system.physmem.bw_read::cpu.data 50628320 +system.physmem.bw_read::total 50949338 +system.physmem.bw_inst_read::cpu.inst 321018 +system.physmem.bw_inst_read::total 321018 +system.physmem.bw_write::writebacks 38828448 +system.physmem.bw_write::total 38828448 +system.physmem.bw_total::writebacks 38828448 +system.physmem.bw_total::cpu.inst 321018 +system.physmem.bw_total::cpu.data 50628320 +system.physmem.bw_total::total 89777786 +system.physmem.readReqs 387733 +system.physmem.writeReqs 295491 +system.physmem.readBursts 387733 +system.physmem.writeBursts 295491 +system.physmem.bytesReadDRAM 24795072 +system.physmem.bytesReadWrQ 19840 +system.physmem.bytesWritten 18909504 +system.physmem.bytesReadSys 24814912 +system.physmem.bytesWrittenSys 18911424 +system.physmem.servicedByWrQ 310 +system.physmem.mergedWrBursts 0 +system.physmem.neitherReadNorWriteReqs 0 +system.physmem.perBankRdBursts::0 24612 +system.physmem.perBankRdBursts::1 26389 +system.physmem.perBankRdBursts::2 24828 +system.physmem.perBankRdBursts::3 24571 +system.physmem.perBankRdBursts::4 23534 +system.physmem.perBankRdBursts::5 23661 +system.physmem.perBankRdBursts::6 24754 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+system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 387742 +system.membus.reqLayer0.occupancy 1998138500 +system.membus.reqLayer0.utilization 0.4 +system.membus.respLayer1.occupancy 2051606500 +system.membus.respLayer1.utilization 0.4 ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini index 4c9b068a2..dd85c448b 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=atomic @@ -88,6 +89,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -167,7 +169,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=parser 2.1.dict -batch cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic drivers= @@ -176,14 +178,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/parser +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 -input=/arm/projectscratch/randd/systems/dist/cpu2000/data/parser/mdred/input/parser.in +input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/parser/mdred/input/parser.in kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=114600000000 system=system uid=100 @@ -207,6 +210,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -218,7 +222,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -226,6 +230,13 @@ width=16 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -234,6 +245,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -241,7 +253,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr index aadc3d011..43d70058a 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr @@ -1,2 +1,6 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout index 3a0d1b2f1..227ee869b 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout @@ -3,16 +3,14 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-ato gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:35:23 -gem5 started Jul 21 2016 14:36:19 -gem5 executing on e108600-lin, pid 18563 -command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/x86/linux/simple-atomic +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:22 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87200 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/20.parser/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... - Reading the dictionary files: *****************************info: Increasing stack size by one page. -******************** + Reading the dictionary files: ************************************************* 58924 words stored in 3784810 bytes @@ -26,8 +24,6 @@ Echoing of input sentence turned on. * as had expected the party to be a success , it was a success * do you know where John 's * he said that , finding that it was impossible to get work as a waiter , he would work as a janitor -info: Increasing stack size by one page. -info: Increasing stack size by one page. * how fast the program is it * I am wondering whether to invite to the party * I gave him for his birthday it @@ -72,4 +68,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 885772926000 because target called exit() +Exiting @ tick 885772926000 because exiting with last active thread context diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt index 0b4609b35..5fc9dc6b8 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -1,145 +1,145 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.885773 # Number of seconds simulated -sim_ticks 885772926000 # Number of ticks simulated -final_tick 885772926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1551014 # Simulator instruction rate (inst/s) -host_op_rate 2870153 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1661547121 # Simulator tick rate (ticks/s) -host_mem_usage 272636 # Number of bytes of host memory used -host_seconds 533.10 # Real time elapsed on the host -sim_insts 826847304 # Number of instructions simulated -sim_ops 1530082521 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 8546485088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 2285527276 # Number of bytes read from this memory -system.physmem.bytes_read::total 10832012364 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 8546485088 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 8546485088 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 991837474 # Number of bytes written to this memory -system.physmem.bytes_written::total 991837474 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1068310636 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 384083342 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1452393978 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 149158211 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149158211 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 9648618554 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2580263190 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12228881744 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 9648618554 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 9648618554 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1119742368 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1119742368 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 9648618554 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3700005559 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13348624112 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 551 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 885772926000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1771545853 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 826847304 # Number of instructions committed -system.cpu.committedOps 1530082521 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1527470226 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 35346287 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 92881952 # number of instructions that are conditional controls -system.cpu.num_int_insts 1527470226 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 3298246119 # number of times the integer registers were read -system.cpu.num_int_register_writes 1240060586 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 562449682 # number of times the CC registers were read -system.cpu.num_cc_register_writes 376900986 # number of times the CC registers were written -system.cpu.num_mem_refs 533241508 # number of memory refs -system.cpu.num_load_insts 384083313 # Number of load instructions -system.cpu.num_store_insts 149158195 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1771545852.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 149981740 # Number of branches fetched -system.cpu.op_class::No_OpClass 2048202 0.13% 0.13% # Class of executed instruction -system.cpu.op_class::IntAlu 989691029 64.68% 64.82% # Class of executed instruction -system.cpu.op_class::IntMult 306834 0.02% 64.84% # Class of executed instruction -system.cpu.op_class::IntDiv 4794948 0.31% 65.15% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::MemRead 384083313 25.10% 90.25% # Class of executed instruction -system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1530082521 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 1452393978 # Transaction distribution -system.membus.trans_dist::ReadResp 1452393978 # Transaction distribution -system.membus.trans_dist::WriteReq 149158211 # Transaction distribution -system.membus.trans_dist::WriteResp 149158211 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 2136621272 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.icache_port::total 2136621272 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1066483106 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::total 1066483106 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3203104378 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 8546485088 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::total 8546485088 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 3277364750 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::total 3277364750 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 11823849838 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1601552189 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1601552189 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1601552189 # Request fanout histogram +sim_seconds 0.885773 +sim_ticks 885772926000 +final_tick 885772926000 +sim_freq 1000000000000 +host_inst_rate 728826 +host_op_rate 1348694 +host_tick_rate 780766307 +host_mem_usage 284536 +host_seconds 1134.49 +sim_insts 826847304 +sim_ops 1530082521 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 885772926000 +system.physmem.bytes_read::cpu.inst 8546485088 +system.physmem.bytes_read::cpu.data 2285527276 +system.physmem.bytes_read::total 10832012364 +system.physmem.bytes_inst_read::cpu.inst 8546485088 +system.physmem.bytes_inst_read::total 8546485088 +system.physmem.bytes_written::cpu.data 991837474 +system.physmem.bytes_written::total 991837474 +system.physmem.num_reads::cpu.inst 1068310636 +system.physmem.num_reads::cpu.data 384083342 +system.physmem.num_reads::total 1452393978 +system.physmem.num_writes::cpu.data 149158211 +system.physmem.num_writes::total 149158211 +system.physmem.bw_read::cpu.inst 9648618554 +system.physmem.bw_read::cpu.data 2580263190 +system.physmem.bw_read::total 12228881744 +system.physmem.bw_inst_read::cpu.inst 9648618554 +system.physmem.bw_inst_read::total 9648618554 +system.physmem.bw_write::cpu.data 1119742368 +system.physmem.bw_write::total 1119742368 +system.physmem.bw_total::cpu.inst 9648618554 +system.physmem.bw_total::cpu.data 3700005559 +system.physmem.bw_total::total 13348624112 +system.pwrStateResidencyTicks::UNDEFINED 885772926000 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 885772926000 +system.cpu.apic_clk_domain.clock 8000 +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 885772926000 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 885772926000 +system.cpu.workload.numSyscalls 551 +system.cpu.pwrStateResidencyTicks::ON 885772926000 +system.cpu.numCycles 1771545853 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 826847304 +system.cpu.committedOps 1530082521 +system.cpu.num_int_alu_accesses 1527470226 +system.cpu.num_fp_alu_accesses 0 +system.cpu.num_func_calls 35346287 +system.cpu.num_conditional_control_insts 92881952 +system.cpu.num_int_insts 1527470226 +system.cpu.num_fp_insts 0 +system.cpu.num_int_register_reads 3298246119 +system.cpu.num_int_register_writes 1240060586 +system.cpu.num_fp_register_reads 0 +system.cpu.num_fp_register_writes 0 +system.cpu.num_cc_register_reads 562449682 +system.cpu.num_cc_register_writes 376900986 +system.cpu.num_mem_refs 533241508 +system.cpu.num_load_insts 384083313 +system.cpu.num_store_insts 149158195 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 1771545853 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 149981740 +system.cpu.op_class::No_OpClass 2048202 0.13% 0.13% +system.cpu.op_class::IntAlu 989691029 64.68% 64.82% +system.cpu.op_class::IntMult 306834 0.02% 64.84% +system.cpu.op_class::IntDiv 4794948 0.31% 65.15% +system.cpu.op_class::FloatAdd 0 0.00% 65.15% +system.cpu.op_class::FloatCmp 0 0.00% 65.15% +system.cpu.op_class::FloatCvt 0 0.00% 65.15% +system.cpu.op_class::FloatMult 0 0.00% 65.15% +system.cpu.op_class::FloatMultAcc 0 0.00% 65.15% +system.cpu.op_class::FloatDiv 0 0.00% 65.15% +system.cpu.op_class::FloatMisc 0 0.00% 65.15% +system.cpu.op_class::FloatSqrt 0 0.00% 65.15% +system.cpu.op_class::SimdAdd 0 0.00% 65.15% +system.cpu.op_class::SimdAddAcc 0 0.00% 65.15% +system.cpu.op_class::SimdAlu 0 0.00% 65.15% +system.cpu.op_class::SimdCmp 0 0.00% 65.15% +system.cpu.op_class::SimdCvt 0 0.00% 65.15% +system.cpu.op_class::SimdMisc 0 0.00% 65.15% +system.cpu.op_class::SimdMult 0 0.00% 65.15% +system.cpu.op_class::SimdMultAcc 0 0.00% 65.15% +system.cpu.op_class::SimdShift 0 0.00% 65.15% +system.cpu.op_class::SimdShiftAcc 0 0.00% 65.15% +system.cpu.op_class::SimdSqrt 0 0.00% 65.15% +system.cpu.op_class::SimdFloatAdd 0 0.00% 65.15% +system.cpu.op_class::SimdFloatAlu 0 0.00% 65.15% +system.cpu.op_class::SimdFloatCmp 0 0.00% 65.15% +system.cpu.op_class::SimdFloatCvt 0 0.00% 65.15% +system.cpu.op_class::SimdFloatDiv 0 0.00% 65.15% +system.cpu.op_class::SimdFloatMisc 0 0.00% 65.15% +system.cpu.op_class::SimdFloatMult 0 0.00% 65.15% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15% +system.cpu.op_class::MemRead 384083313 25.10% 90.25% +system.cpu.op_class::MemWrite 149158195 9.75% 100.00% +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 1530082521 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 885772926000 +system.membus.trans_dist::ReadReq 1452393978 +system.membus.trans_dist::ReadResp 1452393978 +system.membus.trans_dist::WriteReq 149158211 +system.membus.trans_dist::WriteResp 149158211 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 2136621272 +system.membus.pkt_count_system.cpu.icache_port::total 2136621272 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1066483106 +system.membus.pkt_count_system.cpu.dcache_port::total 1066483106 +system.membus.pkt_count::total 3203104378 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 8546485088 +system.membus.pkt_size_system.cpu.icache_port::total 8546485088 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 3277364750 +system.membus.pkt_size_system.cpu.dcache_port::total 3277364750 +system.membus.pkt_size::total 11823849838 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 1601552189 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 1601552189 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 1601552189 ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini index d62d690f2..6ea332421 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=timing @@ -85,6 +86,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -100,14 +102,14 @@ eventq_index=0 [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -121,6 +123,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -133,15 +136,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dtb] type=X86TLB @@ -166,14 +170,14 @@ port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -187,6 +191,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -199,15 +204,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=X86LocalApic @@ -253,14 +259,14 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -274,6 +280,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -286,15 +293,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -330,7 +338,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=parser 2.1.dict -batch cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing drivers= @@ -339,14 +347,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/parser +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 -input=/arm/projectscratch/randd/systems/dist/cpu2000/data/parser/mdred/input/parser.in +input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/parser/mdred/input/parser.in kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=114600000000 system=system uid=100 @@ -370,6 +379,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -381,7 +391,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -389,6 +399,13 @@ width=16 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -397,6 +414,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -404,7 +422,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr index aadc3d011..43d70058a 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr @@ -1,2 +1,6 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout index e0c4a0b01..5231f3e17 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout @@ -3,16 +3,14 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:35:23 -gem5 started Jul 21 2016 14:36:17 -gem5 executing on e108600-lin, pid 18541 -command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/x86/linux/simple-timing +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:22 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87196 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... - Reading the dictionary files: *****************************info: Increasing stack size by one page. -******************** + Reading the dictionary files: ************************************************* 58924 words stored in 3784810 bytes @@ -26,8 +24,6 @@ Echoing of input sentence turned on. * as had expected the party to be a success , it was a success * do you know where John 's * he said that , finding that it was impossible to get work as a waiter , he would work as a janitor -info: Increasing stack size by one page. -info: Increasing stack size by one page. * how fast the program is it * I am wondering whether to invite to the party * I gave him for his birthday it @@ -72,4 +68,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 1650501252500 because target called exit() +Exiting @ tick 1650923912500 because exiting with last active thread context diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index bbca4e86c..48f9b108e 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,546 +1,546 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.650924 # Number of seconds simulated -sim_ticks 1650923912500 # Number of ticks simulated -final_tick 1650923912500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1073233 # Simulator instruction rate (inst/s) -host_op_rate 1986019 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2142868820 # Simulator tick rate (ticks/s) -host_mem_usage 285448 # Number of bytes of host memory used -host_seconds 770.43 # Real time elapsed on the host -sim_insts 826847304 # Number of instructions simulated -sim_ops 1530082521 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 115968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24312256 # Number of bytes read from this memory -system.physmem.bytes_read::total 24428224 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 115968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 115968 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18812864 # Number of bytes written to this memory -system.physmem.bytes_written::total 18812864 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1812 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 379879 # Number of read requests responded to by this memory -system.physmem.num_reads::total 381691 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293951 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293951 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 70244 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 14726455 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14796699 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 70244 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 70244 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 11395355 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 11395355 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 11395355 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 70244 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 14726455 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 26192054 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 551 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 1650923912500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 3301847825 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 826847304 # Number of instructions committed -system.cpu.committedOps 1530082521 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1527470226 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 35346287 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 92881952 # number of instructions that are conditional controls -system.cpu.num_int_insts 1527470226 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 3298246119 # number of times the integer registers were read -system.cpu.num_int_register_writes 1240060586 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 562449682 # number of times the CC registers were read -system.cpu.num_cc_register_writes 376900986 # number of times the CC registers were written -system.cpu.num_mem_refs 533241508 # number of memory refs -system.cpu.num_load_insts 384083313 # Number of load instructions -system.cpu.num_store_insts 149158195 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 3301847824.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 149981740 # Number of branches fetched -system.cpu.op_class::No_OpClass 2048202 0.13% 0.13% # Class of executed instruction -system.cpu.op_class::IntAlu 989691029 64.68% 64.82% # Class of executed instruction -system.cpu.op_class::IntMult 306834 0.02% 64.84% # Class of executed instruction -system.cpu.op_class::IntDiv 4794948 0.31% 65.15% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::MemRead 384083313 25.10% 90.25% # Class of executed instruction -system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1530082521 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2517016 # number of replacements -system.cpu.dcache.tags.tagsinuse 4086.382570 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 530720441 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2521112 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 210.510458 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 8250925500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4086.382570 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997652 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997652 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1069004218 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1069004218 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 382353600 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 382353600 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148366841 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148366841 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 530720441 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 530720441 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 530720441 # number of overall hits -system.cpu.dcache.overall_hits::total 530720441 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1729742 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1729742 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 791370 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 791370 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2521112 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2521112 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2521112 # number of overall misses -system.cpu.dcache.overall_misses::total 2521112 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 31154171500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31154171500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20614263500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20614263500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 51768435000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 51768435000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 51768435000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 51768435000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 384083342 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 384083342 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 149158211 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 533241553 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 533241553 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 533241553 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 533241553 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004504 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004504 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005306 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005306 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.004728 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.004728 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.004728 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.004728 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18010.877634 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 18010.877634 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26048.831141 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 26048.831141 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20533.968741 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20533.968741 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20533.968741 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20533.968741 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each 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-system.cpu.dcache.ReadReq_mshr_miss_latency::total 29424429500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19822893500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 19822893500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49247323000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 49247323000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49247323000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 49247323000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004504 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004504 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005306 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005306 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004728 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.004728 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004728 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.004728 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17010.877634 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17010.877634 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25048.831141 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25048.831141 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19533.968741 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19533.968741 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19533.968741 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19533.968741 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1253 # number of replacements -system.cpu.icache.tags.tagsinuse 881.361666 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1068307822 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 379640.306326 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 881.361666 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.430352 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.430352 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 # Percentage of cache occupancy per task id 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latency -system.cpu.icache.ReadReq_avg_miss_latency::total 45215.707178 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 45215.707178 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 45215.707178 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 45215.707178 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 45215.707178 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles 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latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 44215.707178 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 44215.707178 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 44215.707178 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 44215.707178 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 44215.707178 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 349420 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30439.047290 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4660001 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 382188 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.192955 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 287867097000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 31.679459 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.475071 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 30276.892760 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000967 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003982 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.923977 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.928926 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 346 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 32344 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 40719748 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 40719748 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 2324919 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2324919 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1253 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1253 # number of WritebackClean hits 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-system.cpu.l2cache.ReadExReq_misses::cpu.data 206529 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206529 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1812 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 1812 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 173350 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 173350 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1812 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 379879 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 381691 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1812 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 379879 # number of overall misses -system.cpu.l2cache.overall_misses::total 381691 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12495008000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 12495008000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 109669500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 109669500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10487697500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 10487697500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 109669500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 22982705500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23092375000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 109669500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 22982705500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23092375000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 2324919 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 2324919 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1253 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1253 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 791370 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 791370 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2814 # number of ReadCleanReq accesses(hits+misses) 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60524.006623 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500.068443 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60500.182084 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 293952 # number of writebacks -system.cpu.l2cache.writebacks::total 293952 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 6 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 6 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206529 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206529 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1812 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1812 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 173350 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 173350 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1812 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 379879 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 381691 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1812 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 379879 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 381691 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10429718000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10429718000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 91549500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 91549500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8754197500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8754197500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 91549500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19183915500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19275465000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 91549500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19183915500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19275465000 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260977 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260977 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.643923 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.643923 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100217 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100217 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.643923 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150679 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151229 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.643923 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150679 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151229 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.016947 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.016947 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50524.006623 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50524.006623 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.129795 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.129795 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50524.006623 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.068443 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.182084 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50524.006623 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.068443 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.182084 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5042195 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2518269 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1866 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1866 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1732556 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2618871 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1253 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 247565 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 791370 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 791370 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 2814 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1729742 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6881 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7559240 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7566121 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260288 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310145984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 310406272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 349420 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 18812928 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2873346 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000649 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.025475 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2871480 99.94% 99.94% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1866 0.06% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2873346 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4847269500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3781668000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 729250 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 347559 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 175162 # Transaction distribution -system.membus.trans_dist::WritebackDirty 293951 # Transaction distribution -system.membus.trans_dist::CleanEvict 53608 # Transaction distribution -system.membus.trans_dist::ReadExReq 206529 # Transaction distribution -system.membus.trans_dist::ReadExResp 206529 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 175162 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1110941 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1110941 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1110941 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43241088 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43241088 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43241088 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 381691 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 381691 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 381691 # Request fanout histogram -system.membus.reqLayer0.occupancy 1905079500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1908455000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +sim_seconds 1.650924 +sim_ticks 1650923912500 +final_tick 1650923912500 +sim_freq 1000000000000 +host_inst_rate 500428 +host_op_rate 926043 +host_tick_rate 999178622 +host_mem_usage 295552 +host_seconds 1652.28 +sim_insts 826847304 +sim_ops 1530082521 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 1650923912500 +system.physmem.bytes_read::cpu.inst 115968 +system.physmem.bytes_read::cpu.data 24312256 +system.physmem.bytes_read::total 24428224 +system.physmem.bytes_inst_read::cpu.inst 115968 +system.physmem.bytes_inst_read::total 115968 +system.physmem.bytes_written::writebacks 18812864 +system.physmem.bytes_written::total 18812864 +system.physmem.num_reads::cpu.inst 1812 +system.physmem.num_reads::cpu.data 379879 +system.physmem.num_reads::total 381691 +system.physmem.num_writes::writebacks 293951 +system.physmem.num_writes::total 293951 +system.physmem.bw_read::cpu.inst 70244 +system.physmem.bw_read::cpu.data 14726455 +system.physmem.bw_read::total 14796699 +system.physmem.bw_inst_read::cpu.inst 70244 +system.physmem.bw_inst_read::total 70244 +system.physmem.bw_write::writebacks 11395355 +system.physmem.bw_write::total 11395355 +system.physmem.bw_total::writebacks 11395355 +system.physmem.bw_total::cpu.inst 70244 +system.physmem.bw_total::cpu.data 14726455 +system.physmem.bw_total::total 26192054 +system.pwrStateResidencyTicks::UNDEFINED 1650923912500 +system.cpu_clk_domain.clock 500 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376900986 +system.cpu.num_mem_refs 533241508 +system.cpu.num_load_insts 384083313 +system.cpu.num_store_insts 149158195 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 3301847825 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 149981740 +system.cpu.op_class::No_OpClass 2048202 0.13% 0.13% +system.cpu.op_class::IntAlu 989691029 64.68% 64.82% +system.cpu.op_class::IntMult 306834 0.02% 64.84% +system.cpu.op_class::IntDiv 4794948 0.31% 65.15% +system.cpu.op_class::FloatAdd 0 0.00% 65.15% +system.cpu.op_class::FloatCmp 0 0.00% 65.15% +system.cpu.op_class::FloatCvt 0 0.00% 65.15% +system.cpu.op_class::FloatMult 0 0.00% 65.15% +system.cpu.op_class::FloatMultAcc 0 0.00% 65.15% +system.cpu.op_class::FloatDiv 0 0.00% 65.15% +system.cpu.op_class::FloatMisc 0 0.00% 65.15% +system.cpu.op_class::FloatSqrt 0 0.00% 65.15% +system.cpu.op_class::SimdAdd 0 0.00% 65.15% +system.cpu.op_class::SimdAddAcc 0 0.00% 65.15% +system.cpu.op_class::SimdAlu 0 0.00% 65.15% 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+system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 +system.cpu.dcache.tags.occ_task_id_percent::1024 1 +system.cpu.dcache.tags.tag_accesses 1069004218 +system.cpu.dcache.tags.data_accesses 1069004218 +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1650923912500 +system.cpu.dcache.ReadReq_hits::cpu.data 382353600 +system.cpu.dcache.ReadReq_hits::total 382353600 +system.cpu.dcache.WriteReq_hits::cpu.data 148366841 +system.cpu.dcache.WriteReq_hits::total 148366841 +system.cpu.dcache.demand_hits::cpu.data 530720441 +system.cpu.dcache.demand_hits::total 530720441 +system.cpu.dcache.overall_hits::cpu.data 530720441 +system.cpu.dcache.overall_hits::total 530720441 +system.cpu.dcache.ReadReq_misses::cpu.data 1729742 +system.cpu.dcache.ReadReq_misses::total 1729742 +system.cpu.dcache.WriteReq_misses::cpu.data 791370 +system.cpu.dcache.WriteReq_misses::total 791370 +system.cpu.dcache.demand_misses::cpu.data 2521112 +system.cpu.dcache.demand_misses::total 2521112 +system.cpu.dcache.overall_misses::cpu.data 2521112 +system.cpu.dcache.overall_misses::total 2521112 +system.cpu.dcache.ReadReq_miss_latency::cpu.data 31154171500 +system.cpu.dcache.ReadReq_miss_latency::total 31154171500 +system.cpu.dcache.WriteReq_miss_latency::cpu.data 20614263500 +system.cpu.dcache.WriteReq_miss_latency::total 20614263500 +system.cpu.dcache.demand_miss_latency::cpu.data 51768435000 +system.cpu.dcache.demand_miss_latency::total 51768435000 +system.cpu.dcache.overall_miss_latency::cpu.data 51768435000 +system.cpu.dcache.overall_miss_latency::total 51768435000 +system.cpu.dcache.ReadReq_accesses::cpu.data 384083342 +system.cpu.dcache.ReadReq_accesses::total 384083342 +system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 +system.cpu.dcache.WriteReq_accesses::total 149158211 +system.cpu.dcache.demand_accesses::cpu.data 533241553 +system.cpu.dcache.demand_accesses::total 533241553 +system.cpu.dcache.overall_accesses::cpu.data 533241553 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+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1110941 +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1110941 +system.membus.pkt_count::total 1110941 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43241088 +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43241088 +system.membus.pkt_size::total 43241088 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 381691 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 381691 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 381691 +system.membus.reqLayer0.occupancy 1905079500 +system.membus.reqLayer0.utilization 0.1 +system.membus.respLayer1.occupancy 1908455000 +system.membus.respLayer1.utilization 0.1 ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini index 3870e90de..2c21341f7 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini @@ -65,7 +65,7 @@ SSITSize=1024 activity=0 backComSize=5 branchPred=system.cpu.branchPred -cachePorts=200 +cacheStorePorts=200 checker=Null clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 @@ -141,6 +141,7 @@ socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -176,10 +177,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=6 @@ -193,6 +194,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=8 write_buffers=16 @@ -205,15 +207,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu.dstage2_mmu] type=ArmStage2MMU @@ -316,38 +319,52 @@ pipelined=true [system.cpu.fuPool.FUList2] type=FUDesc -children=opList +children=opList0 opList1 count=1 eventq_index=0 -opList=system.cpu.fuPool.FUList2.opList +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 -[system.cpu.fuPool.FUList2.opList] +[system.cpu.fuPool.FUList2.opList0] type=OpDesc eventq_index=0 opClass=MemRead opLat=2 pipelined=true +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=2 +pipelined=true + [system.cpu.fuPool.FUList3] type=FUDesc -children=opList +children=opList0 opList1 count=1 eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 -[system.cpu.fuPool.FUList3.opList] +[system.cpu.fuPool.FUList3.opList0] type=OpDesc eventq_index=0 opClass=MemWrite opLat=2 pipelined=true +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=2 +pipelined=true + [system.cpu.fuPool.FUList4] type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27 count=2 eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 +opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27 [system.cpu.fuPool.FUList4.opList00] type=OpDesc @@ -479,7 +496,7 @@ pipelined=true type=OpDesc eventq_index=0 opClass=SimdFloatMultAcc -opLat=1 +opLat=5 pipelined=true [system.cpu.fuPool.FUList4.opList19] @@ -531,6 +548,20 @@ opClass=FloatMult opLat=4 pipelined=true +[system.cpu.fuPool.FUList4.opList26] +type=OpDesc +eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList4.opList27] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + [system.cpu.icache] type=Cache children=tags @@ -538,10 +569,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=1 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=1 is_read_only=true max_miss_count=0 mshrs=2 @@ -555,6 +586,7 @@ response_latency=1 sequential_access=false size=32768 system=system +tag_latency=1 tags=system.cpu.icache.tags tgts_per_mshr=8 write_buffers=8 @@ -567,15 +599,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=1 default_p_state=UNDEFINED eventq_index=0 -hit_latency=1 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=1 [system.cpu.interrupts] type=ArmInterrupts @@ -594,8 +627,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -606,8 +637,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -670,10 +699,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl +data_latency=12 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=12 is_read_only=false max_miss_count=0 mshrs=16 @@ -687,6 +716,7 @@ response_latency=12 sequential_access=false size=1048576 system=system +tag_latency=12 tags=system.cpu.l2cache.tags tgts_per_mshr=8 write_buffers=8 @@ -729,15 +759,16 @@ type=RandomRepl assoc=16 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=12 default_p_state=UNDEFINED eventq_index=0 -hit_latency=12 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=1048576 +tag_latency=12 [system.cpu.toL2Bus] type=CoherentXBar @@ -773,7 +804,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing drivers= @@ -782,14 +813,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/eon +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/eon gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr index 3415c9346..2f8aeb16c 100755 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr @@ -1,11 +1,14 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. getting pixel output filename pixels_out.cook opening control file chair.control.cook opening camera file chair.camera opening surfaces file chair.surfaces reading data +info: Increasing stack size by one page. processing 8parts Grid measure is 6 by 3.0001 by 6 cell dimension is 0.863065 @@ -32,6 +35,8 @@ col 12. . . col 13. . . col 14. . . Writing to chair.cook.ppm +info: Increasing stack size by one page. +info: Increasing stack size by one page. 0 8 14 1 8 14 2 8 14 diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout index 5ac8e5d82..2e95c35f3 100755 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout @@ -3,17 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/sim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:51:10 -gem5 executing on e108600-lin, pid 17461 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/arm/linux/o3-timing +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 18:05:52 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 55337 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. Eon, Version 1.1 -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. OO-style eon Time= 0.120000 -Exiting @ tick 122177531500 because target called exit() +Exiting @ tick 124340889500 because exiting with last active thread context diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index be47c4345..f1f3dd777 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,1241 +1,1241 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.124341 # Number of seconds simulated -sim_ticks 124340889500 # Number of ticks simulated -final_tick 124340889500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 229813 # Simulator instruction rate (inst/s) -host_op_rate 275917 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 104656772 # Simulator tick rate (ticks/s) -host_mem_usage 292960 # Number of bytes of host memory used -host_seconds 1188.08 # Real time elapsed on the host -sim_insts 273037218 # Number of instructions simulated -sim_ops 327811600 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 1894400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 14645312 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 169216 # Number of bytes read from this memory -system.physmem.bytes_read::total 16708928 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1894400 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1894400 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 29600 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 228833 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 2644 # Number of read requests responded to by this memory -system.physmem.num_reads::total 261077 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 15235535 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 117783555 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 1360904 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 134379994 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 15235535 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 15235535 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 15235535 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 117783555 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 1360904 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 134379994 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 261078 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 261078 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 16708992 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 16708992 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1259 # Per bank write bursts -system.physmem.perBankRdBursts::1 69989 # Per bank write bursts -system.physmem.perBankRdBursts::2 1294 # Per bank write bursts -system.physmem.perBankRdBursts::3 10805 # Per bank write bursts -system.physmem.perBankRdBursts::4 42847 # Per bank write bursts -system.physmem.perBankRdBursts::5 121814 # Per bank write bursts -system.physmem.perBankRdBursts::6 160 # Per bank write bursts -system.physmem.perBankRdBursts::7 259 # Per bank write bursts -system.physmem.perBankRdBursts::8 225 # Per bank write bursts -system.physmem.perBankRdBursts::9 562 # Per bank write bursts -system.physmem.perBankRdBursts::10 7823 # Per bank write bursts -system.physmem.perBankRdBursts::11 812 # Per bank write bursts -system.physmem.perBankRdBursts::12 1216 # Per bank write bursts -system.physmem.perBankRdBursts::13 747 # Per bank write bursts -system.physmem.perBankRdBursts::14 656 # Per bank write bursts -system.physmem.perBankRdBursts::15 610 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 124340880000 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 261078 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 204158 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 43358 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 12121 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 308 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 247 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 209 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 181 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 231 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 123 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 61 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 67983 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 245.745201 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 180.705876 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 200.483366 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 18259 26.86% 26.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22263 32.75% 59.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 11383 16.74% 76.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 6868 10.10% 86.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4760 7.00% 93.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2080 3.06% 96.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1310 1.93% 98.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 394 0.58% 99.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 666 0.98% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 67983 # Bytes accessed per row activation -system.physmem.totQLat 4612072505 # Total ticks spent queuing -system.physmem.totMemAccLat 9507285005 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1305390000 # Total ticks spent in databus transfers -system.physmem.avgQLat 17665.50 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 36415.50 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 134.38 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 134.38 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.05 # Data bus utilization in percentage -system.physmem.busUtilRead 1.05 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.60 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 193085 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.96 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 476259.51 # Average gap between requests -system.physmem.pageHitRate 73.96 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 450291240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 239324085 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1773768780 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 9681809280.000002 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4644193560 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 227236800 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 45907805700 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 3604922400 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 978458700 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 67507810545 # Total energy per rank (pJ) -system.physmem_0.averagePower 542.925264 # Core power per rank (mW) -system.physmem_0.totalIdleTime 113563299646 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 155533000 # Time in different power states -system.physmem_0.memoryStateTime::REF 4097020000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 3501663750 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 9387944632 # Time in different power states -system.physmem_0.memoryStateTime::ACT 6524904104 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 100673824014 # Time in different power states -system.physmem_1.actEnergy 35171640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 18667605 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 90321000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3119298000.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 731861760 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 127236960 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 10304428080 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 3803073120 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 21964091670 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 40194673995 # Total energy per rank (pJ) -system.physmem_1.averagePower 323.261913 # Core power per rank (mW) -system.physmem_1.totalIdleTime 122403387505 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 207240000 # Time in different power states -system.physmem_1.memoryStateTime::REF 1323736000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 89902145500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 9903979079 # Time in different power states -system.physmem_1.memoryStateTime::ACT 406525995 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 22597262926 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 36038003 # Number of BP lookups -system.cpu.branchPred.condPredicted 19334387 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 996297 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17830996 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13933502 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 78.142029 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6950609 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 4465 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2515874 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 2470358 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 45516 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 129389 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 191 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 124340889500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 248681780 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 13212448 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 309769989 # Number of instructions fetch has processed -system.cpu.fetch.Branches 36038003 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23354469 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 231113604 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2018885 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1934 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 92 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 3406 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 82291256 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 35072 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 245340926 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.517468 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.300338 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 84879866 34.60% 34.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 40535888 16.52% 51.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 28014472 11.42% 62.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 91910700 37.46% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 245340926 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.144916 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.245648 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 27542743 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 94606230 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 97234991 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 25081957 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 875005 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 12946400 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 134756 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 348426325 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3406644 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 875005 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 44284460 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38724844 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 289442 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 104535895 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 56631280 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 344535849 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1483850 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 7863336 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 96546 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 8390481 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 28393613 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 3430855 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 394784790 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2217316444 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 335868704 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 192847846 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 372230048 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22554742 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 11609 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11576 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 59430212 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 89918066 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 84391902 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2366315 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1969070 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 343213178 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22626 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 339325700 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 951900 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 15424204 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 36793818 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 506 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 245340926 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.383078 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.139070 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 64299867 26.21% 26.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 77319752 31.52% 57.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 59651654 24.31% 82.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 34378652 14.01% 96.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 8900677 3.63% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 777968 0.32% 99.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 12356 0.01% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 245340926 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8768859 6.80% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 7313 0.01% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 162373 0.13% 6.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 163818 0.13% 7.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 81957 0.06% 7.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 59658 0.05% 7.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 818593 0.63% 7.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 313085 0.24% 8.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 382100 0.30% 8.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 27482783 21.31% 29.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 41323323 32.04% 61.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 30643180 23.76% 85.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 18783688 14.56% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 108181018 31.88% 31.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2148109 0.63% 32.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 32.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 32.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6799471 2.00% 34.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8597209 2.53% 37.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3207374 0.95% 38.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1592649 0.47% 38.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20858202 6.15% 44.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7175067 2.11% 46.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7140627 2.10% 48.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175298 0.05% 48.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 46505269 13.71% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 55942906 16.49% 79.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 43451689 12.81% 91.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 27550812 8.12% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 339325700 # Type of FU issued -system.cpu.iq.rate 1.364498 # Inst issue rate -system.cpu.iq.fu_busy_cnt 128990730 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.380138 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 765966009 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 235211704 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 219112487 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 287968947 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 123463225 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 116939299 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 298793937 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 169522493 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5585313 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4185791 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7155 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14925 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2016285 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 158671 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 539433 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 875005 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1351770 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1745589 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 343237205 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 89918066 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 84391902 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 11593 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6365 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1739416 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14925 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 447604 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 457294 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 904898 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 337307001 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 89393919 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2018699 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1401 # number of nop insts executed -system.cpu.iew.exec_refs 172494904 # number of memory reference insts executed -system.cpu.iew.exec_branches 31547244 # Number of branches executed -system.cpu.iew.exec_stores 83100985 # Number of stores executed -system.cpu.iew.exec_rate 1.356380 # Inst execution rate -system.cpu.iew.wb_sent 336195874 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 336051786 # cumulative count of insts written-back -system.cpu.iew.wb_producers 153071265 # num instructions producing a value -system.cpu.iew.wb_consumers 267284033 # num instructions consuming a value -system.cpu.iew.wb_rate 1.351333 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.572691 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 14115058 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 861860 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 243135580 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.348269 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.043603 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 113362923 46.63% 46.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 66036162 27.16% 73.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 21343595 8.78% 82.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 13169605 5.42% 87.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8174730 3.36% 91.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4365960 1.80% 93.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2981752 1.23% 94.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2446011 1.01% 95.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 11254842 4.63% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 243135580 # Number of insts commited each cycle -system.cpu.commit.committedInsts 273037830 # Number of instructions committed -system.cpu.commit.committedOps 327812212 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 168107892 # Number of memory references committed -system.cpu.commit.loads 85732275 # Number of loads committed -system.cpu.commit.membars 11033 # Number of memory barriers committed -system.cpu.commit.branches 30563525 # Number of branches committed -system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. -system.cpu.commit.int_insts 258331703 # Number of committed integer instructions. -system.cpu.commit.function_calls 6225114 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 104312485 31.82% 31.82% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2145917 0.65% 32.48% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 32.48% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 32.48% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 32.48% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 32.48% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 32.48% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 32.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 32.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 32.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 32.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 32.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 32.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 32.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 32.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 32.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 32.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 32.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 32.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 6594343 2.01% 34.49% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 34.49% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 7943502 2.42% 36.91% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 3118180 0.95% 37.86% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 1563217 0.48% 38.34% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 19652356 6.00% 44.33% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 44185201 13.48% 62.20% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 55008399 16.78% 78.98% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 41547074 12.67% 91.65% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 27367218 8.35% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 327812212 # Class of committed instruction -system.cpu.commit.bw_lim_events 11254842 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 573805485 # The number of ROB reads -system.cpu.rob.rob_writes 686062388 # The number of ROB writes -system.cpu.timesIdled 39277 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3340854 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 273037218 # Number of Instructions Simulated -system.cpu.committedOps 327811600 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.910798 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.910798 # CPI: Total CPI of All Threads -system.cpu.ipc 1.097938 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.097938 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 325088854 # number of integer regfile reads -system.cpu.int_regfile_writes 134066659 # number of integer regfile writes -system.cpu.fp_regfile_reads 186464530 # number of floating regfile reads -system.cpu.fp_regfile_writes 131741747 # number of floating regfile writes -system.cpu.cc_regfile_reads 1279144313 # number of cc regfile reads -system.cpu.cc_regfile_writes 80001955 # number of cc regfile writes -system.cpu.misc_regfile_reads 1055862294 # number of misc regfile reads -system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1544317 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.844251 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 161914838 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1544829 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 104.810848 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 91273000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.844251 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999696 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999696 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 333130269 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 333130269 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 80902071 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 80902071 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 80921196 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 80921196 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 69698 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 69698 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 10906 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10906 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 161823267 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 161823267 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 161892965 # number of overall hits -system.cpu.dcache.overall_hits::total 161892965 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2746434 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2746434 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1131503 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1131503 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 13 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 13 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3877937 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3877937 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3877950 # number of overall misses -system.cpu.dcache.overall_misses::total 3877950 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 47498967000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 47498967000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9188860405 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9188860405 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 194000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 194000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 56687827405 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 56687827405 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 56687827405 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 56687827405 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 83648505 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 83648505 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 69711 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 69711 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10910 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 10910 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 165701204 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 165701204 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 165770915 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 165770915 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032833 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.032833 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013790 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013790 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000186 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.000186 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000367 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000367 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023403 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023403 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023393 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023393 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17294.778247 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17294.778247 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8120.933312 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 8120.933312 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 48500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 48500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14618.037221 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14618.037221 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14617.988217 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14617.988217 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1101938 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 136754 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 8.057812 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 1544317 # number of writebacks -system.cpu.dcache.writebacks::total 1544317 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1422290 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1422290 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 910806 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 910806 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2333096 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2333096 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2333096 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2333096 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1324144 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1324144 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220697 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 220697 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 7 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 7 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1544841 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1544841 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1544848 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1544848 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27090401500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 27090401500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1844259187 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1844259187 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 932500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 932500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28934660687 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28934660687 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28935593187 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28935593187 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015830 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015830 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002690 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002690 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000100 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000100 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009323 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.009323 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009319 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.009319 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20458.803197 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20458.803197 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8356.521326 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8356.521326 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 133214.285714 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 133214.285714 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18729.863259 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18729.863259 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18730.382010 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18730.382010 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 727442 # number of replacements -system.cpu.icache.tags.tagsinuse 511.812488 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 81555981 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 727954 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 112.034526 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 348938500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.812488 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999634 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999634 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 162 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 98 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 67 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 165310431 # Number of tag accesses -system.cpu.icache.tags.data_accesses 165310431 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 81555981 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 81555981 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 81555981 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 81555981 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 81555981 # number of overall hits -system.cpu.icache.overall_hits::total 81555981 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 735249 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 735249 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 735249 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 735249 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 735249 # number of overall misses -system.cpu.icache.overall_misses::total 735249 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 8470113937 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 8470113937 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 8470113937 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 8470113937 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 8470113937 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 8470113937 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 82291230 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 82291230 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 82291230 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 82291230 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 82291230 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 82291230 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008935 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.008935 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.008935 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.008935 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.008935 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.008935 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11520.061825 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 11520.061825 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 11520.061825 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 11520.061825 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 11520.061825 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 11520.061825 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 144128 # number of cycles access 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(read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 7937418446 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 7937418446 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 7937418446 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008846 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008846 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008846 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.008846 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008846 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.008846 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10903.466680 # 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-system.cpu.l2cache.tags.age_task_id_blocks_1022::4 101 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 547 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 740 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 550 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4130 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.011292 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.374023 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 70659625 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 70659625 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states 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-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.040682 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.148187 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.113756 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 2388.888889 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 2388.888889 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88855.696203 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88855.696203 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89770.785492 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89770.785492 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78657.032709 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78657.032709 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89770.785492 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78692.227552 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 79961.135006 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89770.785492 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78692.227552 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 79961.135006 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of 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number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 91 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 102 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 54077 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 54077 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 18 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 18 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 735 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 735 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 29601 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 29601 # number of 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-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2480103000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16637653500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19117756500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2480103000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16637653500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 203156315 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19320912815 # number of overall MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.947368 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.947368 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003330 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003330 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.040667 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040667 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.172262 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.172262 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.040667 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148128 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.113711 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.040667 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148128 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.137505 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3756.797067 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3756.797067 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15500 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15500 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 87304.761905 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 87304.761905 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 83784.432958 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 83784.432958 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72659.490658 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72659.490658 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 83784.432958 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72706.530527 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73975.392170 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 83784.432958 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72706.530527 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3756.797067 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61824.744777 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4544579 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2271779 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254895 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 51433 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 51432 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 2052102 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 968794 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1302965 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 55467 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 19 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 19 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 220698 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 220698 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 727972 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1324131 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2183308 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4634013 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6817321 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93141504 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197705344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 290846848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 55544 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4928 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2328287 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.131576 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.338031 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2021941 86.84% 86.84% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 306345 13.16% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2328287 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4544048500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 3.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1092026360 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2317274956 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 261096 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 253777 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 260342 # Transaction distribution -system.membus.trans_dist::UpgradeReq 18 # Transaction distribution -system.membus.trans_dist::ReadExReq 735 # Transaction distribution -system.membus.trans_dist::ReadExResp 735 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 260343 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 522173 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 522173 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16708928 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 16708928 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 261096 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 261096 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 261096 # Request fanout histogram -system.membus.reqLayer0.occupancy 316188421 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1389693354 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.1 # Layer utilization (%) +sim_seconds 0.124341 +sim_ticks 124340889500 +final_tick 124340889500 +sim_freq 1000000000000 +host_inst_rate 97563 +host_op_rate 117136 +host_tick_rate 44430232 +host_mem_usage 304636 +host_seconds 2798.57 +sim_insts 273037218 +sim_ops 327811600 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 124340889500 +system.physmem.bytes_read::cpu.inst 1894400 +system.physmem.bytes_read::cpu.data 14645312 +system.physmem.bytes_read::cpu.l2cache.prefetcher 169216 +system.physmem.bytes_read::total 16708928 +system.physmem.bytes_inst_read::cpu.inst 1894400 +system.physmem.bytes_inst_read::total 1894400 +system.physmem.num_reads::cpu.inst 29600 +system.physmem.num_reads::cpu.data 228833 +system.physmem.num_reads::cpu.l2cache.prefetcher 2644 +system.physmem.num_reads::total 261077 +system.physmem.bw_read::cpu.inst 15235535 +system.physmem.bw_read::cpu.data 117783555 +system.physmem.bw_read::cpu.l2cache.prefetcher 1360904 +system.physmem.bw_read::total 134379994 +system.physmem.bw_inst_read::cpu.inst 15235535 +system.physmem.bw_inst_read::total 15235535 +system.physmem.bw_total::cpu.inst 15235535 +system.physmem.bw_total::cpu.data 117783555 +system.physmem.bw_total::cpu.l2cache.prefetcher 1360904 +system.physmem.bw_total::total 134379994 +system.physmem.readReqs 261078 +system.physmem.writeReqs 0 +system.physmem.readBursts 261078 +system.physmem.writeBursts 0 +system.physmem.bytesReadDRAM 16708992 +system.physmem.bytesReadWrQ 0 +system.physmem.bytesWritten 0 +system.physmem.bytesReadSys 16708992 +system.physmem.bytesWrittenSys 0 +system.physmem.servicedByWrQ 0 +system.physmem.mergedWrBursts 0 +system.physmem.neitherReadNorWriteReqs 0 +system.physmem.perBankRdBursts::0 1259 +system.physmem.perBankRdBursts::1 69989 +system.physmem.perBankRdBursts::2 1294 +system.physmem.perBankRdBursts::3 10805 +system.physmem.perBankRdBursts::4 42847 +system.physmem.perBankRdBursts::5 121814 +system.physmem.perBankRdBursts::6 160 +system.physmem.perBankRdBursts::7 259 +system.physmem.perBankRdBursts::8 225 +system.physmem.perBankRdBursts::9 562 +system.physmem.perBankRdBursts::10 7823 +system.physmem.perBankRdBursts::11 812 +system.physmem.perBankRdBursts::12 1216 +system.physmem.perBankRdBursts::13 747 +system.physmem.perBankRdBursts::14 656 +system.physmem.perBankRdBursts::15 610 +system.physmem.perBankWrBursts::0 0 +system.physmem.perBankWrBursts::1 0 +system.physmem.perBankWrBursts::2 0 +system.physmem.perBankWrBursts::3 0 +system.physmem.perBankWrBursts::4 0 +system.physmem.perBankWrBursts::5 0 +system.physmem.perBankWrBursts::6 0 +system.physmem.perBankWrBursts::7 0 +system.physmem.perBankWrBursts::8 0 +system.physmem.perBankWrBursts::9 0 +system.physmem.perBankWrBursts::10 0 +system.physmem.perBankWrBursts::11 0 +system.physmem.perBankWrBursts::12 0 +system.physmem.perBankWrBursts::13 0 +system.physmem.perBankWrBursts::14 0 +system.physmem.perBankWrBursts::15 0 +system.physmem.numRdRetry 0 +system.physmem.numWrRetry 0 +system.physmem.totGap 124340880000 +system.physmem.readPktSize::0 0 +system.physmem.readPktSize::1 0 +system.physmem.readPktSize::2 0 +system.physmem.readPktSize::3 0 +system.physmem.readPktSize::4 0 +system.physmem.readPktSize::5 0 +system.physmem.readPktSize::6 261078 +system.physmem.writePktSize::0 0 +system.physmem.writePktSize::1 0 +system.physmem.writePktSize::2 0 +system.physmem.writePktSize::3 0 +system.physmem.writePktSize::4 0 +system.physmem.writePktSize::5 0 +system.physmem.writePktSize::6 0 +system.physmem.rdQLenPdf::0 204158 +system.physmem.rdQLenPdf::1 43358 +system.physmem.rdQLenPdf::2 12121 +system.physmem.rdQLenPdf::3 308 +system.physmem.rdQLenPdf::4 247 +system.physmem.rdQLenPdf::5 209 +system.physmem.rdQLenPdf::6 181 +system.physmem.rdQLenPdf::7 231 +system.physmem.rdQLenPdf::8 123 +system.physmem.rdQLenPdf::9 61 +system.physmem.rdQLenPdf::10 27 +system.physmem.rdQLenPdf::11 20 +system.physmem.rdQLenPdf::12 17 +system.physmem.rdQLenPdf::13 17 +system.physmem.rdQLenPdf::14 0 +system.physmem.rdQLenPdf::15 0 +system.physmem.rdQLenPdf::16 0 +system.physmem.rdQLenPdf::17 0 +system.physmem.rdQLenPdf::18 0 +system.physmem.rdQLenPdf::19 0 +system.physmem.rdQLenPdf::20 0 +system.physmem.rdQLenPdf::21 0 +system.physmem.rdQLenPdf::22 0 +system.physmem.rdQLenPdf::23 0 +system.physmem.rdQLenPdf::24 0 +system.physmem.rdQLenPdf::25 0 +system.physmem.rdQLenPdf::26 0 +system.physmem.rdQLenPdf::27 0 +system.physmem.rdQLenPdf::28 0 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+system.physmem.wrQLenPdf::59 0 +system.physmem.wrQLenPdf::60 0 +system.physmem.wrQLenPdf::61 0 +system.physmem.wrQLenPdf::62 0 +system.physmem.wrQLenPdf::63 0 +system.physmem.bytesPerActivate::samples 67983 +system.physmem.bytesPerActivate::mean 245.745201 +system.physmem.bytesPerActivate::gmean 180.705876 +system.physmem.bytesPerActivate::stdev 200.483366 +system.physmem.bytesPerActivate::0-127 18259 26.86% 26.86% +system.physmem.bytesPerActivate::128-255 22263 32.75% 59.61% +system.physmem.bytesPerActivate::256-383 11383 16.74% 76.35% +system.physmem.bytesPerActivate::384-511 6868 10.10% 86.45% +system.physmem.bytesPerActivate::512-639 4760 7.00% 93.45% +system.physmem.bytesPerActivate::640-767 2080 3.06% 96.51% +system.physmem.bytesPerActivate::768-895 1310 1.93% 98.44% +system.physmem.bytesPerActivate::896-1023 394 0.58% 99.02% +system.physmem.bytesPerActivate::1024-1151 666 0.98% 100.00% +system.physmem.bytesPerActivate::total 67983 +system.physmem.totQLat 4612072505 +system.physmem.totMemAccLat 9507285005 +system.physmem.totBusLat 1305390000 +system.physmem.avgQLat 17665.50 +system.physmem.avgBusLat 5000.00 +system.physmem.avgMemAccLat 36415.50 +system.physmem.avgRdBW 134.38 +system.physmem.avgWrBW 0.00 +system.physmem.avgRdBWSys 134.38 +system.physmem.avgWrBWSys 0.00 +system.physmem.peakBW 12800.00 +system.physmem.busUtil 1.05 +system.physmem.busUtilRead 1.05 +system.physmem.busUtilWrite 0.00 +system.physmem.avgRdQLen 1.60 +system.physmem.avgWrQLen 0.00 +system.physmem.readRowHits 193085 +system.physmem.writeRowHits 0 +system.physmem.readRowHitRate 73.96 +system.physmem.writeRowHitRate nan +system.physmem.avgGap 476259.51 +system.physmem.pageHitRate 73.96 +system.physmem_0.actEnergy 450291240 +system.physmem_0.preEnergy 239324085 +system.physmem_0.readEnergy 1773768780 +system.physmem_0.writeEnergy 0 +system.physmem_0.refreshEnergy 9681809280.000002 +system.physmem_0.actBackEnergy 4644193560 +system.physmem_0.preBackEnergy 227236800 +system.physmem_0.actPowerDownEnergy 45907805700 +system.physmem_0.prePowerDownEnergy 3604922400 +system.physmem_0.selfRefreshEnergy 978458700 +system.physmem_0.totalEnergy 67507810545 +system.physmem_0.averagePower 542.925264 +system.physmem_0.totalIdleTime 113563299646 +system.physmem_0.memoryStateTime::IDLE 155533000 +system.physmem_0.memoryStateTime::REF 4097020000 +system.physmem_0.memoryStateTime::SREF 3501663750 +system.physmem_0.memoryStateTime::PRE_PDN 9387944632 +system.physmem_0.memoryStateTime::ACT 6524904104 +system.physmem_0.memoryStateTime::ACT_PDN 100673824014 +system.physmem_1.actEnergy 35171640 +system.physmem_1.preEnergy 18667605 +system.physmem_1.readEnergy 90321000 +system.physmem_1.writeEnergy 0 +system.physmem_1.refreshEnergy 3119298000.000000 +system.physmem_1.actBackEnergy 731861760 +system.physmem_1.preBackEnergy 127236960 +system.physmem_1.actPowerDownEnergy 10304428080 +system.physmem_1.prePowerDownEnergy 3803073120 +system.physmem_1.selfRefreshEnergy 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261096 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 261096 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 261096 +system.membus.reqLayer0.occupancy 316188421 +system.membus.reqLayer0.utilization 0.3 +system.membus.respLayer1.occupancy 1389693354 +system.membus.respLayer1.utilization 1.1 ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini index 1b5061343..89604511e 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini @@ -90,6 +90,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -165,8 +166,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -177,8 +176,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -239,7 +236,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic drivers= @@ -248,14 +245,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/eon +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/eon gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -279,6 +277,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -290,7 +289,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -298,6 +297,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -306,6 +312,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -313,7 +320,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simerr b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simerr index c881283f7..a91025695 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simerr +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simerr @@ -1,10 +1,13 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. getting pixel output filename pixels_out.cook opening control file chair.control.cook opening camera file chair.camera opening surfaces file chair.surfaces reading data +info: Increasing stack size by one page. processing 8parts Grid measure is 6 by 3.0001 by 6 cell dimension is 0.863065 @@ -31,6 +34,8 @@ col 12. . . col 13. . . col 14. . . Writing to chair.cook.ppm +info: Increasing stack size by one page. +info: Increasing stack size by one page. 0 8 14 1 8 14 2 8 14 diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout index 154af3aae..728509d4f 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout @@ -3,17 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:54:12 -gem5 executing on e108600-lin, pid 23918 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/arm/linux/simple-atomic +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 17:56:13 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54231 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/30.eon/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. Eon, Version 1.1 -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. OO-style eon Time= 0.200000 -Exiting @ tick 201717314000 because target called exit() +Exiting @ tick 201717314000 because exiting with last active thread context diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt index 5ec20d23b..2e5c48f3e 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -1,262 +1,262 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.201717 # Number of seconds simulated -sim_ticks 201717314000 # Number of ticks simulated -final_tick 201717314000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1476968 # Simulator instruction rate (inst/s) -host_op_rate 1773264 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1091168515 # Simulator tick rate (ticks/s) -host_mem_usage 268416 # Number of bytes of host memory used -host_seconds 184.86 # Real time elapsed on the host -sim_insts 273037595 # Number of instructions simulated -sim_ops 327811950 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 1394641096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 480709216 # Number of bytes read from this memory -system.physmem.bytes_read::total 1875350312 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1394641096 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1394641096 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 400047763 # Number of bytes written to this memory -system.physmem.bytes_written::total 400047763 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 348660274 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 86300511 # Number of read requests responded to by this memory -system.physmem.num_reads::total 434960785 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 82063567 # Number of write requests responded to by this memory -system.physmem.num_writes::total 82063567 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 6913839315 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2383083566 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9296922881 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6913839315 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6913839315 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1983209845 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1983209845 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6913839315 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4366293411 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11280132726 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 191 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 201717314000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 403434629 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 273037595 # Number of instructions committed -system.cpu.committedOps 327811950 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 258331481 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses -system.cpu.num_func_calls 12448615 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15799338 # number of instructions that are conditional controls -system.cpu.num_int_insts 258331481 # number of integer instructions -system.cpu.num_fp_insts 114216705 # number of float instructions -system.cpu.num_int_register_reads 938030601 # number of times the integer registers were read -system.cpu.num_int_register_writes 162499657 # number of times the integer registers were written -system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read -system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written -system.cpu.num_cc_register_reads 985884626 # number of times the CC registers were read -system.cpu.num_cc_register_writes 76361749 # number of times the CC registers were written -system.cpu.num_mem_refs 168107829 # number of memory refs -system.cpu.num_load_insts 85732235 # Number of load instructions -system.cpu.num_store_insts 82375594 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 403434628.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 30563491 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 104312493 31.82% 31.82% # Class of executed instruction -system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 32.48% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 32.48% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 32.48% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 32.48% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 32.48% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 32.48% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 32.48% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 32.48% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 32.48% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 32.48% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 32.48% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 32.48% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 6594343 2.01% 34.49% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction -system.cpu.op_class::MemRead 44185161 13.48% 62.20% # Class of executed instruction -system.cpu.op_class::MemWrite 55008376 16.78% 78.98% # Class of executed instruction -system.cpu.op_class::FloatMemRead 41547074 12.67% 91.65% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 27367218 8.35% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 327812145 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 434895828 # Transaction distribution -system.membus.trans_dist::ReadResp 434906723 # Transaction distribution -system.membus.trans_dist::WriteReq 82052672 # Transaction distribution -system.membus.trans_dist::WriteResp 82052672 # Transaction distribution -system.membus.trans_dist::SoftPFReq 54062 # Transaction distribution -system.membus.trans_dist::SoftPFResp 54062 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 10895 # Transaction distribution -system.membus.trans_dist::StoreCondReq 10895 # Transaction distribution -system.membus.trans_dist::StoreCondResp 10895 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 697320548 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 336728156 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1034048704 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1394641096 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 880756979 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 2275398075 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 517024352 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 517024352 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 517024352 # Request fanout histogram +sim_seconds 0.201717 +sim_ticks 201717314000 +final_tick 201717314000 +sim_freq 1000000000000 +host_inst_rate 634159 +host_op_rate 761378 +host_tick_rate 468510100 +host_mem_usage 279924 +host_seconds 430.55 +sim_insts 273037595 +sim_ops 327811950 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 201717314000 +system.physmem.bytes_read::cpu.inst 1394641096 +system.physmem.bytes_read::cpu.data 480709216 +system.physmem.bytes_read::total 1875350312 +system.physmem.bytes_inst_read::cpu.inst 1394641096 +system.physmem.bytes_inst_read::total 1394641096 +system.physmem.bytes_written::cpu.data 400047763 +system.physmem.bytes_written::total 400047763 +system.physmem.num_reads::cpu.inst 348660274 +system.physmem.num_reads::cpu.data 86300511 +system.physmem.num_reads::total 434960785 +system.physmem.num_writes::cpu.data 82063567 +system.physmem.num_writes::total 82063567 +system.physmem.bw_read::cpu.inst 6913839315 +system.physmem.bw_read::cpu.data 2383083566 +system.physmem.bw_read::total 9296922881 +system.physmem.bw_inst_read::cpu.inst 6913839315 +system.physmem.bw_inst_read::total 6913839315 +system.physmem.bw_write::cpu.data 1983209845 +system.physmem.bw_write::total 1983209845 +system.physmem.bw_total::cpu.inst 6913839315 +system.physmem.bw_total::cpu.data 4366293411 +system.physmem.bw_total::total 11280132726 +system.pwrStateResidencyTicks::UNDEFINED 201717314000 +system.cpu_clk_domain.clock 500 +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000 +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.hits 0 +system.cpu.dstage2_mmu.stage2_tlb.misses 0 +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000 +system.cpu.dtb.walker.walks 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dtb.walker.walkRequestOrigin::total 0 +system.cpu.dtb.inst_hits 0 +system.cpu.dtb.inst_misses 0 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.flush_tlb 0 +system.cpu.dtb.flush_tlb_mva 0 +system.cpu.dtb.flush_tlb_mva_asid 0 +system.cpu.dtb.flush_tlb_asid 0 +system.cpu.dtb.flush_entries 0 +system.cpu.dtb.align_faults 0 +system.cpu.dtb.prefetch_faults 0 +system.cpu.dtb.domain_faults 0 +system.cpu.dtb.perms_faults 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.inst_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000 +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.hits 0 +system.cpu.istage2_mmu.stage2_tlb.misses 0 +system.cpu.istage2_mmu.stage2_tlb.accesses 0 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000 +system.cpu.itb.walker.walks 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.itb.walker.walkRequestOrigin::total 0 +system.cpu.itb.inst_hits 0 +system.cpu.itb.inst_misses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.flush_tlb 0 +system.cpu.itb.flush_tlb_mva 0 +system.cpu.itb.flush_tlb_mva_asid 0 +system.cpu.itb.flush_tlb_asid 0 +system.cpu.itb.flush_entries 0 +system.cpu.itb.align_faults 0 +system.cpu.itb.prefetch_faults 0 +system.cpu.itb.domain_faults 0 +system.cpu.itb.perms_faults 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.inst_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 191 +system.cpu.pwrStateResidencyTicks::ON 201717314000 +system.cpu.numCycles 403434629 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 273037595 +system.cpu.committedOps 327811950 +system.cpu.num_int_alu_accesses 258331481 +system.cpu.num_fp_alu_accesses 114216705 +system.cpu.num_func_calls 12448615 +system.cpu.num_conditional_control_insts 15799338 +system.cpu.num_int_insts 258331481 +system.cpu.num_fp_insts 114216705 +system.cpu.num_int_register_reads 938030601 +system.cpu.num_int_register_writes 162499657 +system.cpu.num_fp_register_reads 180262959 +system.cpu.num_fp_register_writes 126152315 +system.cpu.num_cc_register_reads 985884626 +system.cpu.num_cc_register_writes 76361749 +system.cpu.num_mem_refs 168107829 +system.cpu.num_load_insts 85732235 +system.cpu.num_store_insts 82375594 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 403434629 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 30563491 +system.cpu.op_class::No_OpClass 0 0.00% 0.00% +system.cpu.op_class::IntAlu 104312493 31.82% 31.82% +system.cpu.op_class::IntMult 2145905 0.65% 32.48% +system.cpu.op_class::IntDiv 0 0.00% 32.48% +system.cpu.op_class::FloatAdd 0 0.00% 32.48% +system.cpu.op_class::FloatCmp 0 0.00% 32.48% +system.cpu.op_class::FloatCvt 0 0.00% 32.48% +system.cpu.op_class::FloatMult 0 0.00% 32.48% +system.cpu.op_class::FloatMultAcc 0 0.00% 32.48% +system.cpu.op_class::FloatDiv 0 0.00% 32.48% +system.cpu.op_class::FloatMisc 0 0.00% 32.48% +system.cpu.op_class::FloatSqrt 0 0.00% 32.48% +system.cpu.op_class::SimdAdd 0 0.00% 32.48% +system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% +system.cpu.op_class::SimdAlu 0 0.00% 32.48% +system.cpu.op_class::SimdCmp 0 0.00% 32.48% +system.cpu.op_class::SimdCvt 0 0.00% 32.48% +system.cpu.op_class::SimdMisc 0 0.00% 32.48% +system.cpu.op_class::SimdMult 0 0.00% 32.48% +system.cpu.op_class::SimdMultAcc 0 0.00% 32.48% +system.cpu.op_class::SimdShift 0 0.00% 32.48% +system.cpu.op_class::SimdShiftAcc 0 0.00% 32.48% +system.cpu.op_class::SimdSqrt 0 0.00% 32.48% +system.cpu.op_class::SimdFloatAdd 6594343 2.01% 34.49% +system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% +system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% +system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% +system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% +system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% +system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% +system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% +system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% +system.cpu.op_class::MemRead 44185161 13.48% 62.20% +system.cpu.op_class::MemWrite 55008376 16.78% 78.98% +system.cpu.op_class::FloatMemRead 41547074 12.67% 91.65% +system.cpu.op_class::FloatMemWrite 27367218 8.35% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 327812145 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 201717314000 +system.membus.trans_dist::ReadReq 434895828 +system.membus.trans_dist::ReadResp 434906723 +system.membus.trans_dist::WriteReq 82052672 +system.membus.trans_dist::WriteResp 82052672 +system.membus.trans_dist::SoftPFReq 54062 +system.membus.trans_dist::SoftPFResp 54062 +system.membus.trans_dist::LoadLockedReq 10895 +system.membus.trans_dist::StoreCondReq 10895 +system.membus.trans_dist::StoreCondResp 10895 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 697320548 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 336728156 +system.membus.pkt_count::total 1034048704 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1394641096 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 880756979 +system.membus.pkt_size::total 2275398075 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 517024352 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 517024352 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 517024352 ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini index 0faba130d..e57f29bfa 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini @@ -87,6 +87,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -96,14 +97,14 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -117,6 +118,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -129,15 +131,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dstage2_mmu] type=ArmStage2MMU @@ -193,14 +196,14 @@ port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -214,6 +217,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -226,15 +230,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=ArmInterrupts @@ -253,8 +258,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -265,8 +268,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -325,14 +326,14 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -346,6 +347,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -358,15 +360,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -402,7 +405,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing drivers= @@ -411,14 +414,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/eon +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/eon gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -442,6 +446,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -453,7 +458,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -461,6 +466,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -469,6 +481,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -476,7 +489,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr index c881283f7..a91025695 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr @@ -1,10 +1,13 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. getting pixel output filename pixels_out.cook opening control file chair.control.cook opening camera file chair.camera opening surfaces file chair.surfaces reading data +info: Increasing stack size by one page. processing 8parts Grid measure is 6 by 3.0001 by 6 cell dimension is 0.863065 @@ -31,6 +34,8 @@ col 12. . . col 13. . . col 14. . . Writing to chair.cook.ppm +info: Increasing stack size by one page. +info: Increasing stack size by one page. 0 8 14 1 8 14 2 8 14 diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout index bd192fb8a..7aa5c7a76 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout @@ -3,17 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 15:00:59 -gem5 executing on e108600-lin, pid 24143 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/arm/linux/simple-timing +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 17:56:13 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54216 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/30.eon/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. Eon, Version 1.1 -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. OO-style eon Time= 0.510000 -Exiting @ tick 517291025500 because target called exit() +Exiting @ tick 517297855500 because exiting with last active thread context diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index 9e7563574..c9e238fff 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -1,675 +1,675 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.517298 # Number of seconds simulated -sim_ticks 517297855500 # Number of ticks simulated -final_tick 517297855500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1075622 # Simulator instruction rate (inst/s) -host_op_rate 1291325 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2040106124 # Simulator tick rate (ticks/s) -host_mem_usage 278152 # Number of bytes of host memory used -host_seconds 253.56 # Real time elapsed on the host -sim_insts 272739286 # Number of instructions simulated -sim_ops 327433744 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 166912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 270336 # Number of bytes read from this memory -system.physmem.bytes_read::total 437248 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 166912 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 166912 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2608 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4224 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 322661 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 522593 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 845254 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 322661 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 322661 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 322661 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 522593 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 845254 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 191 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 517297855500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1034595711 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 272739286 # Number of instructions committed -system.cpu.committedOps 327433744 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 258331537 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses -system.cpu.num_func_calls 12448615 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15799349 # number of instructions that are conditional controls -system.cpu.num_int_insts 258331537 # number of integer instructions -system.cpu.num_fp_insts 114216705 # number of float instructions -system.cpu.num_int_register_reads 979511506 # number of times the integer registers were read -system.cpu.num_int_register_writes 162499693 # number of times the integer registers were written -system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read -system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written -system.cpu.num_cc_register_reads 1242915503 # number of times the CC registers were read -system.cpu.num_cc_register_writes 76361814 # number of times the CC registers were written -system.cpu.num_mem_refs 168107847 # number of memory refs -system.cpu.num_load_insts 85732248 # Number of load instructions -system.cpu.num_store_insts 82375599 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1034595710.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 30563503 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 104312544 31.82% 31.82% # Class of executed instruction -system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 32.48% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 32.48% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 32.48% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 32.48% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 32.48% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 32.48% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 32.48% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 32.48% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 32.48% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 32.48% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 32.48% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 32.48% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 6594343 2.01% 34.49% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction -system.cpu.op_class::MemRead 44185174 13.48% 62.20% # Class of executed instruction -system.cpu.op_class::MemWrite 55008381 16.78% 78.98% # Class of executed instruction -system.cpu.op_class::FloatMemRead 41547074 12.67% 91.65% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 27367218 8.35% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 327812214 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1332 # number of replacements -system.cpu.dcache.tags.tagsinuse 3078.320204 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3078.320204 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.751543 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.751543 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168283768 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168283768 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168337827 # number of overall hits -system.cpu.dcache.overall_hits::total 168337827 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1604 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1604 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 4476 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses -system.cpu.dcache.overall_misses::total 4479 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 89418000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 89418000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 180278500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 180278500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 269696500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 269696500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 269696500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 269696500 # number of overall miss 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60213.552132 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 998 # number of writebacks -system.cpu.dcache.writebacks::total 998 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1 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percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.862275 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 697336309 # Number of tag accesses -system.cpu.icache.tags.data_accesses 697336309 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states 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341054000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 341054000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 341054000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 341054000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 341054000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 341054000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 348660353 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 348660353 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 348660353 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 348660353 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 348660353 # number of overall (read+write) accesses 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-system.cpu.icache.overall_avg_miss_latency::cpu.inst 21858.232391 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21858.232391 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 13796 # number of writebacks -system.cpu.icache.writebacks::total 13796 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15603 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15603 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 325451000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 325451000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 325451000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 325451000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 325451000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 325451000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20858.232391 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20858.232391 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20858.232391 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20858.232391 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20858.232391 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20858.232391 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 5901.352793 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 20712 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 6832 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 3.031616 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.314356 # Average occupied blocks per requestor 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-system.cpu.l2cache.tags.tag_accesses 227184 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 227184 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 998 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 998 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 6212 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 6212 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12995 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 12995 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 238 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 238 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 12995 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 254 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 13249 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 12995 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 254 # number of overall hits -system.cpu.l2cache.overall_hits::total 13249 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 2856 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 2856 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2608 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2608 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1368 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 1368 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2608 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 4224 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 6832 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2608 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 4224 # number of overall misses -system.cpu.l2cache.overall_misses::total 6832 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 172926500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 172926500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 157900000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 157900000 # number of ReadCleanReq miss cycles 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accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 6212 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 6212 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2872 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2872 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15603 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 15603 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1606 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1606 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 15603 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 4478 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 20081 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 15603 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 4478 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 20081 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994429 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.994429 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.167147 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.167147 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.851806 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.851806 # miss rate for ReadSharedReq accesses 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-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2608 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2608 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1368 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1368 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2608 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 4224 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 6832 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2608 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 4224 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 144366500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 144366500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 131820000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 131820000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 69279000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 69279000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 131820000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 213645500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 345465500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 131820000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 213645500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 345465500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses 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50565.793326 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50544.478528 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50578.953598 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50565.793326 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 35209 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 15221 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7665 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 998 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 13796 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 334 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 15603 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1606 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45002 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10288 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 55290 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1881536 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2232000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 20081 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.386335 # Request fanout histogram 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(%) -system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 6833 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in 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+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7665 +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 517297855500 +system.cpu.toL2Bus.trans_dist::ReadResp 17209 +system.cpu.toL2Bus.trans_dist::WritebackDirty 998 +system.cpu.toL2Bus.trans_dist::WritebackClean 13796 +system.cpu.toL2Bus.trans_dist::CleanEvict 334 +system.cpu.toL2Bus.trans_dist::ReadExReq 2872 +system.cpu.toL2Bus.trans_dist::ReadExResp 2872 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 15603 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1606 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45002 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10288 +system.cpu.toL2Bus.pkt_count::total 55290 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1881536 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 +system.cpu.toL2Bus.pkt_size::total 2232000 +system.cpu.toL2Bus.snoops 0 +system.cpu.toL2Bus.snoopTraffic 0 +system.cpu.toL2Bus.snoop_fanout::samples 20081 +system.cpu.toL2Bus.snoop_fanout::mean 0.386335 +system.cpu.toL2Bus.snoop_fanout::stdev 0.486921 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 12323 61.37% 61.37% +system.cpu.toL2Bus.snoop_fanout::1 7758 38.63% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 1 +system.cpu.toL2Bus.snoop_fanout::total 20081 +system.cpu.toL2Bus.reqLayer0.occupancy 32398500 +system.cpu.toL2Bus.reqLayer0.utilization 0.0 +system.cpu.toL2Bus.respLayer0.occupancy 23404500 +system.cpu.toL2Bus.respLayer0.utilization 0.0 +system.cpu.toL2Bus.respLayer1.occupancy 6717000 +system.cpu.toL2Bus.respLayer1.utilization 0.0 +system.membus.snoop_filter.tot_requests 6833 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 517297855500 +system.membus.trans_dist::ReadResp 3976 +system.membus.trans_dist::ReadExReq 2856 +system.membus.trans_dist::ReadExResp 2856 +system.membus.trans_dist::ReadSharedReq 3976 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 +system.membus.pkt_count::total 13664 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 +system.membus.pkt_size::total 437248 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 6833 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 6833 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 6833 +system.membus.reqLayer0.occupancy 7281500 +system.membus.reqLayer0.utilization 0.0 +system.membus.respLayer1.occupancy 34160000 +system.membus.respLayer1.utilization 0.0 ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini index 5d9ef8c4a..721f1a541 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -817,7 +817,7 @@ executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/li gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout pgid=100 pid=100 diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout index fb1e27e73..6aa244964 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Apr 2 2017 11:48:43 -gem5 started Apr 2 2017 11:49:00 -gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87253 +gem5 compiled Apr 3 2017 04:18:56 +gem5 started Apr 3 2017 04:19:11 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 3566 command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -647,4 +647,4 @@ Global frequency set at 1000000000000 ticks per second 2000: 2845746745 1000: 2068042552 0: 290958364 -Exiting @ tick 339069355000 because target called exit() +Exiting @ tick 339069355000 because exiting with last active thread context diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 48dadbf2b..51dd3b610 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.339069 sim_ticks 339069355000 final_tick 339069355000 sim_freq 1000000000000 -host_inst_rate 200289 -host_op_rate 246583 -host_tick_rate 106004783 -host_mem_usage 288044 -host_seconds 3198.62 +host_inst_rate 210410 +host_op_rate 259043 +host_tick_rate 111361442 +host_mem_usage 288088 +host_seconds 3044.76 sim_insts 640649299 sim_ops 788724958 system.voltage_domain.voltage 1 @@ -458,7 +458,7 @@ system.cpu.fetch.Insts 824295259 system.cpu.fetch.Branches 175312537 system.cpu.fetch.predictedBranches 103250498 system.cpu.fetch.Cycles 638595633 -system.cpu.fetch.SquashCycles 8083491 +system.cpu.fetch.SquashCycles 8083490 system.cpu.fetch.MiscStallCycles 2728 system.cpu.fetch.PendingTrapStallCycles 17 system.cpu.fetch.IcacheWaitRetryStallCycles 3109 @@ -516,7 +516,7 @@ system.cpu.iq.iqInstsAdded 899826395 system.cpu.iq.iqNonSpecInstsAdded 12582 system.cpu.iq.iqInstsIssued 860048195 system.cpu.iq.iqSquashedInstsIssued 9222152 -system.cpu.iq.iqSquashedInstsExamined 111114019 +system.cpu.iq.iqSquashedInstsExamined 111114018 system.cpu.iq.iqSquashedOperandsExamined 244270336 system.cpu.iq.iqSquashedNonSpecRemoved 428 system.cpu.iq.issued_per_cycle::samples 677669366 @@ -617,7 +617,7 @@ system.cpu.iq.rate 1.268248 system.cpu.iq.fu_busy_cnt 277608649 system.cpu.iq.fu_busy_rate 0.322783 system.cpu.iq.int_inst_queue_reads 2621941266 -system.cpu.iq.int_inst_queue_writes 980329396 +system.cpu.iq.int_inst_queue_writes 980329395 system.cpu.iq.int_inst_queue_wakeup_accesses 820105906 system.cpu.iq.fp_inst_queue_reads 62655291 system.cpu.iq.fp_inst_queue_writes 30642249 @@ -735,7 +735,7 @@ system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% system.cpu.commit.op_class_0::total 788730070 system.cpu.commit.bw_lim_events 29951867 system.cpu.rob.rob_reads 1525019812 -system.cpu.rob.rob_writes 1798395927 +system.cpu.rob.rob_writes 1798395926 system.cpu.timesIdled 10540 system.cpu.idleCycles 469345 system.cpu.committedInsts 640649299 diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini index 5997dda79..8d15582fe 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini @@ -90,6 +90,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -165,8 +166,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -177,8 +176,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -239,7 +236,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=perlbmk -I. -I lib mdred.makerand.pl cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic drivers= @@ -248,14 +245,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/perlbmk +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -279,6 +277,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -290,7 +289,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -298,6 +297,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -306,6 +312,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -313,7 +320,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr index 937e051a4..92c744310 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr @@ -1,3 +1,6 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... warn: fcntl64(3, 2) passed through to host +info: Increasing stack size by one page. +info: Increasing stack size by one page. diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout index 74eea3e5b..2146043b6 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout @@ -3,15 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-at gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:51:02 -gem5 executing on e108600-lin, pid 23320 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/arm/linux/simple-atomic +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 17:56:15 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54237 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/40.perlbmk/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -info: Increasing stack size by one page. 637000: 2581848540 636000: 4117852332 635000: 329081094 @@ -650,4 +647,4 @@ info: Increasing stack size by one page. 2000: 2845746745 1000: 2068042552 0: 290958364 -Exiting @ tick 395726778500 because target called exit() +Exiting @ tick 395726778500 because exiting with last active thread context diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index c1630ee45..b1e10c075 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -1,262 +1,262 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.395727 # Number of seconds simulated -sim_ticks 395726778500 # Number of ticks simulated -final_tick 395726778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1825974 # Simulator instruction rate (inst/s) -host_op_rate 2248015 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1127888505 # Simulator tick rate (ticks/s) -host_mem_usage 268260 # Number of bytes of host memory used -host_seconds 350.86 # Real time elapsed on the host -sim_insts 640654411 # Number of instructions simulated -sim_ops 788730070 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 2573511596 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1144718516 # Number of bytes read from this memory -system.physmem.bytes_read::total 3718230112 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 2573511596 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 2573511596 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 523317413 # Number of bytes written to this memory -system.physmem.bytes_written::total 523317413 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 643377899 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 250335238 # Number of read requests responded to by this memory -system.physmem.num_reads::total 893713137 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 128957216 # Number of write requests responded to by this memory -system.physmem.num_writes::total 128957216 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 6503253598 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2892699151 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9395952748 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6503253598 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6503253598 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1322421027 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1322421027 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6503253598 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4215120178 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10718373776 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 673 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 395726778500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 791453558 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 640654411 # Number of instructions committed -system.cpu.committedOps 788730070 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses -system.cpu.num_func_calls 37261296 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 91575866 # number of instructions that are conditional controls -system.cpu.num_int_insts 682251400 # number of integer instructions -system.cpu.num_fp_insts 24239771 # number of float instructions -system.cpu.num_int_register_reads 1268495038 # number of times the integer registers were read -system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written -system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read -system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written -system.cpu.num_cc_register_reads 2369173294 # number of times the CC registers were read -system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written -system.cpu.num_mem_refs 381221435 # number of memory refs -system.cpu.num_load_insts 252240938 # Number of load instructions -system.cpu.num_store_insts 128980497 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 791453557.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 137364860 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 385757467 48.91% 48.91% # Class of executed instruction -system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction -system.cpu.op_class::MemRead 245222568 31.09% 82.76% # Class of executed instruction -system.cpu.op_class::MemWrite 125149823 15.87% 98.62% # Class of executed instruction -system.cpu.op_class::FloatMemRead 7018370 0.89% 99.51% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 3830674 0.49% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 788730744 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 893703778 # Transaction distribution -system.membus.trans_dist::ReadResp 893709517 # Transaction distribution -system.membus.trans_dist::WriteReq 128951477 # Transaction distribution -system.membus.trans_dist::WriteResp 128951477 # Transaction distribution -system.membus.trans_dist::SoftPFReq 3620 # Transaction distribution -system.membus.trans_dist::SoftPFResp 3620 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 5739 # Transaction distribution -system.membus.trans_dist::StoreCondReq 5739 # Transaction distribution -system.membus.trans_dist::StoreCondResp 5739 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1286755798 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 758584908 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2045340706 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2573511596 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1668035929 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 4241547525 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1022670353 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1022670353 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1022670353 # Request fanout histogram +sim_seconds 0.395727 +sim_ticks 395726778500 +final_tick 395726778500 +sim_freq 1000000000000 +host_inst_rate 761557 +host_op_rate 937577 +host_tick_rate 470407263 +host_mem_usage 279508 +host_seconds 841.24 +sim_insts 640654411 +sim_ops 788730070 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 395726778500 +system.physmem.bytes_read::cpu.inst 2573511596 +system.physmem.bytes_read::cpu.data 1144718516 +system.physmem.bytes_read::total 3718230112 +system.physmem.bytes_inst_read::cpu.inst 2573511596 +system.physmem.bytes_inst_read::total 2573511596 +system.physmem.bytes_written::cpu.data 523317413 +system.physmem.bytes_written::total 523317413 +system.physmem.num_reads::cpu.inst 643377899 +system.physmem.num_reads::cpu.data 250335238 +system.physmem.num_reads::total 893713137 +system.physmem.num_writes::cpu.data 128957216 +system.physmem.num_writes::total 128957216 +system.physmem.bw_read::cpu.inst 6503253598 +system.physmem.bw_read::cpu.data 2892699151 +system.physmem.bw_read::total 9395952748 +system.physmem.bw_inst_read::cpu.inst 6503253598 +system.physmem.bw_inst_read::total 6503253598 +system.physmem.bw_write::cpu.data 1322421027 +system.physmem.bw_write::total 1322421027 +system.physmem.bw_total::cpu.inst 6503253598 +system.physmem.bw_total::cpu.data 4215120178 +system.physmem.bw_total::total 10718373776 +system.pwrStateResidencyTicks::UNDEFINED 395726778500 +system.cpu_clk_domain.clock 500 +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.hits 0 +system.cpu.dstage2_mmu.stage2_tlb.misses 0 +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 +system.cpu.dtb.walker.walks 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dtb.walker.walkRequestOrigin::total 0 +system.cpu.dtb.inst_hits 0 +system.cpu.dtb.inst_misses 0 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.flush_tlb 0 +system.cpu.dtb.flush_tlb_mva 0 +system.cpu.dtb.flush_tlb_mva_asid 0 +system.cpu.dtb.flush_tlb_asid 0 +system.cpu.dtb.flush_entries 0 +system.cpu.dtb.align_faults 0 +system.cpu.dtb.prefetch_faults 0 +system.cpu.dtb.domain_faults 0 +system.cpu.dtb.perms_faults 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.inst_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.hits 0 +system.cpu.istage2_mmu.stage2_tlb.misses 0 +system.cpu.istage2_mmu.stage2_tlb.accesses 0 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 +system.cpu.itb.walker.walks 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.itb.walker.walkRequestOrigin::total 0 +system.cpu.itb.inst_hits 0 +system.cpu.itb.inst_misses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.flush_tlb 0 +system.cpu.itb.flush_tlb_mva 0 +system.cpu.itb.flush_tlb_mva_asid 0 +system.cpu.itb.flush_tlb_asid 0 +system.cpu.itb.flush_entries 0 +system.cpu.itb.align_faults 0 +system.cpu.itb.prefetch_faults 0 +system.cpu.itb.domain_faults 0 +system.cpu.itb.perms_faults 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.inst_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 673 +system.cpu.pwrStateResidencyTicks::ON 395726778500 +system.cpu.numCycles 791453558 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 640654411 +system.cpu.committedOps 788730070 +system.cpu.num_int_alu_accesses 682251400 +system.cpu.num_fp_alu_accesses 24239771 +system.cpu.num_func_calls 37261296 +system.cpu.num_conditional_control_insts 91575866 +system.cpu.num_int_insts 682251400 +system.cpu.num_fp_insts 24239771 +system.cpu.num_int_register_reads 1268495038 +system.cpu.num_int_register_writes 468423268 +system.cpu.num_fp_register_reads 28064643 +system.cpu.num_fp_register_writes 21684311 +system.cpu.num_cc_register_reads 2369173294 +system.cpu.num_cc_register_writes 351919006 +system.cpu.num_mem_refs 381221435 +system.cpu.num_load_insts 252240938 +system.cpu.num_store_insts 128980497 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 791453558 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 137364860 +system.cpu.op_class::No_OpClass 0 0.00% 0.00% +system.cpu.op_class::IntAlu 385757467 48.91% 48.91% +system.cpu.op_class::IntMult 5173441 0.66% 49.56% +system.cpu.op_class::IntDiv 0 0.00% 49.56% +system.cpu.op_class::FloatAdd 0 0.00% 49.56% +system.cpu.op_class::FloatCmp 0 0.00% 49.56% +system.cpu.op_class::FloatCvt 0 0.00% 49.56% +system.cpu.op_class::FloatMult 0 0.00% 49.56% +system.cpu.op_class::FloatMultAcc 0 0.00% 49.56% +system.cpu.op_class::FloatDiv 0 0.00% 49.56% +system.cpu.op_class::FloatMisc 0 0.00% 49.56% +system.cpu.op_class::FloatSqrt 0 0.00% 49.56% +system.cpu.op_class::SimdAdd 0 0.00% 49.56% +system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% +system.cpu.op_class::SimdAlu 0 0.00% 49.56% +system.cpu.op_class::SimdCmp 0 0.00% 49.56% +system.cpu.op_class::SimdCvt 0 0.00% 49.56% +system.cpu.op_class::SimdMisc 0 0.00% 49.56% +system.cpu.op_class::SimdMult 0 0.00% 49.56% +system.cpu.op_class::SimdMultAcc 0 0.00% 49.56% +system.cpu.op_class::SimdShift 0 0.00% 49.56% +system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56% +system.cpu.op_class::SimdSqrt 0 0.00% 49.56% +system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65% +system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65% +system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05% +system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37% +system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37% +system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% +system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% +system.cpu.op_class::MemRead 245222568 31.09% 82.76% +system.cpu.op_class::MemWrite 125149823 15.87% 98.62% +system.cpu.op_class::FloatMemRead 7018370 0.89% 99.51% +system.cpu.op_class::FloatMemWrite 3830674 0.49% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 788730744 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 395726778500 +system.membus.trans_dist::ReadReq 893703778 +system.membus.trans_dist::ReadResp 893709517 +system.membus.trans_dist::WriteReq 128951477 +system.membus.trans_dist::WriteResp 128951477 +system.membus.trans_dist::SoftPFReq 3620 +system.membus.trans_dist::SoftPFResp 3620 +system.membus.trans_dist::LoadLockedReq 5739 +system.membus.trans_dist::StoreCondReq 5739 +system.membus.trans_dist::StoreCondResp 5739 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1286755798 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 758584908 +system.membus.pkt_count::total 2045340706 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2573511596 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1668035929 +system.membus.pkt_size::total 4241547525 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 1022670353 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 1022670353 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 1022670353 ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini index ab5a083f3..b54691470 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini @@ -87,6 +87,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -96,14 +97,14 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -117,6 +118,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -129,15 +131,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dstage2_mmu] type=ArmStage2MMU @@ -193,14 +196,14 @@ port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -214,6 +217,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -226,15 +230,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=ArmInterrupts @@ -253,8 +258,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -265,8 +268,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -325,14 +326,14 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -346,6 +347,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -358,15 +360,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -402,7 +405,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=perlbmk -I. -I lib mdred.makerand.pl cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing drivers= @@ -411,14 +414,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/perlbmk +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -442,6 +446,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -453,7 +458,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -461,6 +466,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -469,6 +481,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -476,7 +489,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr index 937e051a4..92c744310 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr @@ -1,3 +1,6 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... warn: fcntl64(3, 2) passed through to host +info: Increasing stack size by one page. +info: Increasing stack size by one page. diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout index 75004ec86..e660db33d 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout @@ -3,15 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-ti gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:46:39 -gem5 executing on e108600-lin, pid 23194 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/arm/linux/simple-timing +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 18:24:09 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 59398 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/40.perlbmk/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -info: Increasing stack size by one page. 637000: 2581848540 636000: 4117852332 635000: 329081094 @@ -650,4 +647,4 @@ info: Increasing stack size by one page. 2000: 2845746745 1000: 2068042552 0: 290958364 -Exiting @ tick 1045756396500 because target called exit() +Exiting @ tick 1046047111500 because exiting with last active thread context diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index e6b9bff19..be07be0d5 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -1,686 +1,686 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.046047 # Number of seconds simulated -sim_ticks 1046047111500 # Number of ticks simulated -final_tick 1046047111500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1255251 # Simulator instruction rate (inst/s) -host_op_rate 1542152 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2053674689 # Simulator tick rate (ticks/s) -host_mem_usage 277480 # Number of bytes of host memory used -host_seconds 509.35 # Real time elapsed on the host -sim_insts 639366787 # Number of instructions simulated -sim_ops 785501035 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 112576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18471424 # Number of bytes read from this memory -system.physmem.bytes_read::total 18584000 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 112576 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 112576 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory -system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1759 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 288616 # Number of read requests responded to by this memory -system.physmem.num_reads::total 290375 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 107620 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 17658310 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 17765930 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 107620 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 107620 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4044055 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4044055 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4044055 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 107620 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 17658310 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 21809985 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 673 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 1046047111500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2092094223 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 639366787 # Number of instructions committed -system.cpu.committedOps 785501035 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses -system.cpu.num_func_calls 37261296 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 91575866 # number of instructions that are conditional controls -system.cpu.num_int_insts 682251400 # number of integer instructions -system.cpu.num_fp_insts 24239771 # number of float instructions -system.cpu.num_int_register_reads 1272307653 # number of times the integer registers were read -system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written -system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read -system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written -system.cpu.num_cc_register_reads 3116296060 # number of times the CC registers were read -system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written -system.cpu.num_mem_refs 381221435 # number of memory refs -system.cpu.num_load_insts 252240938 # Number of load instructions -system.cpu.num_store_insts 128980497 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 2092094222.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 137364860 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 385757467 48.91% 48.91% # Class of executed instruction -system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction -system.cpu.op_class::MemRead 245222568 31.09% 82.76% # Class of executed instruction -system.cpu.op_class::MemWrite 125149823 15.87% 98.62% # Class of executed instruction -system.cpu.op_class::FloatMemRead 7018370 0.89% 99.51% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 3830674 0.49% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 788730744 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 778046 # number of replacements -system.cpu.dcache.tags.tagsinuse 4093.536872 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1048273500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4093.536872 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999399 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999399 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 591 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1037 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2319 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 759367050 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 759367050 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 249613198 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 249613198 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 128882154 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 128882154 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 3481 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 3481 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 378495352 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 378495352 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 378498833 # number of overall hits -system.cpu.dcache.overall_hits::total 378498833 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 712681 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 712681 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 69323 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 69323 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 139 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 139 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 782004 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 782004 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 782143 # number of overall misses -system.cpu.dcache.overall_misses::total 782143 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 20392265000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 20392265000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4205904500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4205904500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24598169500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24598169500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24598169500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24598169500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 250325879 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 3620 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 3620 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 379277356 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 379277356 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 379280976 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 379280976 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002847 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002847 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000538 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000538 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038398 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.038398 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002062 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002062 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002062 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28613.453986 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28613.453986 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60671.126466 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60671.126466 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31455.298822 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31455.298822 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31449.708685 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31449.708685 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 88967 # number of writebacks -system.cpu.dcache.writebacks::total 88967 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712680 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 712680 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69323 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 69323 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 782003 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19679537000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 19679537000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4136581500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4136581500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1768000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1768000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23816118500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23816118500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23817886500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23817886500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038398 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038398 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27613.426783 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27613.426783 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59671.126466 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59671.126466 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12719.424460 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12719.424460 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30455.277665 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30455.277665 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30452.125701 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30452.125701 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 8769 # number of replacements -system.cpu.icache.tags.tagsinuse 1391.373825 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 643367692 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 63025.831897 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1391.373825 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.679382 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.679382 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1339 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.702637 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1286766008 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1286766008 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 643367692 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 643367692 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 643367692 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 643367692 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 643367692 # number of overall hits -system.cpu.icache.overall_hits::total 643367692 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 10208 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 10208 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 10208 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses -system.cpu.icache.overall_misses::total 10208 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 220829500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 220829500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 220829500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 220829500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 220829500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 220829500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 643377900 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 643377900 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 643377900 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 643377900 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 643377900 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 643377900 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21632.983934 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21632.983934 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21632.983934 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21632.983934 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21632.983934 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21632.983934 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 8769 # number of writebacks -system.cpu.icache.writebacks::total 8769 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10208 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 10208 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 10208 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 10208 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 10208 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 10208 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 210621500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 210621500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 210621500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 210621500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 210621500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 210621500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20632.983934 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20632.983934 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20632.983934 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20632.983934 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20632.983934 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20632.983934 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 257791 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32695.724167 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1287496 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 290559 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.431100 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 4679738000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 22.200866 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 45.803141 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 32627.720160 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000678 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001398 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.995719 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997794 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 146 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 148 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1440 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30945 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 12914999 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 12914999 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 88967 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 88967 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 8752 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 8752 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 3230 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 3230 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8449 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 8449 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490296 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 490296 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 8449 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 493526 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 501975 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 8449 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 493526 # number of overall hits -system.cpu.l2cache.overall_hits::total 501975 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 66093 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66093 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1759 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 1759 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222523 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 222523 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1759 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 288616 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 290375 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1759 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 288616 # number of overall misses -system.cpu.l2cache.overall_misses::total 290375 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3998679500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3998679500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 106512500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 106512500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13462920000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 13462920000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 106512500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 17461599500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 17568112000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 106512500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 17461599500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 17568112000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 88967 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 88967 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 8752 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 8752 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 69323 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 69323 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 10208 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 10208 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712819 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 712819 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 10208 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 782142 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 792350 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 10208 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 782142 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 792350 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953407 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.953407 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.172316 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.172316 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312173 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312173 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.172316 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.369007 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.366473 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.172316 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.369007 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.366473 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.801900 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.801900 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60552.870949 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60552.870949 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60501.251556 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60501.251556 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60552.870949 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60501.148585 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60501.461903 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60552.870949 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60501.148585 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60501.461903 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks -system.cpu.l2cache.writebacks::total 66098 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66093 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66093 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1759 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1759 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222523 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222523 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1759 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 288616 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 290375 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1759 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 288616 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 290375 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3337749500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3337749500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 88922500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 88922500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11237690000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11237690000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 88922500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14575439500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14664362000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 88922500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14575439500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14664362000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953407 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953407 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.172316 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312173 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312173 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369007 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.366473 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369007 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.366473 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.801900 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.801900 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50552.870949 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50552.870949 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50501.251556 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50501.251556 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50552.870949 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.148585 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.461903 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50552.870949 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.148585 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.461903 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1579165 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 786845 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1110 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1590 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1583 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 155065 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 8769 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 880772 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 10208 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 712819 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 29185 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2342330 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2371515 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1214528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55750976 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56965504 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 257791 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4230272 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1050141 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.002606 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.051116 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1047411 99.74% 99.74% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2723 0.26% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 7 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1050141 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 887318500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 15312000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1173213000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 546577 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 256223 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 224282 # Transaction distribution -system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution -system.membus.trans_dist::CleanEvict 190103 # Transaction distribution -system.membus.trans_dist::ReadExReq 66093 # Transaction distribution -system.membus.trans_dist::ReadExResp 66093 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 224282 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 836951 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 836951 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22814272 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22814272 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 290376 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 290376 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 290376 # Request fanout histogram -system.membus.reqLayer0.occupancy 811341000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1451875000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +sim_seconds 1.046047 +sim_ticks 1046047111500 +final_tick 1046047111500 +sim_freq 1000000000000 +host_inst_rate 550252 +host_op_rate 676018 +host_tick_rate 900249421 +host_mem_usage 289500 +host_seconds 1161.95 +sim_insts 639366787 +sim_ops 785501035 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 1046047111500 +system.physmem.bytes_read::cpu.inst 112576 +system.physmem.bytes_read::cpu.data 18471424 +system.physmem.bytes_read::total 18584000 +system.physmem.bytes_inst_read::cpu.inst 112576 +system.physmem.bytes_inst_read::total 112576 +system.physmem.bytes_written::writebacks 4230272 +system.physmem.bytes_written::total 4230272 +system.physmem.num_reads::cpu.inst 1759 +system.physmem.num_reads::cpu.data 288616 +system.physmem.num_reads::total 290375 +system.physmem.num_writes::writebacks 66098 +system.physmem.num_writes::total 66098 +system.physmem.bw_read::cpu.inst 107620 +system.physmem.bw_read::cpu.data 17658310 +system.physmem.bw_read::total 17765930 +system.physmem.bw_inst_read::cpu.inst 107620 +system.physmem.bw_inst_read::total 107620 +system.physmem.bw_write::writebacks 4044055 +system.physmem.bw_write::total 4044055 +system.physmem.bw_total::writebacks 4044055 +system.physmem.bw_total::cpu.inst 107620 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+system.membus.respLayer1.occupancy 1451875000 +system.membus.respLayer1.utilization 0.1 ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini index e2ac8f237..609dcfe4d 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -65,7 +65,7 @@ SSITSize=1024 activity=0 backComSize=5 branchPred=system.cpu.branchPred -cachePorts=200 +cacheStorePorts=200 checker=Null clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 @@ -141,6 +141,7 @@ socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -176,10 +177,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=6 @@ -193,6 +194,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=8 write_buffers=16 @@ -205,15 +207,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu.dstage2_mmu] type=ArmStage2MMU @@ -316,38 +319,52 @@ pipelined=true [system.cpu.fuPool.FUList2] type=FUDesc -children=opList +children=opList0 opList1 count=1 eventq_index=0 -opList=system.cpu.fuPool.FUList2.opList +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 -[system.cpu.fuPool.FUList2.opList] +[system.cpu.fuPool.FUList2.opList0] type=OpDesc eventq_index=0 opClass=MemRead opLat=2 pipelined=true +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=2 +pipelined=true + [system.cpu.fuPool.FUList3] type=FUDesc -children=opList +children=opList0 opList1 count=1 eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 -[system.cpu.fuPool.FUList3.opList] +[system.cpu.fuPool.FUList3.opList0] type=OpDesc eventq_index=0 opClass=MemWrite opLat=2 pipelined=true +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=2 +pipelined=true + [system.cpu.fuPool.FUList4] type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27 count=2 eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 +opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27 [system.cpu.fuPool.FUList4.opList00] type=OpDesc @@ -479,7 +496,7 @@ pipelined=true type=OpDesc eventq_index=0 opClass=SimdFloatMultAcc -opLat=1 +opLat=5 pipelined=true [system.cpu.fuPool.FUList4.opList19] @@ -531,6 +548,20 @@ opClass=FloatMult opLat=4 pipelined=true +[system.cpu.fuPool.FUList4.opList26] +type=OpDesc +eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList4.opList27] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + [system.cpu.icache] type=Cache children=tags @@ -538,10 +569,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=1 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=1 is_read_only=true max_miss_count=0 mshrs=2 @@ -555,6 +586,7 @@ response_latency=1 sequential_access=false size=32768 system=system +tag_latency=1 tags=system.cpu.icache.tags tgts_per_mshr=8 write_buffers=8 @@ -567,15 +599,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=1 default_p_state=UNDEFINED eventq_index=0 -hit_latency=1 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=1 [system.cpu.interrupts] type=ArmInterrupts @@ -594,8 +627,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -606,8 +637,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -670,10 +699,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl +data_latency=12 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=12 is_read_only=false max_miss_count=0 mshrs=16 @@ -687,6 +716,7 @@ response_latency=12 sequential_access=false size=1048576 system=system +tag_latency=12 tags=system.cpu.l2cache.tags tgts_per_mshr=8 write_buffers=8 @@ -729,15 +759,16 @@ type=RandomRepl assoc=16 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=12 default_p_state=UNDEFINED eventq_index=0 -hit_latency=12 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=1048576 +tag_latency=12 [system.cpu.toL2Bus] type=CoherentXBar @@ -773,7 +804,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=vortex lendian.raw cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing drivers= @@ -782,14 +813,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/vortex +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/vortex gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr index bbcd9d751..9acbe6def 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr @@ -1,3 +1,5 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout index 77b319c20..05ef3fbb2 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout @@ -3,12 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:59:48 -gem5 executing on e108600-lin, pid 17544 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/50.vortex/arm/linux/o3-timing +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 17:56:13 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54227 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Exiting @ tick 37982056000 because target called exit() +Exiting @ tick 37944194500 because exiting with last active thread context diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 8304f1e87..477f394fc 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,1266 +1,1266 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.037944 # Number of seconds simulated -sim_ticks 37944194500 # Number of ticks simulated -final_tick 37944194500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 220724 # Simulator instruction rate (inst/s) -host_op_rate 282280 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 118113932 # Simulator tick rate (ticks/s) -host_mem_usage 283128 # Number of bytes of host memory used -host_seconds 321.25 # Real time elapsed on the host -sim_insts 70907652 # Number of instructions simulated -sim_ops 90682607 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 2366464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5687552 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 6178176 # Number of bytes read from this memory -system.physmem.bytes_read::total 14232192 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 2366464 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 2366464 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6224000 # Number of bytes written to this memory -system.physmem.bytes_written::total 6224000 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 36976 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 88868 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 96534 # Number of read requests responded to by this memory -system.physmem.num_reads::total 222378 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97250 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97250 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 62366958 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 149892548 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 162822695 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 375082201 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 62366958 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 62366958 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 164030363 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 164030363 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 164030363 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 62366958 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 149892548 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 162822695 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 539112564 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 222379 # Number of read requests accepted -system.physmem.writeReqs 97250 # Number of write requests accepted -system.physmem.readBursts 222379 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97250 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 14222400 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9856 # Total number of bytes read from write queue -system.physmem.bytesWritten 6222336 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 14232256 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6224000 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 154 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 1 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9631 # Per bank write bursts -system.physmem.perBankRdBursts::1 9947 # Per bank write bursts -system.physmem.perBankRdBursts::2 12518 # Per bank write bursts -system.physmem.perBankRdBursts::3 24674 # Per bank write bursts -system.physmem.perBankRdBursts::4 17362 # Per bank write bursts -system.physmem.perBankRdBursts::5 22065 # Per bank write bursts -system.physmem.perBankRdBursts::6 11751 # Per bank write bursts -system.physmem.perBankRdBursts::7 14087 # Per bank write bursts -system.physmem.perBankRdBursts::8 11655 # Per bank write bursts -system.physmem.perBankRdBursts::9 16110 # Per bank write bursts -system.physmem.perBankRdBursts::10 11699 # Per bank write bursts -system.physmem.perBankRdBursts::11 11328 # Per bank write bursts -system.physmem.perBankRdBursts::12 9447 # Per bank write bursts -system.physmem.perBankRdBursts::13 9546 # Per bank write bursts -system.physmem.perBankRdBursts::14 9858 # Per bank write bursts -system.physmem.perBankRdBursts::15 20547 # Per bank write bursts -system.physmem.perBankWrBursts::0 5941 # Per bank write bursts -system.physmem.perBankWrBursts::1 6221 # Per bank write bursts -system.physmem.perBankWrBursts::2 6116 # Per bank write bursts -system.physmem.perBankWrBursts::3 6136 # Per bank write bursts -system.physmem.perBankWrBursts::4 6032 # Per bank write bursts -system.physmem.perBankWrBursts::5 6294 # Per bank write bursts -system.physmem.perBankWrBursts::6 6000 # Per bank write bursts -system.physmem.perBankWrBursts::7 5967 # Per bank write bursts -system.physmem.perBankWrBursts::8 5964 # Per bank write bursts -system.physmem.perBankWrBursts::9 6073 # Per bank write bursts -system.physmem.perBankWrBursts::10 6219 # Per bank write bursts -system.physmem.perBankWrBursts::11 5919 # Per bank write bursts -system.physmem.perBankWrBursts::12 6077 # Per bank write bursts -system.physmem.perBankWrBursts::13 6073 # Per bank write bursts -system.physmem.perBankWrBursts::14 6160 # Per bank write bursts -system.physmem.perBankWrBursts::15 6032 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 37944183500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 222379 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97250 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 111691 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 60016 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 15678 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 10788 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5274 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4596 # What read queue length does an incoming req see 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 132661 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 154.093818 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 102.620444 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 209.524421 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 82661 62.31% 62.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 32331 24.37% 86.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6343 4.78% 91.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2828 2.13% 93.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1153 0.87% 94.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1000 0.75% 95.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 785 0.59% 95.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 836 0.63% 96.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4724 3.56% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 132661 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5873 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 37.833986 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 211.191475 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 5868 99.91% 99.91% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 4 0.07% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15360-15871 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5873 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5873 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.554401 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.514141 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.221324 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4642 79.04% 79.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 60 1.02% 80.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 721 12.28% 92.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 237 4.04% 96.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 117 1.99% 98.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 50 0.85% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 21 0.36% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 10 0.17% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 9 0.15% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 3 0.05% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 3 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5873 # Writes before turning the bus around for reads -system.physmem.totQLat 8400725955 # Total ticks spent queuing -system.physmem.totMemAccLat 12567444705 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1111125000 # Total ticks spent in databus transfers -system.physmem.avgQLat 37802.79 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 56552.79 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 374.82 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 163.99 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 375.08 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 164.03 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 4.21 # Data bus utilization in percentage -system.physmem.busUtilRead 2.93 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.28 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.37 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.57 # Average write queue length when enqueuing -system.physmem.readRowHits 156951 # Number of row buffer hits during reads -system.physmem.writeRowHits 29827 # Number of row buffer hits during writes -system.physmem.readRowHitRate 70.63 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 30.67 # Row buffer hit rate for writes -system.physmem.avgGap 118713.21 # Average gap between requests -system.physmem.pageHitRate 58.46 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 506618700 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 269259045 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 871329900 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 254250540 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3004974960.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2939010630 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 75129120 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 12925802790 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 1053663840 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 77310705 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 21977801430 # Total energy per rank (pJ) -system.physmem_0.averagePower 579.213801 # Core power per rank (mW) -system.physmem_0.totalIdleTime 31303061618 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 43527335 # Time in different power states -system.physmem_0.memoryStateTime::REF 1271434000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 212368250 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 2743799817 # Time in different power states -system.physmem_0.memoryStateTime::ACT 5326073297 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 28346991801 # Time in different power states -system.physmem_1.actEnergy 440652240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 234189450 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 715349460 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 253258740 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2887578720.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2772991290 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 73095360 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 11918051910 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 1378656480 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 511952955 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 21185918985 # Total energy per rank (pJ) -system.physmem_1.averagePower 558.344142 # Core power per rank (mW) -system.physmem_1.totalIdleTime 31672221792 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 50102341 # Time in different power states -system.physmem_1.memoryStateTime::REF 1221978000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 1946071250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 3589983863 # Time in different power states -system.physmem_1.memoryStateTime::ACT 4999892367 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 26136166679 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 17059712 # Number of BP lookups -system.cpu.branchPred.condPredicted 11436495 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 610883 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9177884 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7343978 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.018205 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1859096 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 101568 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 235599 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 198019 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 37580 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 22235 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 1946 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 37944194500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 75888390 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5573583 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 87028801 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17059712 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9401093 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 65975948 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1248205 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 11552 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 20 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 32118 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22429818 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 69336 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 72217323 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.523317 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.330813 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 27066857 37.48% 37.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 8167411 11.31% 48.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9106696 12.61% 61.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 27876359 38.60% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 72217323 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.224800 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.146800 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8951903 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 26171728 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 30965562 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5674558 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 453572 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6946604 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 172649 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 100221832 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2852875 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 453572 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13609160 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 11386876 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 864961 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 31760902 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14141852 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 98228803 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 864073 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 4236637 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 68346 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4658326 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5438830 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 103135317 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 453117590 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 114171014 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 768 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 93629369 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9505948 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 19046 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 19073 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12792135 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 24137829 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21734716 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1433415 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2312086 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97293576 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 34871 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 94397579 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 595173 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6645840 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 17792691 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1085 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 72217323 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.307132 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.170641 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24111122 33.39% 33.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17469676 24.19% 57.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17013658 23.56% 81.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 11592271 16.05% 97.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2029206 2.81% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1390 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 72217323 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6732689 22.67% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 34 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11048676 37.21% 59.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 11914326 40.12% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 49 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 21 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49269666 52.19% 52.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 86409 0.09% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 33 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 12 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 19 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23933468 25.35% 77.64% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21107870 22.36% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 70 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 32 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 94397579 # Type of FU issued -system.cpu.iq.rate 1.243900 # Inst issue rate -system.cpu.iq.fu_busy_cnt 29695795 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.314582 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 291303077 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 103985333 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 93134762 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 372 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 690 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 96 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 124093153 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 221 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1368431 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1271567 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1549 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11881 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1178978 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 147641 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 185447 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 453572 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 612952 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1120138 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97344492 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 24137829 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21734716 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18951 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1593 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1115880 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11881 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 249751 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 231660 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 481411 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 93615083 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23674361 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 782496 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 16045 # number of nop insts executed -system.cpu.iew.exec_refs 44580255 # number of memory reference insts executed -system.cpu.iew.exec_branches 14200394 # Number of branches executed -system.cpu.iew.exec_stores 20905894 # Number of stores executed -system.cpu.iew.exec_rate 1.233589 # Inst execution rate -system.cpu.iew.wb_sent 93237318 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 93134858 # cumulative count of insts written-back -system.cpu.iew.wb_producers 44916796 # num instructions producing a value -system.cpu.iew.wb_consumers 76568590 # num instructions consuming a value -system.cpu.iew.wb_rate 1.227261 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.586622 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 5786029 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 440353 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 71261477 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.272611 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.107279 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 37792643 53.03% 53.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16691471 23.42% 76.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4304606 6.04% 82.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4169247 5.85% 88.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1943443 2.73% 91.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1235947 1.73% 92.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 743394 1.04% 93.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 579944 0.81% 94.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3800782 5.33% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 71261477 # Number of insts commited each cycle -system.cpu.commit.committedInsts 70913204 # Number of instructions committed -system.cpu.commit.committedOps 90688159 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 43422000 # Number of memory references committed -system.cpu.commit.loads 22866262 # Number of loads committed -system.cpu.commit.membars 15920 # Number of memory barriers committed -system.cpu.commit.branches 13741468 # Number of branches committed -system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. -system.cpu.commit.int_insts 81528527 # Number of committed integer instructions. -system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 47186033 52.03% 52.03% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 7 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 22866242 25.21% 77.33% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 20555706 22.67% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 20 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 32 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 90688159 # Class of committed instruction -system.cpu.commit.bw_lim_events 3800782 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 163909584 # The number of ROB reads -system.cpu.rob.rob_writes 193905843 # The number of ROB writes -system.cpu.timesIdled 54309 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3671067 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 70907652 # Number of Instructions Simulated -system.cpu.committedOps 90682607 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.070243 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.070243 # CPI: Total CPI of All Threads -system.cpu.ipc 0.934368 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.934368 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 101911048 # number of integer regfile reads -system.cpu.int_regfile_writes 56566498 # number of integer regfile writes -system.cpu.fp_regfile_reads 60 # number of floating regfile reads -system.cpu.fp_regfile_writes 50 # number of floating regfile writes -system.cpu.cc_regfile_reads 344842465 # number of cc regfile reads -system.cpu.cc_regfile_writes 38739142 # number of cc regfile writes -system.cpu.misc_regfile_reads 44068796 # number of misc regfile reads -system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 484861 # number of replacements -system.cpu.dcache.tags.tagsinuse 510.868864 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40324171 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 485373 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 83.078727 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 154340500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 510.868864 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997791 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997791 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 456 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 84436477 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 84436477 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 21401665 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21401665 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18831129 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18831129 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 60098 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 60098 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15305 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15305 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40232794 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40232794 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40292892 # number of overall hits -system.cpu.dcache.overall_hits::total 40292892 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 563103 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 563103 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1018772 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1018772 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 68943 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 68943 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 618 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 618 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1581875 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1581875 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1650818 # number of overall misses -system.cpu.dcache.overall_misses::total 1650818 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14421291500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14421291500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14222478926 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14222478926 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5900000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 5900000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28643770426 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28643770426 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28643770426 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28643770426 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21964768 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21964768 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 129041 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 129041 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15923 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 15923 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41814669 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41814669 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41943710 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41943710 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025637 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.025637 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051324 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.051324 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.534272 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.534272 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.038812 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.038812 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037831 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037831 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039358 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.039358 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25610.397210 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25610.397210 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13960.414034 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 13960.414034 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9546.925566 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9546.925566 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18107.480317 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18107.480317 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17351.258846 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17351.258846 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 104 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2957939 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 15 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 131286 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.933333 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 22.530498 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 484861 # number of writebacks -system.cpu.dcache.writebacks::total 484861 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 263994 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 263994 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 870189 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 870189 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 618 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 618 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1134183 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1134183 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1134183 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1134183 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299109 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 299109 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148583 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 148583 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37695 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 37695 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 447692 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 447692 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 485387 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 485387 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7100123000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7100123000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2335671469 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2335671469 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2001428000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2001428000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9435794469 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9435794469 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11437222469 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11437222469 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013618 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013618 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007485 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007485 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.292116 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.292116 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010707 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.010707 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011572 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.011572 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23737.577271 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23737.577271 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15719.641339 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15719.641339 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53095.317681 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53095.317681 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21076.531341 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 21076.531341 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23563.100102 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23563.100102 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 325105 # number of replacements -system.cpu.icache.tags.tagsinuse 510.398248 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22092527 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 325617 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 67.848199 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 1172472500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.398248 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996872 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996872 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 70 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 333 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 8 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45184842 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45184842 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 22092527 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22092527 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22092527 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22092527 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22092527 # number of overall hits -system.cpu.icache.overall_hits::total 22092527 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 337079 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 337079 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 337079 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 337079 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 337079 # number of overall misses -system.cpu.icache.overall_misses::total 337079 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 5811924859 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 5811924859 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 5811924859 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 5811924859 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 5811924859 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 5811924859 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22429606 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22429606 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22429606 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22429606 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22429606 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22429606 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015028 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.015028 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.015028 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.015028 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.015028 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.015028 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17242.025932 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17242.025932 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17242.025932 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17242.025932 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17242.025932 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17242.025932 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 559324 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 118 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 25723 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 21.744120 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 39.333333 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 325105 # number of writebacks -system.cpu.icache.writebacks::total 325105 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 11448 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 11448 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 11448 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 11448 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 11448 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 11448 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 325631 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 325631 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 325631 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 325631 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 325631 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 325631 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5369635927 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 5369635927 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5369635927 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 5369635927 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5369635927 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 5369635927 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014518 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014518 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014518 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.014518 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014518 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.014518 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16489.940844 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16489.940844 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16489.940844 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16489.940844 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16489.940844 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16489.940844 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 822760 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 825879 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 2736 # number of redundant prefetches already in prefetch queue -system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped -system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 78985 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 125384 # number of replacements -system.cpu.l2cache.tags.tagsinuse 15697.006900 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 681705 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 141714 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.810428 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15640.024987 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 56.981913 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.954591 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.003478 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.958069 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 23 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 16307 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 10 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 3 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2537 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12202 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 564 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 868 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.001404 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995300 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 25485617 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 25485617 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 259863 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 259863 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 470316 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 470316 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 137267 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 137267 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 288609 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 288609 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 256036 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 256036 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 288609 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 393303 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 681912 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 288609 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 393303 # number of overall hits -system.cpu.l2cache.overall_hits::total 681912 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 14 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 11350 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 11350 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 37008 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 37008 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 80720 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 80720 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 37008 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 92070 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 129078 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 37008 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 92070 # number of overall misses -system.cpu.l2cache.overall_misses::total 129078 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1217096500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1217096500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 3145310000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 3145310000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6905491500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 6905491500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 3145310000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8122588000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 11267898000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 3145310000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8122588000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 11267898000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 259863 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 259863 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 470316 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 470316 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 148617 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 148617 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 325617 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 325617 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 336756 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 336756 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 325617 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 485373 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 810990 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 325617 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 485373 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 810990 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.076371 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.076371 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.113655 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.113655 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.239699 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.239699 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.113655 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.189689 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.159161 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.113655 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.189689 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.159161 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 107233.171806 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 107233.171806 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84990.002162 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84990.002162 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85548.705401 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85548.705401 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84990.002162 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88221.874661 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 87295.263329 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84990.002162 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88221.874661 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 87295.263329 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.unused_prefetches 367 # number of HardPF blocks evicted w/o reference -system.cpu.l2cache.writebacks::writebacks 97250 # number of writebacks -system.cpu.l2cache.writebacks::total 97250 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3084 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 3084 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 31 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 31 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 118 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 118 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 31 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 3202 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 3233 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 31 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 3202 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 3233 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 115040 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 115040 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 14 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 14 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 8266 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 8266 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 36977 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 36977 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 80602 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 80602 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 36977 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 88868 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 125845 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 36977 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 88868 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 115040 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 240885 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 10309951422 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 10309951422 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 216500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 216500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 719316500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 719316500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2921107000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2921107000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6413507000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6413507000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2921107000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7132823500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 10053930500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2921107000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7132823500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 10309951422 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 20363881922 # number of overall MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.055619 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.055619 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.113560 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.113560 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.239348 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.239348 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113560 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.183092 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.155175 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113560 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.183092 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.297026 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 89620.579120 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 89620.579120 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15464.285714 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15464.285714 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 87021.110573 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 87021.110573 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 78997.944668 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 78997.944668 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79570.072703 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79570.072703 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 78997.944668 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80263.126210 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79891.378283 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 78997.944668 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80263.126210 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 89620.579120 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84537.774963 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1620984 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 810002 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 80349 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 18528 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 18483 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 45 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 662386 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 357113 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 550103 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 28134 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 146171 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 14 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 14 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 148617 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 148617 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 325631 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 336756 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 976352 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1455635 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2431987 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41646144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62094976 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 103741120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 271569 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 6224896 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1082573 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.091409 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.288334 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 983661 90.86% 90.86% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 98867 9.13% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 45 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1082573 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1620458000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 4.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 488577734 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 728149334 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 347777 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 205067 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 214112 # Transaction distribution -system.membus.trans_dist::WritebackDirty 97250 # Transaction distribution -system.membus.trans_dist::CleanEvict 28134 # Transaction distribution -system.membus.trans_dist::UpgradeReq 14 # Transaction distribution -system.membus.trans_dist::ReadExReq 8266 # Transaction distribution -system.membus.trans_dist::ReadExResp 8266 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 214113 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 570155 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 570155 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 20456192 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20456192 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 222393 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 222393 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 222393 # Request fanout histogram -system.membus.reqLayer0.occupancy 835299244 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1174434906 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 3.1 # Layer utilization (%) +sim_seconds 0.037944 +sim_ticks 37944194500 +final_tick 37944194500 +sim_freq 1000000000000 +host_inst_rate 98071 +host_op_rate 125422 +host_tick_rate 52480065 +host_mem_usage 294796 +host_seconds 723.02 +sim_insts 70907652 +sim_ops 90682607 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 37944194500 +system.physmem.bytes_read::cpu.inst 2366464 +system.physmem.bytes_read::cpu.data 5687552 +system.physmem.bytes_read::cpu.l2cache.prefetcher 6178176 +system.physmem.bytes_read::total 14232192 +system.physmem.bytes_inst_read::cpu.inst 2366464 +system.physmem.bytes_inst_read::total 2366464 +system.physmem.bytes_written::writebacks 6224000 +system.physmem.bytes_written::total 6224000 +system.physmem.num_reads::cpu.inst 36976 +system.physmem.num_reads::cpu.data 88868 +system.physmem.num_reads::cpu.l2cache.prefetcher 96534 +system.physmem.num_reads::total 222378 +system.physmem.num_writes::writebacks 97250 +system.physmem.num_writes::total 97250 +system.physmem.bw_read::cpu.inst 62366958 +system.physmem.bw_read::cpu.data 149892548 +system.physmem.bw_read::cpu.l2cache.prefetcher 162822695 +system.physmem.bw_read::total 375082201 +system.physmem.bw_inst_read::cpu.inst 62366958 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0.02% 100.00% +system.physmem.rdPerTurnAround::total 5873 +system.physmem.wrPerTurnAround::samples 5873 +system.physmem.wrPerTurnAround::mean 16.554401 +system.physmem.wrPerTurnAround::gmean 16.514141 +system.physmem.wrPerTurnAround::stdev 1.221324 +system.physmem.wrPerTurnAround::16 4642 79.04% 79.04% +system.physmem.wrPerTurnAround::17 60 1.02% 80.06% +system.physmem.wrPerTurnAround::18 721 12.28% 92.34% +system.physmem.wrPerTurnAround::19 237 4.04% 96.37% +system.physmem.wrPerTurnAround::20 117 1.99% 98.37% +system.physmem.wrPerTurnAround::21 50 0.85% 99.22% +system.physmem.wrPerTurnAround::22 21 0.36% 99.57% +system.physmem.wrPerTurnAround::23 10 0.17% 99.74% +system.physmem.wrPerTurnAround::24 9 0.15% 99.90% +system.physmem.wrPerTurnAround::25 3 0.05% 99.95% +system.physmem.wrPerTurnAround::26 3 0.05% 100.00% +system.physmem.wrPerTurnAround::total 5873 +system.physmem.totQLat 8400725955 +system.physmem.totMemAccLat 12567444705 +system.physmem.totBusLat 1111125000 +system.physmem.avgQLat 37802.79 +system.physmem.avgBusLat 5000.00 +system.physmem.avgMemAccLat 56552.79 +system.physmem.avgRdBW 374.82 +system.physmem.avgWrBW 163.99 +system.physmem.avgRdBWSys 375.08 +system.physmem.avgWrBWSys 164.03 +system.physmem.peakBW 12800.00 +system.physmem.busUtil 4.21 +system.physmem.busUtilRead 2.93 +system.physmem.busUtilWrite 1.28 +system.physmem.avgRdQLen 1.37 +system.physmem.avgWrQLen 24.57 +system.physmem.readRowHits 156951 +system.physmem.writeRowHits 29827 +system.physmem.readRowHitRate 70.63 +system.physmem.writeRowHitRate 30.67 +system.physmem.avgGap 118713.21 +system.physmem.pageHitRate 58.46 +system.physmem_0.actEnergy 506618700 +system.physmem_0.preEnergy 269259045 +system.physmem_0.readEnergy 871329900 +system.physmem_0.writeEnergy 254250540 +system.physmem_0.refreshEnergy 3004974960.000000 +system.physmem_0.actBackEnergy 2939010630 +system.physmem_0.preBackEnergy 75129120 +system.physmem_0.actPowerDownEnergy 12925802790 +system.physmem_0.prePowerDownEnergy 1053663840 +system.physmem_0.selfRefreshEnergy 77310705 +system.physmem_0.totalEnergy 21977801430 +system.physmem_0.averagePower 579.213801 +system.physmem_0.totalIdleTime 31303061618 +system.physmem_0.memoryStateTime::IDLE 43527335 +system.physmem_0.memoryStateTime::REF 1271434000 +system.physmem_0.memoryStateTime::SREF 212368250 +system.physmem_0.memoryStateTime::PRE_PDN 2743799817 +system.physmem_0.memoryStateTime::ACT 5326073297 +system.physmem_0.memoryStateTime::ACT_PDN 28346991801 +system.physmem_1.actEnergy 440652240 +system.physmem_1.preEnergy 234189450 +system.physmem_1.readEnergy 715349460 +system.physmem_1.writeEnergy 253258740 +system.physmem_1.refreshEnergy 2887578720.000000 +system.physmem_1.actBackEnergy 2772991290 +system.physmem_1.preBackEnergy 73095360 +system.physmem_1.actPowerDownEnergy 11918051910 +system.physmem_1.prePowerDownEnergy 1378656480 +system.physmem_1.selfRefreshEnergy 511952955 +system.physmem_1.totalEnergy 21185918985 +system.physmem_1.averagePower 558.344142 +system.physmem_1.totalIdleTime 31672221792 +system.physmem_1.memoryStateTime::IDLE 50102341 +system.physmem_1.memoryStateTime::REF 1221978000 +system.physmem_1.memoryStateTime::SREF 1946071250 +system.physmem_1.memoryStateTime::PRE_PDN 3589983863 +system.physmem_1.memoryStateTime::ACT 4999892367 +system.physmem_1.memoryStateTime::ACT_PDN 26136166679 +system.pwrStateResidencyTicks::UNDEFINED 37944194500 +system.cpu.branchPred.lookups 17059712 +system.cpu.branchPred.condPredicted 11436495 +system.cpu.branchPred.condIncorrect 610883 +system.cpu.branchPred.BTBLookups 9177884 +system.cpu.branchPred.BTBHits 7343978 +system.cpu.branchPred.BTBCorrect 0 +system.cpu.branchPred.BTBHitPct 80.018205 +system.cpu.branchPred.usedRAS 1859096 +system.cpu.branchPred.RASInCorrect 101568 +system.cpu.branchPred.indirectLookups 235599 +system.cpu.branchPred.indirectHits 198019 +system.cpu.branchPred.indirectMisses 37580 +system.cpu.branchPredindirectMispredicted 22235 +system.cpu_clk_domain.clock 500 +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37944194500 +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 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+system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 2 +system.cpu.toL2Bus.snoop_fanout::total 1082573 +system.cpu.toL2Bus.reqLayer0.occupancy 1620458000 +system.cpu.toL2Bus.reqLayer0.utilization 4.3 +system.cpu.toL2Bus.respLayer0.occupancy 488577734 +system.cpu.toL2Bus.respLayer0.utilization 1.3 +system.cpu.toL2Bus.respLayer1.occupancy 728149334 +system.cpu.toL2Bus.respLayer1.utilization 1.9 +system.membus.snoop_filter.tot_requests 347777 +system.membus.snoop_filter.hit_single_requests 205067 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 37944194500 +system.membus.trans_dist::ReadResp 214112 +system.membus.trans_dist::WritebackDirty 97250 +system.membus.trans_dist::CleanEvict 28134 +system.membus.trans_dist::UpgradeReq 14 +system.membus.trans_dist::ReadExReq 8266 +system.membus.trans_dist::ReadExResp 8266 +system.membus.trans_dist::ReadSharedReq 214113 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 570155 +system.membus.pkt_count::total 570155 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 20456192 +system.membus.pkt_size::total 20456192 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 222393 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 222393 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 222393 +system.membus.reqLayer0.occupancy 835299244 +system.membus.reqLayer0.utilization 2.2 +system.membus.respLayer1.occupancy 1174434906 +system.membus.respLayer1.utilization 3.1 ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini index 5a7d7b1a5..5da6802d2 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -65,7 +65,7 @@ SSITSize=1024 activity=0 backComSize=5 branchPred=system.cpu.branchPred -cachePorts=200 +cacheStorePorts=200 checker=Null clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 @@ -141,6 +141,7 @@ socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -176,10 +177,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=6 @@ -193,6 +194,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=8 write_buffers=16 @@ -205,15 +207,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu.dstage2_mmu] type=ArmStage2MMU @@ -316,38 +319,52 @@ pipelined=true [system.cpu.fuPool.FUList2] type=FUDesc -children=opList +children=opList0 opList1 count=1 eventq_index=0 -opList=system.cpu.fuPool.FUList2.opList +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 -[system.cpu.fuPool.FUList2.opList] +[system.cpu.fuPool.FUList2.opList0] type=OpDesc eventq_index=0 opClass=MemRead opLat=2 pipelined=true +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=2 +pipelined=true + [system.cpu.fuPool.FUList3] type=FUDesc -children=opList +children=opList0 opList1 count=1 eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 -[system.cpu.fuPool.FUList3.opList] +[system.cpu.fuPool.FUList3.opList0] type=OpDesc eventq_index=0 opClass=MemWrite opLat=2 pipelined=true +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=2 +pipelined=true + [system.cpu.fuPool.FUList4] type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27 count=2 eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 +opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27 [system.cpu.fuPool.FUList4.opList00] type=OpDesc @@ -479,7 +496,7 @@ pipelined=true type=OpDesc eventq_index=0 opClass=SimdFloatMultAcc -opLat=1 +opLat=5 pipelined=true [system.cpu.fuPool.FUList4.opList19] @@ -531,6 +548,20 @@ opClass=FloatMult opLat=4 pipelined=true +[system.cpu.fuPool.FUList4.opList26] +type=OpDesc +eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList4.opList27] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + [system.cpu.icache] type=Cache children=tags @@ -538,10 +569,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=1 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=1 is_read_only=true max_miss_count=0 mshrs=2 @@ -555,6 +586,7 @@ response_latency=1 sequential_access=false size=32768 system=system +tag_latency=1 tags=system.cpu.icache.tags tgts_per_mshr=8 write_buffers=8 @@ -567,15 +599,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=1 default_p_state=UNDEFINED eventq_index=0 -hit_latency=1 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=1 [system.cpu.interrupts] type=ArmInterrupts @@ -594,8 +627,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -606,8 +637,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -670,10 +699,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl +data_latency=12 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=12 is_read_only=false max_miss_count=0 mshrs=16 @@ -687,6 +716,7 @@ response_latency=12 sequential_access=false size=1048576 system=system +tag_latency=12 tags=system.cpu.l2cache.tags tgts_per_mshr=8 write_buffers=8 @@ -729,15 +759,16 @@ type=RandomRepl assoc=16 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=12 default_p_state=UNDEFINED eventq_index=0 -hit_latency=12 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=1048576 +tag_latency=12 [system.cpu.toL2Bus] type=CoherentXBar @@ -773,7 +804,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=bzip2 input.source 1 cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing drivers= @@ -782,14 +813,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/bzip2 +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr index caeab8324..5467490ac 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr @@ -1,4 +1,8 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4] +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout index fbc8b4e01..19305f061 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout @@ -3,20 +3,16 @@ Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/s gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:48:52 -gem5 executing on e108600-lin, pid 17438 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/arm/linux/o3-timing +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 17:56:14 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54235 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data Input data 1048576 bytes in length Compressing Input Data, level 7 -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. Compressed data 198546 bytes in length Uncompressing Data Uncompressed data 1048576 bytes in length @@ -27,4 +23,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 787742202500 because target called exit() +Exiting @ tick 787835965500 because exiting with last active thread context diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 5ac1aa00b..6256fdd50 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,1282 +1,1282 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.787836 # Number of seconds simulated -sim_ticks 787835965500 # Number of ticks simulated -final_tick 787835965500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 263266 # Simulator instruction rate (inst/s) -host_op_rate 283629 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 134283963 # Simulator tick rate (ticks/s) -host_mem_usage 329624 # Number of bytes of host memory used -host_seconds 5866.94 # Real time elapsed on the host -sim_insts 1544563024 # Number of instructions simulated -sim_ops 1664032416 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 65344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 236015808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 63804544 # Number of bytes read from this memory -system.physmem.bytes_read::total 299885696 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 65344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 65344 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 104593152 # Number of bytes written to this memory -system.physmem.bytes_written::total 104593152 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1021 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3687747 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 996946 # Number of read requests responded to by this memory -system.physmem.num_reads::total 4685714 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1634268 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1634268 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 82941 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 299574808 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 80987092 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 380644841 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 82941 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 82941 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 132760062 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 132760062 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 132760062 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 82941 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 299574808 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 80987092 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 513404904 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 4685714 # Number of read requests accepted -system.physmem.writeReqs 1634268 # Number of write requests accepted -system.physmem.readBursts 4685714 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1634268 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 299374336 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 511360 # Total number of bytes read from write queue -system.physmem.bytesWritten 104589440 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 299885696 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 104593152 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7990 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 28 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 301500 # Per bank write bursts -system.physmem.perBankRdBursts::1 301960 # Per bank write bursts -system.physmem.perBankRdBursts::2 285447 # Per bank write bursts -system.physmem.perBankRdBursts::3 288137 # Per bank write bursts -system.physmem.perBankRdBursts::4 288946 # Per bank write bursts -system.physmem.perBankRdBursts::5 285921 # Per bank write bursts -system.physmem.perBankRdBursts::6 281288 # Per bank write bursts -system.physmem.perBankRdBursts::7 278400 # Per bank write bursts -system.physmem.perBankRdBursts::8 294011 # Per bank write bursts -system.physmem.perBankRdBursts::9 300115 # Per bank write bursts -system.physmem.perBankRdBursts::10 292046 # Per bank write bursts -system.physmem.perBankRdBursts::11 297684 # Per bank write bursts -system.physmem.perBankRdBursts::12 299531 # Per bank write bursts -system.physmem.perBankRdBursts::13 298464 # Per bank write bursts -system.physmem.perBankRdBursts::14 294115 # Per bank write bursts -system.physmem.perBankRdBursts::15 290159 # Per bank write bursts -system.physmem.perBankWrBursts::0 103775 # Per bank write bursts -system.physmem.perBankWrBursts::1 101738 # Per bank write bursts -system.physmem.perBankWrBursts::2 99347 # Per bank write bursts -system.physmem.perBankWrBursts::3 99748 # Per bank write bursts -system.physmem.perBankWrBursts::4 99113 # Per bank write bursts -system.physmem.perBankWrBursts::5 98946 # Per bank write bursts -system.physmem.perBankWrBursts::6 102275 # Per bank write bursts -system.physmem.perBankWrBursts::7 103989 # Per bank write bursts -system.physmem.perBankWrBursts::8 105110 # Per bank write bursts -system.physmem.perBankWrBursts::9 104316 # Per bank write bursts -system.physmem.perBankWrBursts::10 101973 # Per bank write bursts -system.physmem.perBankWrBursts::11 102390 # Per bank write bursts -system.physmem.perBankWrBursts::12 102662 # Per bank write bursts -system.physmem.perBankWrBursts::13 102242 # Per bank write bursts -system.physmem.perBankWrBursts::14 104082 # Per bank write bursts -system.physmem.perBankWrBursts::15 102504 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 787835924500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 4685714 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1634268 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2727826 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1050681 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 326941 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 233426 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 158423 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 90275 # What 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length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 4259361 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 94.841028 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 78.814946 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 102.698820 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3400000 79.82% 79.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 662329 15.55% 95.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 94740 2.22% 97.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 35136 0.82% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 22172 0.52% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12513 0.29% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7488 0.18% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5149 0.12% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19834 0.47% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 4259361 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 98005 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 47.729004 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 99.044358 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-255 95588 97.53% 97.53% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-511 1180 1.20% 98.74% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-767 706 0.72% 99.46% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::768-1023 397 0.41% 99.86% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1279 101 0.10% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1280-1535 19 0.02% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-1791 5 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1792-2047 2 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2303 3 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2560-2815 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2816-3071 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-3327 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4608-4863 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 98005 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 98005 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.674761 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.634865 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.202481 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 70360 71.79% 71.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1982 2.02% 73.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 17660 18.02% 91.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 5209 5.32% 97.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1729 1.76% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 596 0.61% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 225 0.23% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 114 0.12% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 71 0.07% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 31 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 17 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 4 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 98005 # Writes before turning the bus around for reads -system.physmem.totQLat 162836208305 # Total ticks spent queuing -system.physmem.totMemAccLat 250543533305 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 23388620000 # Total ticks spent in databus transfers -system.physmem.avgQLat 34810.99 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 53560.99 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 380.00 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 132.76 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 380.64 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 132.76 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 4.01 # Data bus utilization in percentage -system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.04 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.94 # Average write queue length when enqueuing -system.physmem.readRowHits 1712017 # Number of row buffer hits during reads -system.physmem.writeRowHits 340548 # Number of row buffer hits during writes -system.physmem.readRowHitRate 36.60 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 20.84 # Row buffer hit rate for writes -system.physmem.avgGap 124657.94 # Average gap between requests -system.physmem.pageHitRate 32.52 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 15118935720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 8035889730 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 16504816860 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4222619820 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 59457815040.000015 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 64415436660 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1624122240 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 222796740750 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 36224267040 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 16152645360 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 444563646270 # Total energy per rank (pJ) -system.physmem_0.averagePower 564.284526 # Core power per rank (mW) -system.physmem_0.totalIdleTime 642315388170 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 1436139102 # Time in different power states -system.physmem_0.memoryStateTime::REF 25173062000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 59398115500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 94331998561 # Time in different power states -system.physmem_0.memoryStateTime::ACT 118911366978 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 488585283359 # Time in different power states -system.physmem_1.actEnergy 15292958940 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 8128385265 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 16894132500 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4307956380 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 58918161120.000015 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 64834688190 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1616111040 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 219342669570 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 35641510560 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 18222503400 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 443208649005 # Total energy per rank (pJ) -system.physmem_1.averagePower 562.564626 # Core power per rank (mW) -system.physmem_1.totalIdleTime 641423107931 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 1455389769 # Time in different power states -system.physmem_1.memoryStateTime::REF 24945910000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 67593570250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 92814429154 # Time in different power states -system.physmem_1.memoryStateTime::ACT 120009883050 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 481016783277 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 286288991 # Number of BP lookups -system.cpu.branchPred.condPredicted 223379889 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14638803 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 157014468 # Number of BTB lookups -system.cpu.branchPred.BTBHits 150316303 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.734046 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 16636731 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 64 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 3547 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 2042 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 1505 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 136 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 787835965500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1575671932 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 13942337 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2067450540 # Number of instructions fetch has processed -system.cpu.fetch.Branches 286288991 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 166955076 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1546978368 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29302455 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 311 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 1029 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 656906223 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 925 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1575573272 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.405744 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.233501 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 493163312 31.30% 31.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 465492881 29.54% 60.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 101391668 6.44% 67.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 515525411 32.72% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1575573272 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.181693 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.312107 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 74679257 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 578142352 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 849952798 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 58148325 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 14650540 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 135611620 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 746 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2037153887 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 52516232 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 14650540 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 139761664 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 493000122 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 16309 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 837842196 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 90302441 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1976324662 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 26749907 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 45308958 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 126668 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1624936 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 29276583 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1985726338 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 9127758695 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2432766069 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 161 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 310827393 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 177 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 174 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 111376144 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 542477238 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 199268014 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 26870545 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28963209 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1947887828 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 229 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1857408251 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13517769 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 283855641 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 647022412 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 59 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1575573272 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.178878 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.151815 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 622703787 39.52% 39.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 326030740 20.69% 60.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 378156304 24.00% 84.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 219671219 13.94% 98.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 29004864 1.84% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6358 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1575573272 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 166096777 40.98% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 2401 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 191354081 47.22% 88.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 47812478 11.80% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 19 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 28 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1138249696 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 803001 0.04% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 34 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 532063614 28.65% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186291823 10.03% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 37 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 24 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1857408251 # Type of FU issued -system.cpu.iq.rate 1.178804 # Inst issue rate -system.cpu.iq.fu_busy_cnt 405265784 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.218189 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5709173052 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2231756417 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1805664221 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 275 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 288 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 75 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2262673874 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 161 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 17815816 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 84170904 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 66799 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13274 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 24420969 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4535474 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4852528 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 14650540 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 25426885 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1470128 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1947888203 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 542477238 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 199268014 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 167 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 159099 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1309527 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13274 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 7696809 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8718333 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 16415142 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1827780120 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 516898840 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29628131 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 146 # number of nop insts executed -system.cpu.iew.exec_refs 698650840 # number of memory reference insts executed -system.cpu.iew.exec_branches 229565077 # Number of branches executed -system.cpu.iew.exec_stores 181752000 # Number of stores executed -system.cpu.iew.exec_rate 1.160000 # Inst execution rate -system.cpu.iew.wb_sent 1808693799 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1805664296 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1169145221 # num instructions producing a value -system.cpu.iew.wb_consumers 1689395973 # num instructions consuming a value -system.cpu.iew.wb_rate 1.145965 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692049 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 257953466 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14638116 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1536081048 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.083297 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.009309 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 955788021 62.22% 62.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 250630730 16.32% 78.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 110093475 7.17% 85.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 55285008 3.60% 89.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 29278263 1.91% 91.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 34064309 2.22% 93.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 24750177 1.61% 95.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 18104449 1.18% 96.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 58086616 3.78% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1536081048 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1544563042 # Number of instructions committed -system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 633153379 # Number of memory references committed -system.cpu.commit.loads 458306334 # Number of loads committed -system.cpu.commit.membars 62 # Number of memory barriers committed -system.cpu.commit.branches 213462427 # Number of branches committed -system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1477900421 # Number of committed integer instructions. -system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 1030178730 61.91% 61.91% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 458306322 27.54% 89.49% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 174847021 10.51% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 12 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 24 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction -system.cpu.commit.bw_lim_events 58086616 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3399979733 # The number of ROB reads -system.cpu.rob.rob_writes 3883469027 # The number of ROB writes -system.cpu.timesIdled 836 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 98660 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1544563024 # Number of Instructions Simulated -system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.020141 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.020141 # CPI: Total CPI of All Threads -system.cpu.ipc 0.980257 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.980257 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2175723378 # number of integer regfile reads -system.cpu.int_regfile_writes 1261531313 # number of integer regfile writes -system.cpu.fp_regfile_reads 42 # number of floating regfile reads -system.cpu.fp_regfile_writes 57 # number of floating regfile writes -system.cpu.cc_regfile_reads 6965468307 # number of cc regfile reads -system.cpu.cc_regfile_writes 551796531 # number of cc regfile writes -system.cpu.misc_regfile_reads 675796862 # number of misc regfile reads -system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 17001793 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.963908 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 638014747 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 17002305 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.525191 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 81846500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.963908 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999930 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999930 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 367 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1335598455 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1335598455 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 469297691 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 469297691 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 168716899 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 168716899 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 638014590 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 638014590 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 638014590 # number of overall hits -system.cpu.dcache.overall_hits::total 638014590 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 17414213 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 17414213 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3869148 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3869148 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 21283361 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21283361 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21283363 # number of overall misses -system.cpu.dcache.overall_misses::total 21283363 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 440649629000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 440649629000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 157410000348 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 157410000348 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 389500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 389500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 598059629348 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 598059629348 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 598059629348 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 598059629348 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 486711904 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 486711904 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 659297951 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 659297951 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 659297953 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 659297953 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035779 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.035779 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022419 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.022419 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032282 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032282 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032282 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032282 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25304.022008 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25304.022008 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40683.375345 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 40683.375345 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 97375 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 97375 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28099.867749 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28099.867749 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28099.865108 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28099.865108 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 21246265 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3823077 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 940794 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 67416 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.583334 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 56.708749 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 17001793 # number of writebacks -system.cpu.dcache.writebacks::total 17001793 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3149457 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3149457 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1131591 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1131591 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4281048 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4281048 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4281048 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4281048 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14264756 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 14264756 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737557 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2737557 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 17002313 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 17002313 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 17002314 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 17002314 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 354315671500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 354315671500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 121139018143 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 121139018143 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 75000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 75000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 475454689643 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 475454689643 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 475454764643 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 475454764643 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029308 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029308 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025789 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025789 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24838.537126 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24838.537126 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44250.774739 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44250.774739 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 75000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 75000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27964.118155 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27964.118155 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27964.120922 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 27964.120922 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 591 # number of replacements -system.cpu.icache.tags.tagsinuse 443.744305 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 656904625 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1075 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 611074.069767 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 443.744305 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.866688 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.866688 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 484 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 438 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.945312 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1313813517 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1313813517 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 656904625 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 656904625 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 656904625 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 656904625 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 656904625 # number of overall hits -system.cpu.icache.overall_hits::total 656904625 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1596 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1596 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1596 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1596 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1596 # number of overall misses -system.cpu.icache.overall_misses::total 1596 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 121940986 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 121940986 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 121940986 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 121940986 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 121940986 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 121940986 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 656906221 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 656906221 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 656906221 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 656906221 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 656906221 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 656906221 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76404.126566 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 76404.126566 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 76404.126566 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 76404.126566 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 76404.126566 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 76404.126566 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 19802 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 336 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 187 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 10 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 105.893048 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 33.600000 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 591 # number of writebacks -system.cpu.icache.writebacks::total 591 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 520 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 520 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 520 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 520 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 520 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 520 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1076 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1076 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1076 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1076 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1076 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1076 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 89957490 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 89957490 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 89957490 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 89957490 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 89957490 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 89957490 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83603.615242 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83603.615242 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83603.615242 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 83603.615242 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83603.615242 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 83603.615242 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 11616550 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 11644306 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 18561 # number of redundant prefetches already in prefetch queue -system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped -system.cpu.l2cache.prefetcher.pfRemovedFull 1 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 4655502 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 4647569 # number of replacements -system.cpu.l2cache.tags.tagsinuse 15870.791949 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 13265757 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4663475 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.844608 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15652.012265 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 218.779684 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.955323 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.013353 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.968676 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 135 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15771 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 3 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 109 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 23 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4017 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 7150 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2693 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1496 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.008240 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.962585 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 561731761 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 561731761 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 4837264 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 4837264 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 12143869 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 12143869 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1756642 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1756642 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 54 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 54 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 11509702 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 11509702 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 54 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 13266344 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 13266398 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 54 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 13266344 # number of overall hits -system.cpu.l2cache.overall_hits::total 13266398 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 9 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 9 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 980963 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 980963 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1022 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 1022 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2754998 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 2754998 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1022 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3735961 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 3736983 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1022 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3735961 # number of overall misses -system.cpu.l2cache.overall_misses::total 3736983 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 191500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 191500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 104504427500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 104504427500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 88486500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 88486500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 256725449000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 256725449000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 88486500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 361229876500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 361318363000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 88486500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 361229876500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 361318363000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 4837264 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 4837264 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 12143869 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 12143869 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 9 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 9 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737605 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2737605 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1076 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1076 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 14264700 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 14264700 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1076 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 17002305 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 17003381 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1076 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 17002305 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 17003381 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358329 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.358329 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.949814 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.949814 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.193134 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.193134 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.949814 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.219733 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.219779 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.949814 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.219733 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.219779 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21277.777778 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21277.777778 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 106532.486444 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 106532.486444 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 86581.702544 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 86581.702544 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93185.348592 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 93185.348592 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 86581.702544 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 96689.948450 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 96687.184020 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86581.702544 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 96689.948450 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 96687.184020 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.unused_prefetches 58080 # number of HardPF blocks evicted w/o reference -system.cpu.l2cache.writebacks::writebacks 1634268 # number of writebacks -system.cpu.l2cache.writebacks::total 1634268 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3942 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 3942 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 45595 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 45595 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 49537 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 49538 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 49537 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 49538 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1199044 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 1199044 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 9 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 9 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 977021 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 977021 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1021 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1021 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2709403 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2709403 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1021 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3686424 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3687445 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1021 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3686424 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1199044 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 4886489 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 84363300436 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 84363300436 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 137500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 137500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 98257390500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 98257390500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 82266500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 82266500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 237433882500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 237433882500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 82266500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 335691273000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 335773539500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 82266500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 335691273000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 84363300436 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 420136839936 # number of overall MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356889 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356889 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.948885 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.948885 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189938 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189938 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.948885 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216819 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.216865 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.948885 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216819 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.287383 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 70358.802876 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 70358.802876 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15277.777778 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15277.777778 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 100568.350629 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 100568.350629 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 80574.436827 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 80574.436827 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87633.283974 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87633.283974 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 80574.436827 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 91061.492926 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 91058.589213 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 80574.436827 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 91061.492926 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 70358.802876 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 85979.286956 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 34005774 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 17002402 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21251 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 202098 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 202097 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 14265775 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 6471532 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 12165120 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 3013301 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 1495847 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFResp 14 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 9 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 9 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2737605 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2737605 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1076 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 14264700 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2742 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51006435 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 51009177 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176263168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2176369792 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 6143430 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 104594048 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 23146806 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.009650 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.097758 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 22923448 99.04% 99.04% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 223357 0.96% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 23146806 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 34005271029 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 4.3 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 21045 # Layer occupancy (ticks) -system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1613498 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 25503465992 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 3.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 9333292 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 4668829 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 3708542 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1634268 # Transaction distribution -system.membus.trans_dist::CleanEvict 3013301 # Transaction distribution -system.membus.trans_dist::UpgradeReq 9 # Transaction distribution -system.membus.trans_dist::ReadExReq 977171 # Transaction distribution -system.membus.trans_dist::ReadExResp 977171 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3708543 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14019005 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14019005 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 404478784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 404478784 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 4685723 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 4685723 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 4685723 # Request fanout histogram -system.membus.reqLayer0.occupancy 17639856241 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 25447920698 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 3.2 # Layer utilization (%) +sim_seconds 0.787836 +sim_ticks 787835965500 +final_tick 787835965500 +sim_freq 1000000000000 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0 +system.physmem.wrQLenPdf::58 0 +system.physmem.wrQLenPdf::59 0 +system.physmem.wrQLenPdf::60 0 +system.physmem.wrQLenPdf::61 0 +system.physmem.wrQLenPdf::62 0 +system.physmem.wrQLenPdf::63 0 +system.physmem.bytesPerActivate::samples 4259361 +system.physmem.bytesPerActivate::mean 94.841028 +system.physmem.bytesPerActivate::gmean 78.814946 +system.physmem.bytesPerActivate::stdev 102.698820 +system.physmem.bytesPerActivate::0-127 3400000 79.82% 79.82% +system.physmem.bytesPerActivate::128-255 662329 15.55% 95.37% +system.physmem.bytesPerActivate::256-383 94740 2.22% 97.60% +system.physmem.bytesPerActivate::384-511 35136 0.82% 98.42% +system.physmem.bytesPerActivate::512-639 22172 0.52% 98.94% +system.physmem.bytesPerActivate::640-767 12513 0.29% 99.24% +system.physmem.bytesPerActivate::768-895 7488 0.18% 99.41% +system.physmem.bytesPerActivate::896-1023 5149 0.12% 99.53% +system.physmem.bytesPerActivate::1024-1151 19834 0.47% 100.00% +system.physmem.bytesPerActivate::total 4259361 +system.physmem.rdPerTurnAround::samples 98005 +system.physmem.rdPerTurnAround::mean 47.729004 +system.physmem.rdPerTurnAround::stdev 99.044358 +system.physmem.rdPerTurnAround::0-255 95588 97.53% 97.53% +system.physmem.rdPerTurnAround::256-511 1180 1.20% 98.74% +system.physmem.rdPerTurnAround::512-767 706 0.72% 99.46% +system.physmem.rdPerTurnAround::768-1023 397 0.41% 99.86% +system.physmem.rdPerTurnAround::1024-1279 101 0.10% 99.97% +system.physmem.rdPerTurnAround::1280-1535 19 0.02% 99.99% +system.physmem.rdPerTurnAround::1536-1791 5 0.01% 99.99% +system.physmem.rdPerTurnAround::1792-2047 2 0.00% 99.99% +system.physmem.rdPerTurnAround::2048-2303 3 0.00% 100.00% +system.physmem.rdPerTurnAround::2560-2815 1 0.00% 100.00% +system.physmem.rdPerTurnAround::2816-3071 1 0.00% 100.00% +system.physmem.rdPerTurnAround::3072-3327 1 0.00% 100.00% +system.physmem.rdPerTurnAround::4608-4863 1 0.00% 100.00% +system.physmem.rdPerTurnAround::total 98005 +system.physmem.wrPerTurnAround::samples 98005 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+system.physmem.wrPerTurnAround::total 98005 +system.physmem.totQLat 162836208305 +system.physmem.totMemAccLat 250543533305 +system.physmem.totBusLat 23388620000 +system.physmem.avgQLat 34810.99 +system.physmem.avgBusLat 5000.00 +system.physmem.avgMemAccLat 53560.99 +system.physmem.avgRdBW 380.00 +system.physmem.avgWrBW 132.76 +system.physmem.avgRdBWSys 380.64 +system.physmem.avgWrBWSys 132.76 +system.physmem.peakBW 12800.00 +system.physmem.busUtil 4.01 +system.physmem.busUtilRead 2.97 +system.physmem.busUtilWrite 1.04 +system.physmem.avgRdQLen 1.44 +system.physmem.avgWrQLen 24.94 +system.physmem.readRowHits 1712017 +system.physmem.writeRowHits 340548 +system.physmem.readRowHitRate 36.60 +system.physmem.writeRowHitRate 20.84 +system.physmem.avgGap 124657.94 +system.physmem.pageHitRate 32.52 +system.physmem_0.actEnergy 15118935720 +system.physmem_0.preEnergy 8035889730 +system.physmem_0.readEnergy 16504816860 +system.physmem_0.writeEnergy 4222619820 +system.physmem_0.refreshEnergy 59457815040.000015 +system.physmem_0.actBackEnergy 64415436660 +system.physmem_0.preBackEnergy 1624122240 +system.physmem_0.actPowerDownEnergy 222796740750 +system.physmem_0.prePowerDownEnergy 36224267040 +system.physmem_0.selfRefreshEnergy 16152645360 +system.physmem_0.totalEnergy 444563646270 +system.physmem_0.averagePower 564.284526 +system.physmem_0.totalIdleTime 642315388170 +system.physmem_0.memoryStateTime::IDLE 1436139102 +system.physmem_0.memoryStateTime::REF 25173062000 +system.physmem_0.memoryStateTime::SREF 59398115500 +system.physmem_0.memoryStateTime::PRE_PDN 94331998561 +system.physmem_0.memoryStateTime::ACT 118911366978 +system.physmem_0.memoryStateTime::ACT_PDN 488585283359 +system.physmem_1.actEnergy 15292958940 +system.physmem_1.preEnergy 8128385265 +system.physmem_1.readEnergy 16894132500 +system.physmem_1.writeEnergy 4307956380 +system.physmem_1.refreshEnergy 58918161120.000015 +system.physmem_1.actBackEnergy 64834688190 +system.physmem_1.preBackEnergy 1616111040 +system.physmem_1.actPowerDownEnergy 219342669570 +system.physmem_1.prePowerDownEnergy 35641510560 +system.physmem_1.selfRefreshEnergy 18222503400 +system.physmem_1.totalEnergy 443208649005 +system.physmem_1.averagePower 562.564626 +system.physmem_1.totalIdleTime 641423107931 +system.physmem_1.memoryStateTime::IDLE 1455389769 +system.physmem_1.memoryStateTime::REF 24945910000 +system.physmem_1.memoryStateTime::SREF 67593570250 +system.physmem_1.memoryStateTime::PRE_PDN 92814429154 +system.physmem_1.memoryStateTime::ACT 120009883050 +system.physmem_1.memoryStateTime::ACT_PDN 481016783277 +system.pwrStateResidencyTicks::UNDEFINED 787835965500 +system.cpu.branchPred.lookups 286288991 +system.cpu.branchPred.condPredicted 223379889 +system.cpu.branchPred.condIncorrect 14638803 +system.cpu.branchPred.BTBLookups 157014468 +system.cpu.branchPred.BTBHits 150316303 +system.cpu.branchPred.BTBCorrect 0 +system.cpu.branchPred.BTBHitPct 95.734046 +system.cpu.branchPred.usedRAS 16636731 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0.00% +system.cpu.toL2Bus.snoop_fanout::0 22923448 99.04% 99.04% +system.cpu.toL2Bus.snoop_fanout::1 223357 0.96% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 2 +system.cpu.toL2Bus.snoop_fanout::total 23146806 +system.cpu.toL2Bus.reqLayer0.occupancy 34005271029 +system.cpu.toL2Bus.reqLayer0.utilization 4.3 +system.cpu.toL2Bus.snoopLayer0.occupancy 21045 +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 +system.cpu.toL2Bus.respLayer0.occupancy 1613498 +system.cpu.toL2Bus.respLayer0.utilization 0.0 +system.cpu.toL2Bus.respLayer1.occupancy 25503465992 +system.cpu.toL2Bus.respLayer1.utilization 3.2 +system.membus.snoop_filter.tot_requests 9333292 +system.membus.snoop_filter.hit_single_requests 4668829 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 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100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 4685723 +system.membus.reqLayer0.occupancy 17639856241 +system.membus.reqLayer0.utilization 2.2 +system.membus.respLayer1.occupancy 25447920698 +system.membus.respLayer1.utilization 3.2 ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini index 0bd2c9396..36301b9e3 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini @@ -90,6 +90,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -165,8 +166,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -177,8 +176,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -239,7 +236,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=bzip2 input.source 1 cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic drivers= @@ -248,14 +245,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/bzip2 +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -279,6 +277,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -290,7 +289,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -298,6 +297,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -306,6 +312,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -313,7 +320,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr index aadc3d011..43d70058a 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr @@ -1,2 +1,6 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout index c1b3d9c87..61d98894f 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout @@ -3,20 +3,16 @@ Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atom gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:38:22 -gem5 executing on e108600-lin, pid 23077 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/arm/linux/simple-atomic +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 18:15:54 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 57397 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/60.bzip2/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data Input data 1048576 bytes in length Compressing Input Data, level 7 -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. Compressed data 198546 bytes in length Uncompressing Data Uncompressed data 1048576 bytes in length @@ -27,4 +23,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 832017490500 because target called exit() +Exiting @ tick 832017490500 because exiting with last active thread context diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index 2806362a5..5e4ef201f 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -1,262 +1,262 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.832017 # Number of seconds simulated -sim_ticks 832017490500 # Number of ticks simulated -final_tick 832017490500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2178592 # Simulator instruction rate (inst/s) -host_op_rate 2347103 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1173553065 # Simulator tick rate (ticks/s) -host_mem_usage 260024 # Number of bytes of host memory used -host_seconds 708.97 # Real time elapsed on the host -sim_insts 1544563042 # Number of instructions simulated -sim_ops 1664032434 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 6178262360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1581387671 # Number of bytes read from this memory -system.physmem.bytes_read::total 7759650031 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 6178262360 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6178262360 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 624158392 # Number of bytes written to this memory -system.physmem.bytes_written::total 624158392 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1544565590 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 454909197 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1999474787 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 172586108 # Number of write requests responded to by this memory -system.physmem.num_writes::total 172586108 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7425640002 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1900666379 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9326306381 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7425640002 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7425640002 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 750174605 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 750174605 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7425640002 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2650840984 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10076480986 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 832017490500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1664034982 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1544563042 # Number of instructions committed -system.cpu.committedOps 1664032434 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses -system.cpu.num_func_calls 27330256 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 167612489 # number of instructions that are conditional controls -system.cpu.num_int_insts 1477900422 # number of integer instructions -system.cpu.num_fp_insts 36 # number of float instructions -system.cpu.num_int_register_reads 2605402867 # number of times the integer registers were read -system.cpu.num_int_register_writes 1125475224 # number of times the integer registers were written -system.cpu.num_fp_register_reads 24 # number of times the floating registers were read -system.cpu.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu.num_cc_register_reads 4992096239 # number of times the CC registers were read -system.cpu.num_cc_register_writes 518236214 # number of times the CC registers were written -system.cpu.num_mem_refs 633153380 # number of memory refs -system.cpu.num_load_insts 458306334 # Number of load instructions -system.cpu.num_store_insts 174847046 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1664034981.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 213462427 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 1030178776 61.91% 61.91% # Class of executed instruction -system.cpu.op_class::IntMult 700322 0.04% 61.95% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::MemRead 458306322 27.54% 89.49% # Class of executed instruction -system.cpu.op_class::MemWrite 174847022 10.51% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 12 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 24 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1664032481 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 1999474725 # Transaction distribution -system.membus.trans_dist::ReadResp 1999474786 # Transaction distribution -system.membus.trans_dist::WriteReq 172586047 # Transaction distribution -system.membus.trans_dist::WriteResp 172586047 # Transaction distribution -system.membus.trans_dist::SoftPFReq 1 # Transaction distribution -system.membus.trans_dist::SoftPFResp 1 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 61 # Transaction distribution -system.membus.trans_dist::StoreCondReq 61 # Transaction distribution -system.membus.trans_dist::StoreCondResp 61 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 3089131180 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1254990610 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4344121790 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 6178262360 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2205546063 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 8383808423 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2172060895 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2172060895 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2172060895 # Request fanout histogram +sim_seconds 0.832017 +sim_ticks 832017490500 +final_tick 832017490500 +sim_freq 1000000000000 +host_inst_rate 917891 +host_op_rate 988888 +host_tick_rate 494444669 +host_mem_usage 271524 +host_seconds 1682.73 +sim_insts 1544563042 +sim_ops 1664032434 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 832017490500 +system.physmem.bytes_read::cpu.inst 6178262360 +system.physmem.bytes_read::cpu.data 1581387671 +system.physmem.bytes_read::total 7759650031 +system.physmem.bytes_inst_read::cpu.inst 6178262360 +system.physmem.bytes_inst_read::total 6178262360 +system.physmem.bytes_written::cpu.data 624158392 +system.physmem.bytes_written::total 624158392 +system.physmem.num_reads::cpu.inst 1544565590 +system.physmem.num_reads::cpu.data 454909197 +system.physmem.num_reads::total 1999474787 +system.physmem.num_writes::cpu.data 172586108 +system.physmem.num_writes::total 172586108 +system.physmem.bw_read::cpu.inst 7425640002 +system.physmem.bw_read::cpu.data 1900666379 +system.physmem.bw_read::total 9326306381 +system.physmem.bw_inst_read::cpu.inst 7425640002 +system.physmem.bw_inst_read::total 7425640002 +system.physmem.bw_write::cpu.data 750174605 +system.physmem.bw_write::total 750174605 +system.physmem.bw_total::cpu.inst 7425640002 +system.physmem.bw_total::cpu.data 2650840984 +system.physmem.bw_total::total 10076480986 +system.pwrStateResidencyTicks::UNDEFINED 832017490500 +system.cpu_clk_domain.clock 500 +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.read_misses 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+system.cpu.workload.numSyscalls 46 +system.cpu.pwrStateResidencyTicks::ON 832017490500 +system.cpu.numCycles 1664034982 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 1544563042 +system.cpu.committedOps 1664032434 +system.cpu.num_int_alu_accesses 1477900422 +system.cpu.num_fp_alu_accesses 36 +system.cpu.num_func_calls 27330256 +system.cpu.num_conditional_control_insts 167612489 +system.cpu.num_int_insts 1477900422 +system.cpu.num_fp_insts 36 +system.cpu.num_int_register_reads 2605402867 +system.cpu.num_int_register_writes 1125475224 +system.cpu.num_fp_register_reads 24 +system.cpu.num_fp_register_writes 16 +system.cpu.num_cc_register_reads 4992096239 +system.cpu.num_cc_register_writes 518236214 +system.cpu.num_mem_refs 633153380 +system.cpu.num_load_insts 458306334 +system.cpu.num_store_insts 174847046 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 1664034982 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 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+system.cpu.op_class::SimdShift 0 0.00% 61.95% +system.cpu.op_class::SimdShiftAcc 0 0.00% 61.95% +system.cpu.op_class::SimdSqrt 0 0.00% 61.95% +system.cpu.op_class::SimdFloatAdd 0 0.00% 61.95% +system.cpu.op_class::SimdFloatAlu 0 0.00% 61.95% +system.cpu.op_class::SimdFloatCmp 0 0.00% 61.95% +system.cpu.op_class::SimdFloatCvt 0 0.00% 61.95% +system.cpu.op_class::SimdFloatDiv 0 0.00% 61.95% +system.cpu.op_class::SimdFloatMisc 3 0.00% 61.95% +system.cpu.op_class::SimdFloatMult 0 0.00% 61.95% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95% +system.cpu.op_class::MemRead 458306322 27.54% 89.49% +system.cpu.op_class::MemWrite 174847022 10.51% 100.00% +system.cpu.op_class::FloatMemRead 12 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 24 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 1664032481 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 832017490500 +system.membus.trans_dist::ReadReq 1999474725 +system.membus.trans_dist::ReadResp 1999474786 +system.membus.trans_dist::WriteReq 172586047 +system.membus.trans_dist::WriteResp 172586047 +system.membus.trans_dist::SoftPFReq 1 +system.membus.trans_dist::SoftPFResp 1 +system.membus.trans_dist::LoadLockedReq 61 +system.membus.trans_dist::StoreCondReq 61 +system.membus.trans_dist::StoreCondResp 61 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 3089131180 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1254990610 +system.membus.pkt_count::total 4344121790 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 6178262360 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2205546063 +system.membus.pkt_size::total 8383808423 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 2172060895 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 2172060895 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 2172060895 ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini index 65c2bbf99..c5f8c8ed0 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini @@ -87,6 +87,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -96,14 +97,14 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -117,6 +118,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -129,15 +131,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dstage2_mmu] type=ArmStage2MMU @@ -193,14 +196,14 @@ port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -214,6 +217,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -226,15 +230,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=ArmInterrupts @@ -253,8 +258,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -265,8 +268,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -325,14 +326,14 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -346,6 +347,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -358,15 +360,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -402,7 +405,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=bzip2 input.source 1 cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing drivers= @@ -411,14 +414,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/bzip2 +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -442,6 +446,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -453,7 +458,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -461,6 +466,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -469,6 +481,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -476,7 +489,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr index aadc3d011..43d70058a 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr @@ -1,2 +1,6 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout index 4382bd2ba..3fe74519c 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout @@ -3,20 +3,16 @@ Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:49:25 -gem5 executing on e108600-lin, pid 23292 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/arm/linux/simple-timing +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 17:57:50 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54313 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/60.bzip2/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data Input data 1048576 bytes in length Compressing Input Data, level 7 -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. Compressed data 198546 bytes in length Uncompressing Data Uncompressed data 1048576 bytes in length @@ -27,4 +23,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2377029670500 because target called exit() +Exiting @ tick 2379921906500 because exiting with last active thread context diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 11790cc5e..fd3a8134b 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -1,682 +1,682 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.379922 # Number of seconds simulated -sim_ticks 2379921906500 # Number of ticks simulated -final_tick 2379921906500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1526036 # Simulator instruction rate (inst/s) -host_op_rate 1644518 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2360243305 # Simulator tick rate (ticks/s) -host_mem_usage 271808 # Number of bytes of host memory used -host_seconds 1008.34 # Real time elapsed on the host -sim_insts 1538759602 # Number of instructions simulated -sim_ops 1658228915 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 126077056 # Number of bytes read from this memory -system.physmem.bytes_read::total 126116480 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 66029376 # Number of bytes written to this memory -system.physmem.bytes_written::total 66029376 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1969954 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1970570 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1031709 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1031709 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 16565 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 52975291 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52991856 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 16565 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 16565 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 27744346 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 27744346 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 27744346 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 16565 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 52975291 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 80736202 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 2379921906500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 4759843813 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1538759602 # Number of instructions committed -system.cpu.committedOps 1658228915 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses -system.cpu.num_func_calls 27330256 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 167612489 # number of instructions that are conditional controls -system.cpu.num_int_insts 1477900422 # number of integer instructions -system.cpu.num_fp_insts 36 # number of float instructions -system.cpu.num_int_register_reads 2601860297 # number of times the integer registers were read -system.cpu.num_int_register_writes 1125475224 # number of times the integer registers were written -system.cpu.num_fp_register_reads 24 # number of times the floating registers were read -system.cpu.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu.num_cc_register_reads 6356387678 # number of times the CC registers were read -system.cpu.num_cc_register_writes 518236214 # number of times the CC registers were written -system.cpu.num_mem_refs 633153380 # number of memory refs -system.cpu.num_load_insts 458306334 # Number of load instructions -system.cpu.num_store_insts 174847046 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 4759843812.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 213462427 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 1030178776 61.91% 61.91% # Class of executed instruction -system.cpu.op_class::IntMult 700322 0.04% 61.95% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95% # Class of executed instruction -system.cpu.op_class::MemRead 458306322 27.54% 89.49% # Class of executed instruction -system.cpu.op_class::MemWrite 174847022 10.51% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 12 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 24 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1664032481 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9111140 # number of replacements -system.cpu.dcache.tags.tagsinuse 4083.747199 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 25232837500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4083.747199 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997009 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997009 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1149 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2648 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 147 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1264105846 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1264105846 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 447683049 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 447683049 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 618379947 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 618379947 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 618379947 # number of overall hits -system.cpu.dcache.overall_hits::total 618379947 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7226086 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7226086 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 9115235 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses -system.cpu.dcache.overall_misses::total 9115236 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 152766688500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 152766688500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 64243803000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 64243803000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 217010491500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 217010491500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 217010491500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 217010491500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 627495182 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 627495182 # number of demand (read+write) accesses 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of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 3667054 # number of writebacks -system.cpu.dcache.writebacks::total 3667054 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226086 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7226086 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 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62000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22807.448903 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22807.448903 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22807.453203 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22807.453203 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 7 # number of replacements -system.cpu.icache.tags.tagsinuse 515.169434 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1544564953 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 638 # Sample count of references to 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-system.cpu.icache.tags.data_accesses 3089131820 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1544564953 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1544564953 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1544564953 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1544564953 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1544564953 # number of overall hits -system.cpu.icache.overall_hits::total 1544564953 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 638 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 638 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 638 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses 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latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61335.423197 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61335.423197 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61335.423197 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61335.423197 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 7 # number of writebacks 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cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38494000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 38494000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60335.423197 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60335.423197 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60335.423197 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 60335.423197 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60335.423197 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 60335.423197 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1938113 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31679.342131 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 16254769 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1970881 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 8.247463 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 138952277000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 10.111234 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.251326 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31645.979571 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000309 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000710 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.965759 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.966777 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 744 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2874 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1739 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27370 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 147777841 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 147777841 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 3667054 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 3667054 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 7 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 7 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1095453 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1095453 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 22 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 22 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6049829 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 6049829 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7145282 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7145304 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 7145282 # number of overall hits -system.cpu.l2cache.overall_hits::total 7145304 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 793696 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 793696 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 616 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 616 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1176258 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 1176258 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 616 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1969954 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1970570 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1969954 # number of overall misses -system.cpu.l2cache.overall_misses::total 1970570 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 48018674000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 48018674000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 37281000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 37281000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 71177285500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 71177285500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 37281000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 119195959500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 119233240500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 37281000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 119195959500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 119233240500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 3667054 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 3667054 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 7 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 7 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889149 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1889149 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 638 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 638 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7226087 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 7226087 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 638 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9115236 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9115874 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 638 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9115236 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9115874 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.420134 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.420134 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.965517 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.965517 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.162779 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.162779 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965517 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.216117 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.216169 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.216117 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.216169 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.083155 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.083155 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60521.103896 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60521.103896 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60511.627126 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60511.627126 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60521.103896 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60506.976051 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60506.980468 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60521.103896 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60506.976051 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60506.980468 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 1031709 # number of writebacks -system.cpu.l2cache.writebacks::total 1031709 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 220 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 220 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 793696 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 793696 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 616 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 616 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1176258 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1176258 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1969954 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1970570 # number of demand (read+write) MSHR misses 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 99496419500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 99527540500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31121000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 99496419500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 99527540500 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.420134 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.420134 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965517 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162779 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162779 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216117 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.216169 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216117 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.216169 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.083155 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.083155 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50521.103896 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50521.103896 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50511.627126 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50511.627126 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50521.103896 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50506.976051 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50506.980468 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50521.103896 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50506.976051 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50506.980468 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 18227021 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9111154 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1151 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1220 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1220 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4698763 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 7 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6350490 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 638 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7226087 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1283 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27341612 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27342895 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818066560 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 818107840 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1938113 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 66029376 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11053987 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000215 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.014666 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11051609 99.98% 99.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2378 0.02% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11053987 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12780571500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 957000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13672854000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 3907683 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1937205 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1176874 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1031709 # Transaction distribution -system.membus.trans_dist::CleanEvict 905404 # Transaction distribution -system.membus.trans_dist::ReadExReq 793696 # Transaction distribution -system.membus.trans_dist::ReadExResp 793696 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1176874 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5878253 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5878253 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192145856 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 192145856 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1970570 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1970570 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1970570 # Request fanout histogram -system.membus.reqLayer0.occupancy 8048170000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 9852850000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.4 # Layer utilization (%) +sim_seconds 2.379922 +sim_ticks 2379921906500 +final_tick 2379921906500 +sim_freq 1000000000000 +host_inst_rate 663470 +host_op_rate 714982 +host_tick_rate 1026156085 +host_mem_usage 282544 +host_seconds 2319.26 +sim_insts 1538759602 +sim_ops 1658228915 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 2379921906500 +system.physmem.bytes_read::cpu.inst 39424 +system.physmem.bytes_read::cpu.data 126077056 +system.physmem.bytes_read::total 126116480 +system.physmem.bytes_inst_read::cpu.inst 39424 +system.physmem.bytes_inst_read::total 39424 +system.physmem.bytes_written::writebacks 66029376 +system.physmem.bytes_written::total 66029376 +system.physmem.num_reads::cpu.inst 616 +system.physmem.num_reads::cpu.data 1969954 +system.physmem.num_reads::total 1970570 +system.physmem.num_writes::writebacks 1031709 +system.physmem.num_writes::total 1031709 +system.physmem.bw_read::cpu.inst 16565 +system.physmem.bw_read::cpu.data 52975291 +system.physmem.bw_read::total 52991856 +system.physmem.bw_inst_read::cpu.inst 16565 +system.physmem.bw_inst_read::total 16565 +system.physmem.bw_write::writebacks 27744346 +system.physmem.bw_write::total 27744346 +system.physmem.bw_total::writebacks 27744346 +system.physmem.bw_total::cpu.inst 16565 +system.physmem.bw_total::cpu.data 52975291 +system.physmem.bw_total::total 80736202 +system.pwrStateResidencyTicks::UNDEFINED 2379921906500 +system.cpu_clk_domain.clock 500 +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 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+system.cpu.dtb.walker.walkRequestOrigin::total 0 +system.cpu.dtb.inst_hits 0 +system.cpu.dtb.inst_misses 0 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.flush_tlb 0 +system.cpu.dtb.flush_tlb_mva 0 +system.cpu.dtb.flush_tlb_mva_asid 0 +system.cpu.dtb.flush_tlb_asid 0 +system.cpu.dtb.flush_entries 0 +system.cpu.dtb.align_faults 0 +system.cpu.dtb.prefetch_faults 0 +system.cpu.dtb.domain_faults 0 +system.cpu.dtb.perms_faults 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.inst_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 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100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 1970570 +system.membus.reqLayer0.occupancy 8048170000 +system.membus.reqLayer0.utilization 0.3 +system.membus.respLayer1.occupancy 9852850000 +system.membus.respLayer1.utilization 0.4 ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini index 3f64cee84..2dc49338c 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=atomic @@ -88,6 +89,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -167,7 +169,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=bzip2 input.source 1 cwd=build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic drivers= @@ -176,14 +178,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/bzip2 +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/bzip2 gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -207,6 +210,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -218,7 +222,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -226,6 +230,13 @@ width=16 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -234,6 +245,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -241,7 +253,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr index aadc3d011..43d70058a 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr @@ -1,2 +1,6 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout index 715860400..c93c64d50 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout @@ -3,20 +3,16 @@ Redirecting stderr to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atom gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:35:23 -gem5 started Jul 21 2016 14:36:17 -gem5 executing on e108600-lin, pid 18539 -command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/x86/linux/simple-atomic +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:24 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87211 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/60.bzip2/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data Input data 1048576 bytes in length Compressing Input Data, level 7 -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. Compressed data 198546 bytes in length Uncompressing Data Uncompressed data 1048576 bytes in length @@ -27,4 +23,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2846007227500 because target called exit() +Exiting @ tick 2846007227500 because exiting with last active thread context diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index 213b5c5af..3d3e0703d 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -1,145 +1,145 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.846007 # Number of seconds simulated -sim_ticks 2846007227500 # Number of ticks simulated -final_tick 2846007227500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1654731 # Simulator instruction rate (inst/s) -host_op_rate 2578221 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1565575242 # Simulator tick rate (ticks/s) -host_mem_usage 262288 # Number of bytes of host memory used -host_seconds 1817.87 # Real time elapsed on the host -sim_insts 3008081022 # Number of instructions simulated -sim_ops 4686862596 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 32105863056 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5023868345 # Number of bytes read from this memory -system.physmem.bytes_read::total 37129731401 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 32105863056 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 32105863056 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 1544656792 # Number of bytes written to this memory -system.physmem.bytes_written::total 1544656792 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4013232882 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1239184746 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5252417628 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 438528338 # Number of write requests responded to by this memory -system.physmem.num_writes::total 438528338 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11281019509 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1765233867 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13046253376 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11281019509 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11281019509 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 542745211 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 542745211 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11281019509 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2307979078 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13588998587 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 2846007227500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 5692014456 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 3008081022 # Number of instructions committed -system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4684368009 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 33534539 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls -system.cpu.num_int_insts 4684368009 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 10688755601 # number of times the integer registers were read -system.cpu.num_int_register_writes 3999841477 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 1226718827 # number of times the CC registers were read -system.cpu.num_cc_register_writes 1355930461 # number of times the CC registers were written -system.cpu.num_mem_refs 1677713084 # number of memory refs -system.cpu.num_load_insts 1239184746 # Number of load instructions -system.cpu.num_store_insts 438528338 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 5692014455.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 248500691 # Number of branches fetched -system.cpu.op_class::No_OpClass 2494522 0.05% 0.05% # Class of executed instruction -system.cpu.op_class::IntAlu 3006647871 64.15% 64.20% # Class of executed instruction -system.cpu.op_class::IntMult 6215 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::IntDiv 904 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::MemRead 1239184746 26.44% 90.64% # Class of executed instruction -system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 4686862596 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 5252417628 # Transaction distribution -system.membus.trans_dist::ReadResp 5252417628 # Transaction distribution -system.membus.trans_dist::WriteReq 438528338 # Transaction distribution -system.membus.trans_dist::WriteResp 438528338 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 8026465764 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.icache_port::total 8026465764 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3355426168 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::total 3355426168 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11381891932 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 32105863056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::total 32105863056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 6568525137 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::total 6568525137 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 38674388193 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 5690945966 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5690945966 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5690945966 # Request fanout histogram +sim_seconds 2.846007 +sim_ticks 2846007227500 +final_tick 2846007227500 +sim_freq 1000000000000 +host_inst_rate 877028 +host_op_rate 1366490 +host_tick_rate 829774485 +host_mem_usage 274188 +host_seconds 3429.86 +sim_insts 3008081022 +sim_ops 4686862596 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 2846007227500 +system.physmem.bytes_read::cpu.inst 32105863056 +system.physmem.bytes_read::cpu.data 5023868345 +system.physmem.bytes_read::total 37129731401 +system.physmem.bytes_inst_read::cpu.inst 32105863056 +system.physmem.bytes_inst_read::total 32105863056 +system.physmem.bytes_written::cpu.data 1544656792 +system.physmem.bytes_written::total 1544656792 +system.physmem.num_reads::cpu.inst 4013232882 +system.physmem.num_reads::cpu.data 1239184746 +system.physmem.num_reads::total 5252417628 +system.physmem.num_writes::cpu.data 438528338 +system.physmem.num_writes::total 438528338 +system.physmem.bw_read::cpu.inst 11281019509 +system.physmem.bw_read::cpu.data 1765233867 +system.physmem.bw_read::total 13046253376 +system.physmem.bw_inst_read::cpu.inst 11281019509 +system.physmem.bw_inst_read::total 11281019509 +system.physmem.bw_write::cpu.data 542745211 +system.physmem.bw_write::total 542745211 +system.physmem.bw_total::cpu.inst 11281019509 +system.physmem.bw_total::cpu.data 2307979078 +system.physmem.bw_total::total 13588998587 +system.pwrStateResidencyTicks::UNDEFINED 2846007227500 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2846007227500 +system.cpu.apic_clk_domain.clock 8000 +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 2846007227500 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2846007227500 +system.cpu.workload.numSyscalls 46 +system.cpu.pwrStateResidencyTicks::ON 2846007227500 +system.cpu.numCycles 5692014456 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 3008081022 +system.cpu.committedOps 4686862596 +system.cpu.num_int_alu_accesses 4684368009 +system.cpu.num_fp_alu_accesses 0 +system.cpu.num_func_calls 33534539 +system.cpu.num_conditional_control_insts 182173300 +system.cpu.num_int_insts 4684368009 +system.cpu.num_fp_insts 0 +system.cpu.num_int_register_reads 10688755601 +system.cpu.num_int_register_writes 3999841477 +system.cpu.num_fp_register_reads 0 +system.cpu.num_fp_register_writes 0 +system.cpu.num_cc_register_reads 1226718827 +system.cpu.num_cc_register_writes 1355930461 +system.cpu.num_mem_refs 1677713084 +system.cpu.num_load_insts 1239184746 +system.cpu.num_store_insts 438528338 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 5692014456 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 248500691 +system.cpu.op_class::No_OpClass 2494522 0.05% 0.05% +system.cpu.op_class::IntAlu 3006647871 64.15% 64.20% +system.cpu.op_class::IntMult 6215 0.00% 64.20% +system.cpu.op_class::IntDiv 904 0.00% 64.20% +system.cpu.op_class::FloatAdd 0 0.00% 64.20% +system.cpu.op_class::FloatCmp 0 0.00% 64.20% +system.cpu.op_class::FloatCvt 0 0.00% 64.20% +system.cpu.op_class::FloatMult 0 0.00% 64.20% +system.cpu.op_class::FloatMultAcc 0 0.00% 64.20% +system.cpu.op_class::FloatDiv 0 0.00% 64.20% +system.cpu.op_class::FloatMisc 0 0.00% 64.20% +system.cpu.op_class::FloatSqrt 0 0.00% 64.20% +system.cpu.op_class::SimdAdd 0 0.00% 64.20% +system.cpu.op_class::SimdAddAcc 0 0.00% 64.20% +system.cpu.op_class::SimdAlu 0 0.00% 64.20% +system.cpu.op_class::SimdCmp 0 0.00% 64.20% +system.cpu.op_class::SimdCvt 0 0.00% 64.20% +system.cpu.op_class::SimdMisc 0 0.00% 64.20% +system.cpu.op_class::SimdMult 0 0.00% 64.20% +system.cpu.op_class::SimdMultAcc 0 0.00% 64.20% +system.cpu.op_class::SimdShift 0 0.00% 64.20% +system.cpu.op_class::SimdShiftAcc 0 0.00% 64.20% +system.cpu.op_class::SimdSqrt 0 0.00% 64.20% +system.cpu.op_class::SimdFloatAdd 0 0.00% 64.20% +system.cpu.op_class::SimdFloatAlu 0 0.00% 64.20% +system.cpu.op_class::SimdFloatCmp 0 0.00% 64.20% +system.cpu.op_class::SimdFloatCvt 0 0.00% 64.20% +system.cpu.op_class::SimdFloatDiv 0 0.00% 64.20% +system.cpu.op_class::SimdFloatMisc 0 0.00% 64.20% +system.cpu.op_class::SimdFloatMult 0 0.00% 64.20% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.20% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.20% +system.cpu.op_class::MemRead 1239184746 26.44% 90.64% +system.cpu.op_class::MemWrite 438528338 9.36% 100.00% +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 4686862596 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 2846007227500 +system.membus.trans_dist::ReadReq 5252417628 +system.membus.trans_dist::ReadResp 5252417628 +system.membus.trans_dist::WriteReq 438528338 +system.membus.trans_dist::WriteResp 438528338 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 8026465764 +system.membus.pkt_count_system.cpu.icache_port::total 8026465764 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3355426168 +system.membus.pkt_count_system.cpu.dcache_port::total 3355426168 +system.membus.pkt_count::total 11381891932 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 32105863056 +system.membus.pkt_size_system.cpu.icache_port::total 32105863056 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 6568525137 +system.membus.pkt_size_system.cpu.dcache_port::total 6568525137 +system.membus.pkt_size::total 38674388193 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 5690945966 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 5690945966 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 5690945966 ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini index 1048d999e..136c4396f 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=timing @@ -85,6 +86,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -100,14 +102,14 @@ eventq_index=0 [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -121,6 +123,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -133,15 +136,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dtb] type=X86TLB @@ -166,14 +170,14 @@ port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -187,6 +191,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -199,15 +204,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=X86LocalApic @@ -253,14 +259,14 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -274,6 +280,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -286,15 +293,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -330,7 +338,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=bzip2 input.source 1 cwd=build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing drivers= @@ -339,14 +347,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/bzip2 +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/bzip2 gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -370,6 +379,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -381,7 +391,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -389,6 +399,13 @@ width=16 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -397,6 +414,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -404,7 +422,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr index aadc3d011..43d70058a 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr @@ -1,2 +1,6 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout index 0337bc6ef..f2fd8c974 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout @@ -3,20 +3,16 @@ Redirecting stderr to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:35:23 -gem5 started Jul 21 2016 14:36:20 -gem5 executing on e108600-lin, pid 18569 -command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/x86/linux/simple-timing +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:21 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87163 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data Input data 1048576 bytes in length Compressing Input Data, level 7 -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. Compressed data 198546 bytes in length Uncompressing Data Uncompressed data 1048576 bytes in length @@ -27,4 +23,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 5895947852500 because target called exit() +Exiting @ tick 5898831348500 because exiting with last active thread context diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 4f06487d9..01185a8e0 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,541 +1,541 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.898831 # Number of seconds simulated -sim_ticks 5898831348500 # Number of ticks simulated -final_tick 5898831348500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1175665 # Simulator instruction rate (inst/s) -host_op_rate 1831792 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2305472192 # Simulator tick rate (ticks/s) -host_mem_usage 275096 # Number of bytes of host memory used -host_seconds 2558.62 # Real time elapsed on the host -sim_insts 3008081022 # Number of instructions simulated -sim_ops 4686862596 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 126068992 # Number of bytes read from this memory -system.physmem.bytes_read::total 126112192 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 66108032 # Number of bytes written to this memory -system.physmem.bytes_written::total 66108032 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1969828 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1970503 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1032938 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1032938 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7323 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 21371859 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 21379183 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7323 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7323 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 11206971 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 11206971 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 11206971 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7323 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 21371859 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 32586154 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 5898831348500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 11797662697 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 3008081022 # Number of instructions committed -system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4684368009 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 33534539 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls -system.cpu.num_int_insts 4684368009 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 10688755601 # number of times the integer registers were read -system.cpu.num_int_register_writes 3999841477 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 1226718827 # number of times the CC registers were read -system.cpu.num_cc_register_writes 1355930461 # number of times the CC registers were written -system.cpu.num_mem_refs 1677713084 # number of memory refs -system.cpu.num_load_insts 1239184746 # Number of load instructions -system.cpu.num_store_insts 438528338 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 11797662696.997999 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 248500691 # Number of branches fetched -system.cpu.op_class::No_OpClass 2494522 0.05% 0.05% # Class of executed instruction -system.cpu.op_class::IntAlu 3006647871 64.15% 64.20% # Class of executed instruction -system.cpu.op_class::IntMult 6215 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::IntDiv 904 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.20% # Class of executed instruction -system.cpu.op_class::MemRead 1239184746 26.44% 90.64% # Class of executed instruction -system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 4686862596 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9108581 # number of replacements -system.cpu.dcache.tags.tagsinuse 4084.589706 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9112677 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 183.107599 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 58922805500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4084.589706 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997214 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 898 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2768 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 329 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 3364538845 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 3364538845 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 436638511 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1668600407 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1668600407 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1668600407 # number of overall hits -system.cpu.dcache.overall_hits::total 1668600407 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1889827 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 9112677 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses -system.cpu.dcache.overall_misses::total 9112677 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 152690255000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 152690255000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 64265951000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 64265951000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 216956206000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 216956206000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 216956206000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 216956206000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1239184746 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1239184746 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 438528338 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 438528338 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1677713084 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1677713084 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1677713084 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1677713084 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.004309 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21139.890071 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21139.890071 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34006.261420 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34006.261420 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23808.174700 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23808.174700 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23808.174700 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23808.174700 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 3669049 # number of writebacks -system.cpu.dcache.writebacks::total 3669049 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1889827 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 145467405000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 145467405000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62376124000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 62376124000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 207843529000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 207843529000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 207843529000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 207843529000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004309 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20139.890071 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20139.890071 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33006.261420 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33006.261420 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22808.174700 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22808.174700 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22808.174700 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22808.174700 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 10 # number of replacements -system.cpu.icache.tags.tagsinuse 555.760511 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 4013232207 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 675 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5945529.195556 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 555.760511 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.271367 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.271367 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 665 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 632 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.324707 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 8026466439 # Number of tag accesses -system.cpu.icache.tags.data_accesses 8026466439 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 4013232207 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4013232207 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4013232207 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4013232207 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4013232207 # number of overall hits -system.cpu.icache.overall_hits::total 4013232207 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 675 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 675 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses -system.cpu.icache.overall_misses::total 675 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 42528500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 42528500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 42528500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 42528500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 42528500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 42528500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 4013232882 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 4013232882 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 4013232882 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 4013232882 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 4013232882 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 4013232882 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63005.185185 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 63005.185185 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 63005.185185 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 63005.185185 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 63005.185185 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 63005.185185 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 10 # number of writebacks -system.cpu.icache.writebacks::total 10 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 675 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 675 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41853500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 41853500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41853500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 41853500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41853500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 41853500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62005.185185 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62005.185185 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62005.185185 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 62005.185185 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62005.185185 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 62005.185185 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1938075 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31745.660470 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 16250887 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1970843 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 8.245653 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 320350195000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 11.856683 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.308015 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31708.495772 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000362 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000772 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.967666 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.968801 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 435 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3097 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 786 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 28399 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 147746387 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 147746387 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 3669049 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 3669049 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 10 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 10 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1095863 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1095863 # number of ReadExReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6046986 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 6046986 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.data 7142849 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7142849 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7142849 # number of overall hits -system.cpu.l2cache.overall_hits::total 7142849 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 793964 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 793964 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 675 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 675 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1175864 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 1175864 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 675 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1969828 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1970503 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 675 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1969828 # number of overall misses -system.cpu.l2cache.overall_misses::total 1970503 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 48034822000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 48034822000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 40839500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 40839500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 71139776000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 71139776000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 40839500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 119174598000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 119215437500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 40839500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 119174598000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 119215437500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 3669049 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 3669049 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 10 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 10 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889827 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1889827 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 675 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 675 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7222850 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 7222850 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 675 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9112677 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9113352 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 675 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9112677 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9113352 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.420125 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.420125 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.162798 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.162798 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.216163 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.216222 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.216163 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.216222 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60502.962963 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60502.962963 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500.003402 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500.003402 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60502.962963 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500.002031 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60500.003045 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60502.962963 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500.002031 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60500.003045 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 1032938 # number of writebacks -system.cpu.l2cache.writebacks::total 1032938 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 213 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 213 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 793964 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 793964 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 675 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 675 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1175864 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1175864 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1969828 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1970503 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1969828 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1970503 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 40095182000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 40095182000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 34089500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 34089500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59381136000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59381136000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34089500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 99476318000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 99510407500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34089500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 99476318000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 99510407500 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.420125 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.420125 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162798 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162798 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216163 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.216222 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216163 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.216222 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50502.962963 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50502.962963 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.003402 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.003402 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50502.962963 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.002031 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.003045 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50502.962963 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.002031 # average overall mshr miss latency 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time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4701987 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 10 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6344669 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1889827 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1889827 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 675 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7222850 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1360 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27333935 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27335295 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43840 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818030464 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 818074304 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1938075 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 66108032 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11051427 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000107 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.010359 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11050241 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1186 0.01% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11051427 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12780030500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1012500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13669015500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 3907605 # Total number of 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+system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 1970503 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 1970503 +system.membus.reqLayer0.occupancy 8039359500 +system.membus.reqLayer0.utilization 0.1 +system.membus.respLayer1.occupancy 9852515000 +system.membus.respLayer1.utilization 0.2 ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini index 3c414751d..87b4a600e 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -65,7 +65,7 @@ SSITSize=1024 activity=0 backComSize=5 branchPred=system.cpu.branchPred -cachePorts=200 +cacheStorePorts=200 checker=Null clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 @@ -141,6 +141,7 @@ socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -176,10 +177,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=6 @@ -193,6 +194,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=8 write_buffers=16 @@ -205,15 +207,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu.dstage2_mmu] type=ArmStage2MMU @@ -316,38 +319,52 @@ pipelined=true [system.cpu.fuPool.FUList2] type=FUDesc -children=opList +children=opList0 opList1 count=1 eventq_index=0 -opList=system.cpu.fuPool.FUList2.opList +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 -[system.cpu.fuPool.FUList2.opList] +[system.cpu.fuPool.FUList2.opList0] type=OpDesc eventq_index=0 opClass=MemRead opLat=2 pipelined=true +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=2 +pipelined=true + [system.cpu.fuPool.FUList3] type=FUDesc -children=opList +children=opList0 opList1 count=1 eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 -[system.cpu.fuPool.FUList3.opList] +[system.cpu.fuPool.FUList3.opList0] type=OpDesc eventq_index=0 opClass=MemWrite opLat=2 pipelined=true +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=2 +pipelined=true + [system.cpu.fuPool.FUList4] type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27 count=2 eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 +opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27 [system.cpu.fuPool.FUList4.opList00] type=OpDesc @@ -479,7 +496,7 @@ pipelined=true type=OpDesc eventq_index=0 opClass=SimdFloatMultAcc -opLat=1 +opLat=5 pipelined=true [system.cpu.fuPool.FUList4.opList19] @@ -531,6 +548,20 @@ opClass=FloatMult opLat=4 pipelined=true +[system.cpu.fuPool.FUList4.opList26] +type=OpDesc +eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList4.opList27] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + [system.cpu.icache] type=Cache children=tags @@ -538,10 +569,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=1 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=1 is_read_only=true max_miss_count=0 mshrs=2 @@ -555,6 +586,7 @@ response_latency=1 sequential_access=false size=32768 system=system +tag_latency=1 tags=system.cpu.icache.tags tgts_per_mshr=8 write_buffers=8 @@ -567,15 +599,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=1 default_p_state=UNDEFINED eventq_index=0 -hit_latency=1 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=1 [system.cpu.interrupts] type=ArmInterrupts @@ -594,8 +627,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -606,8 +637,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -670,10 +699,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl +data_latency=12 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=12 is_read_only=false max_miss_count=0 mshrs=16 @@ -687,6 +716,7 @@ response_latency=12 sequential_access=false size=1048576 system=system +tag_latency=12 tags=system.cpu.l2cache.tags tgts_per_mshr=8 write_buffers=8 @@ -729,15 +759,16 @@ type=RandomRepl assoc=16 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=12 default_p_state=UNDEFINED eventq_index=0 -hit_latency=12 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=1048576 +tag_latency=12 [system.cpu.toL2Bus] type=CoherentXBar @@ -773,7 +804,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=twolf smred cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing drivers= @@ -782,14 +813,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/twolf +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/twolf gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr index bbcd9d751..9acbe6def 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr @@ -1,3 +1,5 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout index 8c06d056d..0119254bf 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout @@ -3,21 +3,19 @@ Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/s gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:43:01 -gem5 executing on e108600-lin, pid 17342 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/70.twolf/arm/linux/o3-timing +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 18:24:01 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 59389 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/70.twolf/arm/linux/o3-timing Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 Standard Cell Placement and Global Routing Program Authors: Carl Sechen, Bill Swartz Yale University -info: Increasing stack size by one page. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 @@ -26,4 +24,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 86053034000 because target called exit() +122 123 124 Exiting @ tick 85986203000 because exiting with last active thread context diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 1ab6131a6..407dc44a0 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,1233 +1,1233 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.085986 # Number of seconds simulated -sim_ticks 85986203000 # Number of ticks simulated -final_tick 85986203000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 210936 # Simulator instruction rate (inst/s) -host_op_rate 222361 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 105265513 # Simulator tick rate (ticks/s) -host_mem_usage 272504 # Number of bytes of host memory used -host_seconds 816.85 # Real time elapsed on the host -sim_insts 172303022 # Number of instructions simulated -sim_ops 181635954 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 651776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 193408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 71680 # Number of bytes read from this memory -system.physmem.bytes_read::total 916864 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 651776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 651776 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 10184 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3022 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 1120 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14326 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 7580007 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2249291 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 833622 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10662920 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7580007 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7580007 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7580007 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2249291 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 833622 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10662920 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 14327 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 14327 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 916928 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 916928 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1379 # Per bank write bursts -system.physmem.perBankRdBursts::1 501 # Per bank write bursts -system.physmem.perBankRdBursts::2 5100 # Per bank write bursts -system.physmem.perBankRdBursts::3 815 # Per bank write bursts -system.physmem.perBankRdBursts::4 2265 # Per bank write bursts -system.physmem.perBankRdBursts::5 427 # Per bank write bursts -system.physmem.perBankRdBursts::6 394 # Per bank write bursts -system.physmem.perBankRdBursts::7 623 # Per bank write bursts -system.physmem.perBankRdBursts::8 270 # Per bank write bursts -system.physmem.perBankRdBursts::9 230 # Per bank write bursts -system.physmem.perBankRdBursts::10 354 # Per bank write bursts -system.physmem.perBankRdBursts::11 345 # Per bank write bursts -system.physmem.perBankRdBursts::12 321 # Per bank write bursts -system.physmem.perBankRdBursts::13 266 # Per bank write bursts -system.physmem.perBankRdBursts::14 239 # Per bank write bursts -system.physmem.perBankRdBursts::15 798 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 85986194000 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 14327 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 12781 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1074 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 181 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 85 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 42 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 8483 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 107.969350 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 86.508882 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 122.734500 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 5897 69.52% 69.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 2092 24.66% 94.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 251 2.96% 97.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 65 0.77% 97.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 38 0.45% 98.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 36 0.42% 98.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 15 0.18% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 10 0.12% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 79 0.93% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 8483 # Bytes accessed per row activation -system.physmem.totQLat 1497477800 # Total ticks spent queuing -system.physmem.totMemAccLat 1766109050 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 71635000 # Total ticks spent in databus transfers -system.physmem.avgQLat 104521.38 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 123271.38 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 10.66 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 10.66 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.08 # Data bus utilization in percentage -system.physmem.busUtilRead 0.08 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 5838 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 40.75 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 6001688.70 # Average gap between requests -system.physmem.pageHitRate 40.75 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 51557940 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 27392310 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 82138560 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5188176240.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1121049780 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 275286240 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 12230933460 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 8389841280 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 9251896980 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 36621408690 # Total energy per rank (pJ) -system.physmem_0.averagePower 425.898657 # Core power per rank (mW) -system.physmem_0.totalIdleTime 82802255264 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 532741000 # Time in different power states -system.physmem_0.memoryStateTime::REF 2206324000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 34133171250 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 21848572364 # Time in different power states -system.physmem_0.memoryStateTime::ACT 443169236 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 26822225150 # Time in different power states -system.physmem_1.actEnergy 9046380 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 4800675 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 20149080 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 880164480.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 198118890 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 50592480 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 1982659500 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 1381296480 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 18795083175 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 23322152130 # Total energy per rank (pJ) -system.physmem_1.averagePower 271.231327 # Core power per rank (mW) -system.physmem_1.totalIdleTime 85419499755 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 100592000 # Time in different power states -system.physmem_1.memoryStateTime::REF 374546000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 77474388250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 3597111150 # Time in different power states -system.physmem_1.memoryStateTime::ACT 91565245 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 4348000355 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 85644201 # Number of BP lookups -system.cpu.branchPred.condPredicted 68263451 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5948841 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 39900262 # Number of BTB lookups -system.cpu.branchPred.BTBHits 38156956 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.630841 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3658994 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 81907 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 654149 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 629298 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 24851 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 40566 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 85986203000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 171972407 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5684699 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 346733793 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85644201 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 42445248 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 158074641 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 11911485 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 4331 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingQuiesceStallCycles 80 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 4750 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 78152122 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 17905 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 169724243 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.137034 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.057596 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 18311667 10.79% 10.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 29948653 17.65% 28.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31633861 18.64% 47.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 89830062 52.93% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 169724243 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.498011 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.016218 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17545924 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 18077628 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 121579812 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6764631 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5756248 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 32661376 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 214759 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 304427843 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 27289068 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5756248 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37507593 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8946109 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 602389 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 108088153 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8823751 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 276998119 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13097154 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3089202 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 850461 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2596711 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 40764 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 26854 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 480912034 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1185877305 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 296009785 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3004340 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 187935105 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 23572 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23567 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13428642 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 33801265 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14384966 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2539582 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1819756 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 263460878 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 45929 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 214221426 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5142742 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 81870853 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 215931448 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 713 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 169724243 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.262173 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.018049 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 53012533 31.23% 31.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 36041444 21.24% 52.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 65469642 38.57% 91.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 13608265 8.02% 99.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1546158 0.91% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 45935 0.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 266 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 169724243 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35637562 66.14% 66.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 153239 0.28% 66.43% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 66.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 66.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 66.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 66.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 1065 0.00% 66.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 35742 0.07% 66.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 263 0.00% 66.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 559 0.00% 66.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 40182 0.07% 66.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 13886588 25.77% 92.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3846845 7.14% 99.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 141772 0.26% 99.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 136229 0.25% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 166877725 77.90% 77.90% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 919560 0.43% 78.33% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 78.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 78.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33017 0.02% 78.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 165187 0.08% 78.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 245719 0.11% 78.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 460300 0.21% 78.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206641 0.10% 78.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 318 0.00% 78.92% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 31220842 14.57% 93.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13220710 6.17% 99.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 576371 0.27% 99.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 147395 0.07% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 214221426 # Type of FU issued -system.cpu.iq.rate 1.245673 # Inst issue rate -system.cpu.iq.fu_busy_cnt 53880251 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.251517 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 653198075 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 343375917 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 204156399 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3992013 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2008700 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1806249 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 265928183 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2173494 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1586831 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5905121 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6947 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 7000 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1740332 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 25012 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 810 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5756248 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5611049 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 173372 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 263527171 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 33801265 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14384966 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23521 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3789 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 166382 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 7000 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3130012 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3255540 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6385552 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 206995589 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 30591856 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7225837 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 20364 # number of nop insts executed -system.cpu.iew.exec_refs 43730352 # number of memory reference insts executed -system.cpu.iew.exec_branches 44853428 # Number of branches executed -system.cpu.iew.exec_stores 13138496 # Number of stores executed -system.cpu.iew.exec_rate 1.203656 # Inst execution rate -system.cpu.iew.wb_sent 206269583 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 205962648 # cumulative count of insts written-back -system.cpu.iew.wb_producers 129302452 # num instructions producing a value -system.cpu.iew.wb_consumers 221536410 # num instructions consuming a value -system.cpu.iew.wb_rate 1.197649 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.583662 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 68402964 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 5749347 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158452610 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.146402 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.651768 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 73893836 46.63% 46.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 41104048 25.94% 72.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 22555911 14.24% 86.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9496527 5.99% 92.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3557786 2.25% 95.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2129951 1.34% 96.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1320929 0.83% 97.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1010558 0.64% 97.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3383064 2.14% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158452610 # Number of insts commited each cycle -system.cpu.commit.committedInsts 172317410 # Number of instructions committed -system.cpu.commit.committedOps 181650342 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 40540778 # Number of memory references committed -system.cpu.commit.loads 27896144 # Number of loads committed -system.cpu.commit.membars 22408 # Number of memory barriers committed -system.cpu.commit.branches 40300312 # Number of branches committed -system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. -system.cpu.commit.int_insts 143085667 # Number of committed integer instructions. -system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 138987813 76.51% 76.51% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 77.01% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 77.01% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 77.01% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 77.01% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 77.01% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 77.01% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 77.01% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 77.01% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 77.01% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 77.01% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 77.01% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 77.01% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 77.01% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 77.01% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 77.01% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 77.01% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 77.01% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 77.01% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 77.01% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 77.01% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 32754 0.02% 77.03% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 77.03% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 154829 0.09% 77.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 238880 0.13% 77.25% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 76016 0.04% 77.29% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 437591 0.24% 77.53% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 200806 0.11% 77.64% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 71617 0.04% 77.68% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 27348059 15.06% 92.74% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 12498388 6.88% 99.62% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 548085 0.30% 99.92% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 146246 0.08% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 181650342 # Class of committed instruction -system.cpu.commit.bw_lim_events 3383064 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 405117651 # The number of ROB reads -system.cpu.rob.rob_writes 511394543 # The number of ROB writes -system.cpu.timesIdled 9924 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 2248164 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 172303022 # Number of Instructions Simulated -system.cpu.committedOps 181635954 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.998081 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.998081 # CPI: Total CPI of All Threads -system.cpu.ipc 1.001922 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.001922 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 218599432 # number of integer regfile reads -system.cpu.int_regfile_writes 114087616 # number of integer regfile writes -system.cpu.fp_regfile_reads 2903991 # number of floating regfile reads -system.cpu.fp_regfile_writes 2441715 # number of floating regfile writes -system.cpu.cc_regfile_reads 707769294 # number of cc regfile reads -system.cpu.cc_regfile_writes 229397390 # number of cc regfile writes -system.cpu.misc_regfile_reads 57427586 # number of misc regfile reads -system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 72391 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.400200 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40997604 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 72903 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 562.358257 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 554902500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.400200 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998829 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998829 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 230 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 44 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 82292817 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 82292817 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 28611296 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28611296 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12341384 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12341384 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 362 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 362 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22154 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22154 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40952680 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40952680 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40953042 # number of overall hits -system.cpu.dcache.overall_hits::total 40953042 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89081 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89081 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 22903 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 22903 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 117 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 117 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 253 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 253 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 111984 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 111984 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 112101 # number of overall misses -system.cpu.dcache.overall_misses::total 112101 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1981259500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1981259500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 246570499 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 246570499 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2257000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 2257000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 2227829999 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 2227829999 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 2227829999 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 2227829999 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28700377 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28700377 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 479 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 479 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41064664 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41064664 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41065143 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41065143 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003104 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003104 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001852 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001852 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.244259 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.244259 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011291 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011291 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002727 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002727 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002730 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002730 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22241.100796 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22241.100796 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10765.860324 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10765.860324 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8920.948617 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8920.948617 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19894.181303 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19894.181303 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19873.417713 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19873.417713 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 180 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 11209 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 865 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 90 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 12.958382 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 72391 # number of writebacks -system.cpu.dcache.writebacks::total 72391 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24849 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 24849 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14345 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 14345 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 253 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 253 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 39194 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 39194 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 39194 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 39194 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64232 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 64232 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8558 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 8558 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 114 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 114 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 72790 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 72790 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 72904 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 72904 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1056234000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1056234000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 88380499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 88380499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 977000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 977000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1144614499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 1144614499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1145591499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 1145591499 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002238 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002238 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000692 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000692 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.237996 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.237996 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001773 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001773 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001775 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001775 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16444.046581 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16444.046581 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10327.237556 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10327.237556 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8570.175439 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8570.175439 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15724.886647 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15724.886647 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15713.698823 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15713.698823 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 53106 # number of replacements -system.cpu.icache.tags.tagsinuse 510.578015 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 78094905 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 53618 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1456.505371 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 85215430500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.578015 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997223 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997223 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 49 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 156357779 # Number of tag accesses -system.cpu.icache.tags.data_accesses 156357779 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 78094905 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 78094905 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 78094905 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 78094905 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 78094905 # number of overall hits -system.cpu.icache.overall_hits::total 78094905 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 57175 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 57175 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 57175 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 57175 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 57175 # number of overall misses -system.cpu.icache.overall_misses::total 57175 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2239186435 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2239186435 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2239186435 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2239186435 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2239186435 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2239186435 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 78152080 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 78152080 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 78152080 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 78152080 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 78152080 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 78152080 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000732 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000732 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000732 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000732 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000732 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000732 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39163.733013 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 39163.733013 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 39163.733013 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 39163.733013 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 39163.733013 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 39163.733013 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 91615 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 88 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3140 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 29.176752 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 29.333333 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 53106 # number of writebacks -system.cpu.icache.writebacks::total 53106 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3554 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3554 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3554 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3554 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3554 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3554 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 53621 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 53621 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 53621 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 53621 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 53621 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 53621 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2047106952 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2047106952 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2047106952 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2047106952 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2047106952 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2047106952 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000686 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000686 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000686 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 38177.336342 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 38177.336342 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 38177.336342 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 38177.336342 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38177.336342 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 38177.336342 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 9132 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 9132 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue -system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped -system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 1308 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 1811.625085 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 98153 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2844 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 34.512307 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 1727.578627 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 84.046457 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.105443 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.005130 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.110573 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 138 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 2706 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 15 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 46 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 77 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 283 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1128 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 205 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 955 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.008423 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.165161 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3980963 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3980963 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 64558 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 64558 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 50469 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 50469 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 8390 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 8390 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 43430 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 43430 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 61482 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 61482 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 43430 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 69872 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 113302 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 43430 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 69872 # number of overall hits -system.cpu.l2cache.overall_hits::total 113302 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 236 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 236 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10190 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 10190 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2795 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 2795 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 10190 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3031 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 13221 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 10190 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3031 # number of overall misses -system.cpu.l2cache.overall_misses::total 13221 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 21033000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 21033000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1708556000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 1708556000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 553419500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 553419500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1708556000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 574452500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 2283008500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1708556000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 574452500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 2283008500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 64558 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 64558 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 50469 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 50469 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 8626 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 8626 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 53620 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 53620 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 64277 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 64277 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 53620 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 72903 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 126523 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 53620 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 72903 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 126523 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.027359 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.027359 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.190041 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.190041 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043484 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043484 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.190041 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.041576 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.104495 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.190041 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.041576 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.104495 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89122.881356 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89122.881356 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 167669.872424 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 167669.872424 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 198003.398927 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 198003.398927 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 167669.872424 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 189525.734081 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 172680.470464 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 167669.872424 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 189525.734081 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 172680.470464 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 1 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 5 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 5 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 8 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 8 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1986 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 1986 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 235 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 235 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10185 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10185 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2787 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2787 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 10185 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3022 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 13207 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 10185 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3022 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1986 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 15193 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 99174661 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 99174661 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 16000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 16000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 19399000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 19399000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1646592500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1646592500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 536158000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 536158000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1646592500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 555557000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 2202149500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1646592500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 555557000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 99174661 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 2301324161 # number of overall MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027243 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027243 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.189948 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.189948 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043359 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043359 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.189948 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.041452 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.104384 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.189948 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.041452 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.120081 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 49936.888721 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 49936.888721 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82548.936170 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82548.936170 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 161668.384880 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 161668.384880 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 192378.184428 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 192378.184428 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 161668.384880 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 183837.524818 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 166741.084273 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 161668.384880 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 183837.524818 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 49936.888721 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 151472.662476 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 252022 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 125518 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10474 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 866 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 865 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 117896 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 64558 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 60939 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 2337 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 8626 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 8626 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 53621 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 64277 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 160345 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218199 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 378544 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6830336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9298816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 16129152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2338 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 64 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 128862 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.088172 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.283573 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 117501 91.18% 91.18% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 11360 8.82% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 128862 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 251508000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 80437981 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 109359491 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 14328 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 10478 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 14090 # Transaction distribution -system.membus.trans_dist::UpgradeReq 1 # Transaction distribution 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+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 19399000 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 19399000 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1646592500 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1646592500 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 536158000 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 536158000 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1646592500 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 555557000 +system.cpu.l2cache.demand_mshr_miss_latency::total 2202149500 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1646592500 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 555557000 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 99174661 +system.cpu.l2cache.overall_mshr_miss_latency::total 2301324161 +system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf +system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027243 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027243 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.189948 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.189948 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043359 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043359 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.189948 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.041452 +system.cpu.l2cache.demand_mshr_miss_rate::total 0.104384 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.189948 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.041452 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf +system.cpu.l2cache.overall_mshr_miss_rate::total 0.120081 +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 49936.888721 +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 49936.888721 +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16000 +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16000 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82548.936170 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82548.936170 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 161668.384880 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 161668.384880 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 192378.184428 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 192378.184428 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 161668.384880 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 183837.524818 +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 166741.084273 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 161668.384880 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 183837.524818 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 49936.888721 +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 151472.662476 +system.cpu.toL2Bus.snoop_filter.tot_requests 252022 +system.cpu.toL2Bus.snoop_filter.hit_single_requests 125518 +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10474 +system.cpu.toL2Bus.snoop_filter.tot_snoops 866 +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 865 +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 85986203000 +system.cpu.toL2Bus.trans_dist::ReadResp 117896 +system.cpu.toL2Bus.trans_dist::WritebackDirty 64558 +system.cpu.toL2Bus.trans_dist::WritebackClean 60939 +system.cpu.toL2Bus.trans_dist::HardPFReq 2337 +system.cpu.toL2Bus.trans_dist::UpgradeReq 1 +system.cpu.toL2Bus.trans_dist::UpgradeResp 1 +system.cpu.toL2Bus.trans_dist::ReadExReq 8626 +system.cpu.toL2Bus.trans_dist::ReadExResp 8626 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 53621 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 64277 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 160345 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218199 +system.cpu.toL2Bus.pkt_count::total 378544 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6830336 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9298816 +system.cpu.toL2Bus.pkt_size::total 16129152 +system.cpu.toL2Bus.snoops 2338 +system.cpu.toL2Bus.snoopTraffic 64 +system.cpu.toL2Bus.snoop_fanout::samples 128862 +system.cpu.toL2Bus.snoop_fanout::mean 0.088172 +system.cpu.toL2Bus.snoop_fanout::stdev 0.283573 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 117501 91.18% 91.18% +system.cpu.toL2Bus.snoop_fanout::1 11360 8.82% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 2 +system.cpu.toL2Bus.snoop_fanout::total 128862 +system.cpu.toL2Bus.reqLayer0.occupancy 251508000 +system.cpu.toL2Bus.reqLayer0.utilization 0.3 +system.cpu.toL2Bus.respLayer0.occupancy 80437981 +system.cpu.toL2Bus.respLayer0.utilization 0.1 +system.cpu.toL2Bus.respLayer1.occupancy 109359491 +system.cpu.toL2Bus.respLayer1.utilization 0.1 +system.membus.snoop_filter.tot_requests 14328 +system.membus.snoop_filter.hit_single_requests 10478 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 85986203000 +system.membus.trans_dist::ReadResp 14090 +system.membus.trans_dist::UpgradeReq 1 +system.membus.trans_dist::ReadExReq 235 +system.membus.trans_dist::ReadExResp 235 +system.membus.trans_dist::ReadSharedReq 14092 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 28653 +system.membus.pkt_count::total 28653 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 916800 +system.membus.pkt_size::total 916800 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 14328 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 14328 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 14328 +system.membus.reqLayer0.occupancy 18011178 +system.membus.reqLayer0.utilization 0.0 +system.membus.respLayer1.occupancy 77254535 +system.membus.respLayer1.utilization 0.1 ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout index 2531961c1..4f7383f25 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/s gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 30 2017 17:14:30 -gem5 started Mar 30 2017 17:14:43 -gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 80103 +gem5 compiled Mar 31 2017 16:17:52 +gem5 started Mar 31 2017 16:18:04 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 50433 command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/70.twolf/x86/linux/o3-timing Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav @@ -24,4 +24,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 102720088500 because target called exit() +122 123 124 Exiting @ tick 102720088500 because exiting with last active thread context diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index c833a13ad..0cd025b0c 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.102720 sim_ticks 102720088500 final_tick 102720088500 sim_freq 1000000000000 -host_inst_rate 110078 -host_op_rate 184500 -host_tick_rate 85614304 -host_mem_usage 318036 -host_seconds 1199.80 +host_inst_rate 108111 +host_op_rate 181205 +host_tick_rate 84085065 +host_mem_usage 318048 +host_seconds 1221.62 sim_insts 132071192 sim_ops 221363384 system.voltage_domain.voltage 1 @@ -290,7 +290,7 @@ system.cpu.fetch.Insts 415890076 system.cpu.fetch.Branches 40475084 system.cpu.fetch.predictedBranches 13128503 system.cpu.fetch.Cycles 151898082 -system.cpu.fetch.SquashCycles 14677483 +system.cpu.fetch.SquashCycles 14677482 system.cpu.fetch.TlbCycles 200 system.cpu.fetch.MiscStallCycles 5835 system.cpu.fetch.PendingTrapStallCycles 64355 @@ -352,7 +352,7 @@ system.cpu.iq.iqInstsAdded 486700641 system.cpu.iq.iqNonSpecInstsAdded 63617 system.cpu.iq.iqInstsIssued 336591190 system.cpu.iq.iqSquashedInstsIssued 1075815 -system.cpu.iq.iqSquashedInstsExamined 265400874 +system.cpu.iq.iqSquashedInstsExamined 265400873 system.cpu.iq.iqSquashedOperandsExamined 520101528 system.cpu.iq.iqSquashedNonSpecRemoved 62372 system.cpu.iq.issued_per_cycle::samples 205201489 @@ -453,7 +453,7 @@ system.cpu.iq.rate 1.638390 system.cpu.iq.fu_busy_cnt 3927876 system.cpu.iq.fu_busy_rate 0.011670 system.cpu.iq.int_inst_queue_reads 875282503 -system.cpu.iq.int_inst_queue_writes 737961959 +system.cpu.iq.int_inst_queue_writes 737961958 system.cpu.iq.int_inst_queue_wakeup_accesses 314539840 system.cpu.iq.fp_inst_queue_reads 8105057 system.cpu.iq.fp_inst_queue_writes 15024545 @@ -503,11 +503,11 @@ system.cpu.iew.wb_fanout 0.588199 system.cpu.commit.commitSquashedInsts 265431246 system.cpu.commit.commitNonSpecStalls 1245 system.cpu.commit.branchMispredicts 6620627 -system.cpu.commit.committed_per_cycle::samples 163282867 +system.cpu.commit.committed_per_cycle::samples 163282868 system.cpu.commit.committed_per_cycle::mean 1.355705 system.cpu.commit.committed_per_cycle::stdev 1.936594 system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% -system.cpu.commit.committed_per_cycle::0 66681317 40.84% 40.84% +system.cpu.commit.committed_per_cycle::0 66681318 40.84% 40.84% system.cpu.commit.committed_per_cycle::1 54877393 33.61% 74.45% system.cpu.commit.committed_per_cycle::2 13218924 8.10% 82.54% system.cpu.commit.committed_per_cycle::3 10716776 6.56% 89.11% @@ -519,7 +519,7 @@ system.cpu.commit.committed_per_cycle::8 6989165 4.28% 100.00% system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% system.cpu.commit.committed_per_cycle::min_value 0 system.cpu.commit.committed_per_cycle::max_value 8 -system.cpu.commit.committed_per_cycle::total 163282867 +system.cpu.commit.committed_per_cycle::total 163282868 system.cpu.commit.committedInsts 132071192 system.cpu.commit.committedOps 221363384 system.cpu.commit.swp_count 0 @@ -570,8 +570,8 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% system.cpu.commit.op_class_0::total 221363384 system.cpu.commit.bw_lim_events 6989165 -system.cpu.rob.rob_reads 643088332 -system.cpu.rob.rob_writes 1015902506 +system.cpu.rob.rob_reads 643088333 +system.cpu.rob.rob_writes 1015902505 system.cpu.timesIdled 2802 system.cpu.idleCycles 238689 system.cpu.committedInsts 132071192 diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini index fc8ce75af..b967ed849 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini @@ -118,6 +118,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system threadPolicy=RoundRobin tracer=system.cpu.tracer @@ -155,10 +156,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -172,6 +173,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -184,15 +186,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dstage2_mmu] type=ArmStage2MMU @@ -404,9 +407,9 @@ timings=system.cpu.executeFuncUnits.funcUnits4.timings [system.cpu.executeFuncUnits.funcUnits4.opClasses] type=MinorOpClassSet -children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 +children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 opClasses26 opClasses27 eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] type=MinorOpClass @@ -426,116 +429,126 @@ opClass=FloatCvt [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] type=MinorOpClass eventq_index=0 -opClass=FloatMult +opClass=FloatMisc [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] type=MinorOpClass eventq_index=0 -opClass=FloatDiv +opClass=FloatMult [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] type=MinorOpClass eventq_index=0 -opClass=FloatSqrt +opClass=FloatMultAcc [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] type=MinorOpClass eventq_index=0 -opClass=SimdAdd +opClass=FloatDiv [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] type=MinorOpClass eventq_index=0 -opClass=SimdAddAcc +opClass=FloatSqrt [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] type=MinorOpClass eventq_index=0 -opClass=SimdAlu +opClass=SimdAdd [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] type=MinorOpClass eventq_index=0 -opClass=SimdCmp +opClass=SimdAddAcc [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] type=MinorOpClass eventq_index=0 -opClass=SimdCvt +opClass=SimdAlu [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] type=MinorOpClass eventq_index=0 -opClass=SimdMisc +opClass=SimdCmp [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] type=MinorOpClass eventq_index=0 -opClass=SimdMult +opClass=SimdCvt [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] type=MinorOpClass eventq_index=0 -opClass=SimdMultAcc +opClass=SimdMisc [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] type=MinorOpClass eventq_index=0 -opClass=SimdShift +opClass=SimdMult [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] type=MinorOpClass eventq_index=0 -opClass=SimdShiftAcc +opClass=SimdMultAcc [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] type=MinorOpClass eventq_index=0 -opClass=SimdSqrt +opClass=SimdShift [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] type=MinorOpClass eventq_index=0 -opClass=SimdFloatAdd +opClass=SimdShiftAcc [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] type=MinorOpClass eventq_index=0 -opClass=SimdFloatAlu +opClass=SimdSqrt [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] type=MinorOpClass eventq_index=0 -opClass=SimdFloatCmp +opClass=SimdFloatAdd [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] type=MinorOpClass eventq_index=0 -opClass=SimdFloatCvt +opClass=SimdFloatAlu [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] type=MinorOpClass eventq_index=0 -opClass=SimdFloatDiv +opClass=SimdFloatCmp [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] type=MinorOpClass eventq_index=0 -opClass=SimdFloatMisc +opClass=SimdFloatCvt [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] type=MinorOpClass eventq_index=0 -opClass=SimdFloatMult +opClass=SimdFloatDiv [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] type=MinorOpClass eventq_index=0 -opClass=SimdFloatMultAcc +opClass=SimdFloatMisc [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] type=MinorOpClass eventq_index=0 +opClass=SimdFloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27] +type=MinorOpClass +eventq_index=0 opClass=SimdFloatSqrt [system.cpu.executeFuncUnits.funcUnits4.timings] @@ -569,9 +582,9 @@ timings=system.cpu.executeFuncUnits.funcUnits5.timings [system.cpu.executeFuncUnits.funcUnits5.opClasses] type=MinorOpClassSet -children=opClasses0 opClasses1 +children=opClasses0 opClasses1 opClasses2 opClasses3 eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3 [system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] type=MinorOpClass @@ -583,6 +596,16 @@ type=MinorOpClass eventq_index=0 opClass=MemWrite +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2] +type=MinorOpClass +eventq_index=0 +opClass=FloatMemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3] +type=MinorOpClass +eventq_index=0 +opClass=FloatMemWrite + [system.cpu.executeFuncUnits.funcUnits5.timings] type=MinorFUTiming children=opClasses @@ -635,10 +658,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -652,6 +675,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -664,15 +688,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=ArmInterrupts @@ -691,8 +716,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -703,8 +726,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -767,10 +788,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -784,6 +805,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -796,15 +818,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -840,7 +863,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -849,14 +872,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/arm/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/arm/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simerr b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simerr index bbcd9d751..707fed98b 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simerr +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simerr @@ -1,3 +1,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simout index 6a285f351..0722728b6 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:42:59 -gem5 executing on e108600-lin, pid 17319 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/arm/linux/minor-timing +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 17:56:13 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54225 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/arm/linux/minor-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 32719500 because target called exit() +Exiting @ tick 32617500 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index 218cf1458..4b0e86c1b 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -1,878 +1,878 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000033 # Number of seconds simulated -sim_ticks 32617500 # Number of ticks simulated -final_tick 32617500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 159604 # Simulator instruction rate (inst/s) -host_op_rate 186772 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1129633158 # Simulator tick rate (ticks/s) -host_mem_usage 268376 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -sim_insts 4605 # Number of instructions simulated -sim_ops 5391 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 19456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7424 # Number of bytes read from this memory -system.physmem.bytes_read::total 26880 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 19456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 19456 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 304 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory -system.physmem.num_reads::total 420 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 596489614 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 227607879 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 824097494 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 596489614 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 596489614 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 596489614 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 227607879 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 824097494 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 420 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 420 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26880 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26880 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 91 # Per bank write bursts -system.physmem.perBankRdBursts::1 52 # Per bank write bursts -system.physmem.perBankRdBursts::2 20 # Per bank write bursts -system.physmem.perBankRdBursts::3 43 # Per bank write bursts -system.physmem.perBankRdBursts::4 21 # Per bank write bursts -system.physmem.perBankRdBursts::5 41 # Per bank write bursts -system.physmem.perBankRdBursts::6 36 # Per bank write bursts -system.physmem.perBankRdBursts::7 12 # Per bank write bursts -system.physmem.perBankRdBursts::8 5 # Per bank write bursts -system.physmem.perBankRdBursts::9 6 # Per bank write bursts -system.physmem.perBankRdBursts::10 27 # Per bank write bursts -system.physmem.perBankRdBursts::11 42 # Per bank write bursts -system.physmem.perBankRdBursts::12 9 # Per bank write bursts -system.physmem.perBankRdBursts::13 8 # Per bank write bursts -system.physmem.perBankRdBursts::14 0 # Per bank write bursts -system.physmem.perBankRdBursts::15 7 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 32519500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 420 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 342 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 70 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 70 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 373.942857 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 254.068407 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 318.910277 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13 18.57% 18.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 19 27.14% 45.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 11 15.71% 61.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8 11.43% 72.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 4.29% 77.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 2.86% 80.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5 7.14% 87.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 2.86% 90.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7 10.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 70 # Bytes accessed per row activation -system.physmem.totQLat 5148000 # Total ticks spent queuing -system.physmem.totMemAccLat 13023000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2100000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12257.14 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31007.14 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 824.10 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 824.10 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 6.44 # Data bus utilization in percentage -system.physmem.busUtilRead 6.44 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.23 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 346 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.38 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 77427.38 # Average gap between requests -system.physmem.pageHitRate 82.38 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 349860 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 174570 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2256240 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 2458560.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4399260 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 59520 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 10401930 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 1440 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 20101380 # Total energy per rank (pJ) -system.physmem_0.averagePower 616.275926 # Core power per rank (mW) -system.physmem_0.totalIdleTime 22764750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 30000 # Time in different power states -system.physmem_0.memoryStateTime::REF 1040000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 3750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 8725000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 22818750 # Time in different power states -system.physmem_1.actEnergy 178500 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 91080 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 742560 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2458560.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1740780 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 96960 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 12060060 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 806400 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 18174900 # Total energy per rank (pJ) -system.physmem_1.averagePower 557.213152 # Core power per rank (mW) -system.physmem_1.totalIdleTime 28278000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 141000 # Time in different power states -system.physmem_1.memoryStateTime::REF 1040000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 2099750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 2887500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 26449250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 1965 # Number of BP lookups -system.cpu.branchPred.condPredicted 1175 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 349 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1668 # Number of BTB lookups -system.cpu.branchPred.BTBHits 324 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 19.424460 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 220 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 137 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 8 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 129 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 32617500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 65235 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 4605 # Number of instructions committed -system.cpu.committedOps 5391 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1187 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 14.166124 # CPI: cycles per instruction -system.cpu.ipc 0.070591 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.op_class_0::IntAlu 3419 63.42% 63.42% # Class of committed instruction -system.cpu.op_class_0::IntMult 4 0.07% 63.49% # Class of committed instruction -system.cpu.op_class_0::IntDiv 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::FloatMult 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::FloatMultAcc 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 3 0.06% 63.55% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 63.55% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 63.55% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 63.55% # Class of committed instruction -system.cpu.op_class_0::MemRead 1027 19.05% 82.60% # Class of committed instruction -system.cpu.op_class_0::MemWrite 922 17.10% 99.70% # Class of committed instruction -system.cpu.op_class_0::FloatMemRead 0 0.00% 99.70% # Class of committed instruction -system.cpu.op_class_0::FloatMemWrite 16 0.30% 100.00% # Class of committed instruction -system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 5391 # Class of committed instruction -system.cpu.tickCycles 10712 # Number of cycles that the object actually ticked -system.cpu.idleCycles 54523 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.828759 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1918 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.136986 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.828759 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021198 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021198 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4334 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4334 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1050 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1050 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1896 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1896 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1896 # number of overall hits -system.cpu.dcache.overall_hits::total 1896 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 109 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 109 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 67 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 67 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 176 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 176 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 176 # number of overall misses -system.cpu.dcache.overall_misses::total 176 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7434500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7434500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5464500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5464500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12899000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12899000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12899000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12899000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1159 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1159 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2072 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2072 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2072 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2072 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.094047 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.094047 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.073384 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.084942 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.084942 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.084942 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.084942 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68206.422018 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68206.422018 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81559.701493 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 81559.701493 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73289.772727 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73289.772727 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73289.772727 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73289.772727 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 24 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 24 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 30 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 30 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 30 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 30 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7061000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7061000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3488000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3488000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10549000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10549000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10549000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10549000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088870 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088870 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070463 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.070463 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070463 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.070463 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68553.398058 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68553.398058 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81116.279070 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81116.279070 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72253.424658 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72253.424658 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72253.424658 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72253.424658 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 4 # number of replacements -system.cpu.icache.tags.tagsinuse 162.068358 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1966 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 321 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.124611 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 162.068358 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.079135 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.079135 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 317 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 219 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.154785 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4895 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4895 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1966 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1966 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1966 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1966 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1966 # number of overall hits -system.cpu.icache.overall_hits::total 1966 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 321 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 321 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 321 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 321 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 321 # number of overall misses -system.cpu.icache.overall_misses::total 321 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25981000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25981000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25981000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25981000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25981000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25981000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2287 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2287 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2287 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2287 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2287 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2287 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.140359 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.140359 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.140359 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.140359 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.140359 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.140359 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80937.694704 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 80937.694704 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 80937.694704 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 80937.694704 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 80937.694704 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 80937.694704 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 4 # number of writebacks -system.cpu.icache.writebacks::total 4 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 321 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 321 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 321 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 321 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 321 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 321 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25660000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 25660000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25660000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 25660000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25660000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 25660000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.140359 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.140359 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.140359 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.140359 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.140359 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.140359 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79937.694704 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79937.694704 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79937.694704 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 79937.694704 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79937.694704 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 79937.694704 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 223.784324 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 42 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 420 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.100000 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.947993 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 68.836332 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004729 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002101 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006829 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 420 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012817 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4180 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4180 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackClean_hits::writebacks 3 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 3 # number of WritebackClean hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 17 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 22 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 22 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 22 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 22 # number of overall hits -system.cpu.l2cache.overall_hits::total 39 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 304 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 304 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 81 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 81 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 304 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 124 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 428 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 304 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 124 # number of overall misses -system.cpu.l2cache.overall_misses::total 428 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3423500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3423500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 24983000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 24983000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6647000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 6647000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 24983000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10070500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 35053500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 24983000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10070500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 35053500 # number of overall miss cycles -system.cpu.l2cache.WritebackClean_accesses::writebacks 3 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 3 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 321 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 321 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 103 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 103 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 321 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 467 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 321 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 467 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.947040 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.947040 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.786408 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.786408 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.947040 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.849315 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.916488 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947040 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.916488 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79616.279070 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79616.279070 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82180.921053 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82180.921053 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82061.728395 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82061.728395 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82180.921053 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81213.709677 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 81900.700935 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82180.921053 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81213.709677 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 81900.700935 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 8 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 8 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 8 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 304 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 304 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 73 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 73 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 116 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 420 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 304 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 116 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 420 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2993500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2993500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 21943000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 21943000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5321000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5321000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21943000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8314500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30257500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21943000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8314500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30257500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947040 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947040 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.708738 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.708738 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947040 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.899358 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947040 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.899358 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69616.279070 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69616.279070 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72180.921053 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72180.921053 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72890.410959 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72890.410959 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72180.921053 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71676.724138 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72041.666667 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72180.921053 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71676.724138 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72041.666667 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 471 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 50 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 4 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 321 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 646 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 938 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20800 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 30144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 467 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.100642 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.301177 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 420 89.94% 89.94% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 47 10.06% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 467 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 239500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 481500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 222992 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 420 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 377 # Transaction distribution -system.membus.trans_dist::ReadExReq 43 # Transaction distribution -system.membus.trans_dist::ReadExResp 43 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 377 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 840 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 840 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26880 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26880 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 420 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 420 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 420 # Request fanout histogram -system.membus.reqLayer0.occupancy 489000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 2233000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.8 # Layer utilization (%) +sim_seconds 0.000033 +sim_ticks 32617500 +final_tick 32617500 +sim_freq 1000000000000 +host_inst_rate 73373 +host_op_rate 85866 +host_tick_rate 519360115 +host_mem_usage 279788 +host_seconds 0.06 +sim_insts 4605 +sim_ops 5391 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 32617500 +system.physmem.bytes_read::cpu.inst 19456 +system.physmem.bytes_read::cpu.data 7424 +system.physmem.bytes_read::total 26880 +system.physmem.bytes_inst_read::cpu.inst 19456 +system.physmem.bytes_inst_read::total 19456 +system.physmem.num_reads::cpu.inst 304 +system.physmem.num_reads::cpu.data 116 +system.physmem.num_reads::total 420 +system.physmem.bw_read::cpu.inst 596489614 +system.physmem.bw_read::cpu.data 227607879 +system.physmem.bw_read::total 824097494 +system.physmem.bw_inst_read::cpu.inst 596489614 +system.physmem.bw_inst_read::total 596489614 +system.physmem.bw_total::cpu.inst 596489614 +system.physmem.bw_total::cpu.data 227607879 +system.physmem.bw_total::total 824097494 +system.physmem.readReqs 420 +system.physmem.writeReqs 0 +system.physmem.readBursts 420 +system.physmem.writeBursts 0 +system.physmem.bytesReadDRAM 26880 +system.physmem.bytesReadWrQ 0 +system.physmem.bytesWritten 0 +system.physmem.bytesReadSys 26880 +system.physmem.bytesWrittenSys 0 +system.physmem.servicedByWrQ 0 +system.physmem.mergedWrBursts 0 +system.physmem.neitherReadNorWriteReqs 0 +system.physmem.perBankRdBursts::0 91 +system.physmem.perBankRdBursts::1 52 +system.physmem.perBankRdBursts::2 20 +system.physmem.perBankRdBursts::3 43 +system.physmem.perBankRdBursts::4 21 +system.physmem.perBankRdBursts::5 41 +system.physmem.perBankRdBursts::6 36 +system.physmem.perBankRdBursts::7 12 +system.physmem.perBankRdBursts::8 5 +system.physmem.perBankRdBursts::9 6 +system.physmem.perBankRdBursts::10 27 +system.physmem.perBankRdBursts::11 42 +system.physmem.perBankRdBursts::12 9 +system.physmem.perBankRdBursts::13 8 +system.physmem.perBankRdBursts::14 0 +system.physmem.perBankRdBursts::15 7 +system.physmem.perBankWrBursts::0 0 +system.physmem.perBankWrBursts::1 0 +system.physmem.perBankWrBursts::2 0 +system.physmem.perBankWrBursts::3 0 +system.physmem.perBankWrBursts::4 0 +system.physmem.perBankWrBursts::5 0 +system.physmem.perBankWrBursts::6 0 +system.physmem.perBankWrBursts::7 0 +system.physmem.perBankWrBursts::8 0 +system.physmem.perBankWrBursts::9 0 +system.physmem.perBankWrBursts::10 0 +system.physmem.perBankWrBursts::11 0 +system.physmem.perBankWrBursts::12 0 +system.physmem.perBankWrBursts::13 0 +system.physmem.perBankWrBursts::14 0 +system.physmem.perBankWrBursts::15 0 +system.physmem.numRdRetry 0 +system.physmem.numWrRetry 0 +system.physmem.totGap 32519500 +system.physmem.readPktSize::0 0 +system.physmem.readPktSize::1 0 +system.physmem.readPktSize::2 0 +system.physmem.readPktSize::3 0 +system.physmem.readPktSize::4 0 +system.physmem.readPktSize::5 0 +system.physmem.readPktSize::6 420 +system.physmem.writePktSize::0 0 +system.physmem.writePktSize::1 0 +system.physmem.writePktSize::2 0 +system.physmem.writePktSize::3 0 +system.physmem.writePktSize::4 0 +system.physmem.writePktSize::5 0 +system.physmem.writePktSize::6 0 +system.physmem.rdQLenPdf::0 342 +system.physmem.rdQLenPdf::1 70 +system.physmem.rdQLenPdf::2 8 +system.physmem.rdQLenPdf::3 0 +system.physmem.rdQLenPdf::4 0 +system.physmem.rdQLenPdf::5 0 +system.physmem.rdQLenPdf::6 0 +system.physmem.rdQLenPdf::7 0 +system.physmem.rdQLenPdf::8 0 +system.physmem.rdQLenPdf::9 0 +system.physmem.rdQLenPdf::10 0 +system.physmem.rdQLenPdf::11 0 +system.physmem.rdQLenPdf::12 0 +system.physmem.rdQLenPdf::13 0 +system.physmem.rdQLenPdf::14 0 +system.physmem.rdQLenPdf::15 0 +system.physmem.rdQLenPdf::16 0 +system.physmem.rdQLenPdf::17 0 +system.physmem.rdQLenPdf::18 0 +system.physmem.rdQLenPdf::19 0 +system.physmem.rdQLenPdf::20 0 +system.physmem.rdQLenPdf::21 0 +system.physmem.rdQLenPdf::22 0 +system.physmem.rdQLenPdf::23 0 +system.physmem.rdQLenPdf::24 0 +system.physmem.rdQLenPdf::25 0 +system.physmem.rdQLenPdf::26 0 +system.physmem.rdQLenPdf::27 0 +system.physmem.rdQLenPdf::28 0 +system.physmem.rdQLenPdf::29 0 +system.physmem.rdQLenPdf::30 0 +system.physmem.rdQLenPdf::31 0 +system.physmem.wrQLenPdf::0 0 +system.physmem.wrQLenPdf::1 0 +system.physmem.wrQLenPdf::2 0 +system.physmem.wrQLenPdf::3 0 +system.physmem.wrQLenPdf::4 0 +system.physmem.wrQLenPdf::5 0 +system.physmem.wrQLenPdf::6 0 +system.physmem.wrQLenPdf::7 0 +system.physmem.wrQLenPdf::8 0 +system.physmem.wrQLenPdf::9 0 +system.physmem.wrQLenPdf::10 0 +system.physmem.wrQLenPdf::11 0 +system.physmem.wrQLenPdf::12 0 +system.physmem.wrQLenPdf::13 0 +system.physmem.wrQLenPdf::14 0 +system.physmem.wrQLenPdf::15 0 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a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini index ff436d924..64046a027 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini @@ -65,7 +65,7 @@ SSITSize=1024 activity=0 backComSize=5 branchPred=system.cpu.branchPred -cachePorts=200 +cacheStorePorts=200 checker=system.cpu.checker clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 @@ -141,6 +141,7 @@ socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -206,6 +207,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.checker.tracer updateOnError=true @@ -276,8 +278,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -288,8 +288,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -356,10 +354,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -373,6 +371,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -385,15 +384,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dstage2_mmu] type=ArmStage2MMU @@ -517,10 +517,10 @@ pipelined=true [system.cpu.fuPool.FUList3] type=FUDesc -children=opList0 opList1 opList2 +children=opList0 opList1 opList2 opList3 opList4 count=2 eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 [system.cpu.fuPool.FUList3.opList0] type=OpDesc @@ -532,11 +532,25 @@ pipelined=true [system.cpu.fuPool.FUList3.opList1] type=OpDesc eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 opClass=FloatDiv opLat=12 pipelined=false -[system.cpu.fuPool.FUList3.opList2] +[system.cpu.fuPool.FUList3.opList4] type=OpDesc eventq_index=0 opClass=FloatSqrt @@ -545,18 +559,25 @@ pipelined=false [system.cpu.fuPool.FUList4] type=FUDesc -children=opList +children=opList0 opList1 count=0 eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList +opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 -[system.cpu.fuPool.FUList4.opList] +[system.cpu.fuPool.FUList4.opList0] type=OpDesc eventq_index=0 opClass=MemRead opLat=1 pipelined=true +[system.cpu.fuPool.FUList4.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList5] type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 @@ -706,24 +727,31 @@ pipelined=true [system.cpu.fuPool.FUList6] type=FUDesc -children=opList +children=opList0 opList1 count=0 eventq_index=0 -opList=system.cpu.fuPool.FUList6.opList +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 -[system.cpu.fuPool.FUList6.opList] +[system.cpu.fuPool.FUList6.opList0] type=OpDesc eventq_index=0 opClass=MemWrite opLat=1 pipelined=true +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList7] type=FUDesc -children=opList0 opList1 +children=opList0 opList1 opList2 opList3 count=4 eventq_index=0 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 [system.cpu.fuPool.FUList7.opList0] type=OpDesc @@ -739,6 +767,20 @@ opClass=MemWrite opLat=1 pipelined=true +[system.cpu.fuPool.FUList7.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList8] type=FUDesc children=opList @@ -760,10 +802,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -777,6 +819,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -789,15 +832,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=ArmInterrupts @@ -816,8 +860,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -828,8 +870,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -892,10 +932,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -909,6 +949,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -921,15 +962,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -965,7 +1007,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -974,14 +1016,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/arm/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/arm/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simerr b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simerr index 57447a9b7..1f8287d96 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simerr +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simerr @@ -2,3 +2,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assign warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout index e9b447feb..122f716a7 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing- gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:42:58 -gem5 executing on e108600-lin, pid 17311 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/arm/linux/o3-timing-checker +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 18:05:15 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 55322 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/arm/linux/o3-timing-checker Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 18422500 because target called exit() +Exiting @ tick 18517500 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index b3c6058a4..306010dfa 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,1273 +1,1273 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 18517500 # Number of ticks simulated -final_tick 18517500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 74881 # Simulator instruction rate (inst/s) -host_op_rate 87684 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 301872470 # Simulator tick rate (ticks/s) -host_mem_usage 270416 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -sim_insts 4592 # Number of instructions simulated -sim_ops 5378 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory -system.physmem.bytes_read::total 25344 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory -system.physmem.num_reads::total 396 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 950452275 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 418199001 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1368651276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 950452275 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 950452275 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 950452275 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 418199001 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1368651276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 396 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 396 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25344 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25344 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 89 # Per bank write bursts -system.physmem.perBankRdBursts::1 45 # Per bank write bursts -system.physmem.perBankRdBursts::2 20 # Per bank write bursts -system.physmem.perBankRdBursts::3 43 # Per bank write bursts -system.physmem.perBankRdBursts::4 18 # Per bank write bursts -system.physmem.perBankRdBursts::5 32 # Per bank write bursts -system.physmem.perBankRdBursts::6 35 # Per bank write bursts -system.physmem.perBankRdBursts::7 10 # Per bank write bursts -system.physmem.perBankRdBursts::8 4 # Per bank write bursts -system.physmem.perBankRdBursts::9 8 # Per bank write bursts -system.physmem.perBankRdBursts::10 28 # Per bank write bursts -system.physmem.perBankRdBursts::11 42 # Per bank write bursts -system.physmem.perBankRdBursts::12 10 # Per bank write bursts -system.physmem.perBankRdBursts::13 6 # Per bank write bursts -system.physmem.perBankRdBursts::14 0 # Per bank write bursts -system.physmem.perBankRdBursts::15 6 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 18432000 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 396 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 204 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 121 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 59 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 406.779661 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 269.610222 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 346.645206 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 11 18.64% 18.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16 27.12% 45.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7 11.86% 57.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8 13.56% 71.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1 1.69% 72.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 5.08% 77.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 3.39% 81.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 3.39% 84.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9 15.25% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 59 # Bytes accessed per row activation -system.physmem.totQLat 5212000 # Total ticks spent queuing -system.physmem.totMemAccLat 12637000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1980000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13161.62 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31911.62 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1368.65 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1368.65 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.69 # Data bus utilization in percentage -system.physmem.busUtilRead 10.69 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.87 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 329 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.08 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 46545.45 # Average gap between requests -system.physmem.pageHitRate 83.08 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 314160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 151800 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2084880 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3085980 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 37920 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 5290170 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 19200 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 12213390 # Total energy per rank (pJ) -system.physmem_0.averagePower 659.559336 # Core power per rank (mW) -system.physmem_0.totalIdleTime 11496500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 29500 # Time in different power states -system.physmem_0.memoryStateTime::REF 520000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 49250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 6316250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 11602500 # Time in different power states -system.physmem_1.actEnergy 164220 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 72105 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 742560 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1457490 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 66240 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 6092730 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 686400 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 10511025 # Total energy per rank (pJ) -system.physmem_1.averagePower 567.626569 # Core power per rank (mW) -system.physmem_1.totalIdleTime 15098500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 116000 # Time in different power states -system.physmem_1.memoryStateTime::REF 520000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 1787250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 2733750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 13360500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2820 # Number of BP lookups -system.cpu.branchPred.condPredicted 1728 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 468 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2384 # Number of BTB lookups -system.cpu.branchPred.BTBHits 844 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 35.402685 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 322 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 260 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 13 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 247 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 64 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.inst_hits 0 # ITB inst hits -system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 0 # DTB read hits -system.cpu.checker.dtb.read_misses 0 # DTB read misses -system.cpu.checker.dtb.write_hits 0 # DTB write hits -system.cpu.checker.dtb.write_misses 0 # DTB write misses -system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 0 # DTB read accesses -system.cpu.checker.dtb.write_accesses 0 # DTB write accesses -system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 0 # DTB hits -system.cpu.checker.dtb.misses 0 # DTB misses -system.cpu.checker.dtb.accesses 0 # DTB accesses -system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.checker.itb.walker.walks 0 # Table walker walks requested -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.inst_hits 0 # ITB inst hits -system.cpu.checker.itb.inst_misses 0 # ITB inst misses -system.cpu.checker.itb.read_hits 0 # DTB read hits -system.cpu.checker.itb.read_misses 0 # DTB read misses -system.cpu.checker.itb.write_hits 0 # DTB write hits -system.cpu.checker.itb.write_misses 0 # DTB write misses -system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.checker.itb.read_accesses 0 # DTB read accesses -system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.itb.hits 0 # DTB hits -system.cpu.checker.itb.misses 0 # DTB misses -system.cpu.checker.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 13 # Number of system calls -system.cpu.checker.pwrStateResidencyTicks::ON 18517500 # Cumulative time (in ticks) in various power states -system.cpu.checker.numCycles 5391 # number of cpu cycles simulated -system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.pwrStateResidencyTicks::ON 18517500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 37036 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7733 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12373 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2820 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1179 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 5113 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 985 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 260 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1982 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 291 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13616 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.093052 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.461769 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10916 80.17% 80.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 271 1.99% 82.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 182 1.34% 83.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 206 1.51% 85.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 259 1.90% 86.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 398 2.92% 89.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 138 1.01% 90.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 192 1.41% 92.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1054 7.74% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13616 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.076142 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.334080 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6341 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4657 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2138 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 142 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 338 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 909 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12250 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 489 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 338 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6573 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 835 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2470 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2036 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1364 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11552 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 181 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 144 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1170 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 11673 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 53030 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 12530 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 199 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6179 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 40 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 34 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 442 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2293 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1619 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 33 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 22 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10296 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 44 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8207 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 43 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4962 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 12830 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13616 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.602747 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.340306 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10392 76.32% 76.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1145 8.41% 84.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 762 5.60% 90.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 485 3.56% 93.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 356 2.61% 96.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 278 2.04% 98.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 127 0.93% 99.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 61 0.45% 99.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 10 0.07% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13616 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9 5.42% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 83 50.00% 55.42% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 61 36.75% 92.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 92.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 13 7.83% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5024 61.22% 61.22% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.09% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1962 23.91% 85.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1178 14.35% 99.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 33 0.40% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8207 # Type of FU issued -system.cpu.iq.rate 0.221595 # Inst issue rate -system.cpu.iq.fu_busy_cnt 166 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.020227 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30145 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 15189 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7438 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 94 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 132 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8327 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 46 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 24 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1266 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 681 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 32 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 338 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 707 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10349 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 128 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2293 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1619 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 32 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 93 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 267 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 360 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7885 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1840 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 322 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9 # number of nop insts executed -system.cpu.iew.exec_refs 3007 # number of memory reference insts executed -system.cpu.iew.exec_branches 1490 # Number of branches executed -system.cpu.iew.exec_stores 1167 # Number of stores executed -system.cpu.iew.exec_rate 0.212901 # Inst execution rate -system.cpu.iew.wb_sent 7581 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7470 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3518 # num instructions producing a value -system.cpu.iew.wb_consumers 6872 # num instructions consuming a value -system.cpu.iew.wb_rate 0.201696 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.511932 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 4970 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 314 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12743 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.422036 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.264076 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10698 83.95% 83.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 879 6.90% 90.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 416 3.26% 94.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 216 1.70% 95.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 111 0.87% 96.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 220 1.73% 98.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 55 0.43% 98.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 39 0.31% 99.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 109 0.86% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12743 # Number of insts commited each cycle -system.cpu.commit.committedInsts 4592 # Number of instructions committed -system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 1965 # Number of memory references committed -system.cpu.commit.loads 1027 # Number of loads committed -system.cpu.commit.membars 12 # Number of memory barriers committed -system.cpu.commit.branches 1008 # Number of branches committed -system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 4624 # Number of committed integer instructions. -system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 3406 63.33% 63.33% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 4 0.07% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 3 0.06% 63.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 922 17.14% 99.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 99.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 16 0.30% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 5378 # Class of committed instruction -system.cpu.commit.bw_lim_events 109 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 22825 # The number of ROB reads -system.cpu.rob.rob_writes 21580 # The number of ROB writes -system.cpu.timesIdled 193 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 23420 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 4592 # Number of Instructions Simulated -system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 8.065331 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.065331 # CPI: Total CPI of All Threads -system.cpu.ipc 0.123987 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.123987 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 7779 # number of integer regfile reads -system.cpu.int_regfile_writes 4297 # number of integer regfile writes -system.cpu.fp_regfile_reads 32 # number of floating regfile reads -system.cpu.cc_regfile_reads 28140 # number of cc regfile reads -system.cpu.cc_regfile_writes 3276 # number of cc regfile writes -system.cpu.misc_regfile_reads 3029 # number of misc regfile reads -system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 87.889702 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2158 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 14.680272 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 87.889702 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021457 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021457 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5471 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5471 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1540 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1540 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 597 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2137 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2137 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2137 # number of overall hits -system.cpu.dcache.overall_hits::total 2137 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 186 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 186 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 502 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 502 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 502 # number of overall misses -system.cpu.dcache.overall_misses::total 502 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11381500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11381500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24478000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24478000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 156000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 156000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35859500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35859500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35859500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35859500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1726 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1726 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2639 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2639 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2639 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2639 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.107764 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.107764 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.346112 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.346112 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.190224 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.190224 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.190224 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.190224 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61190.860215 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61190.860215 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77462.025316 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 77462.025316 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 78000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 78000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 71433.266932 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 71433.266932 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 71433.266932 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 71433.266932 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 159 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 81 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 274 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 274 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 355 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 355 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 355 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 355 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7338000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7338000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3668000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3668000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11006000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11006000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11006000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11006000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.060834 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.060834 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055703 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.055703 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055703 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.055703 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69885.714286 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69885.714286 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 87333.333333 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 87333.333333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74870.748299 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74870.748299 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74870.748299 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74870.748299 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 2 # number of replacements -system.cpu.icache.tags.tagsinuse 148.671994 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1587 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 293 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.416382 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 148.671994 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.072594 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.072594 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 291 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 160 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.142090 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4257 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4257 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1587 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1587 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1587 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1587 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1587 # number of overall hits -system.cpu.icache.overall_hits::total 1587 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 395 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 395 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 395 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 395 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 395 # number of overall misses -system.cpu.icache.overall_misses::total 395 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 29663500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 29663500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 29663500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 29663500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 29663500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 29663500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1982 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1982 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1982 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1982 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1982 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1982 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.199294 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.199294 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.199294 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.199294 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.199294 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.199294 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75097.468354 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 75097.468354 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 75097.468354 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 75097.468354 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 75097.468354 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 75097.468354 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 422 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 105.500000 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 2 # number of writebacks -system.cpu.icache.writebacks::total 2 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 102 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 102 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 102 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 102 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 102 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 102 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 293 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 293 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 293 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 293 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 293 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23439000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23439000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23439000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23439000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23439000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23439000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.147830 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.147830 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.147830 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.147830 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.147830 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.147830 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79996.587031 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79996.587031 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79996.587031 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 79996.587031 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79996.587031 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 79996.587031 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 213.492112 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 396 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.098485 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.462705 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 74.029407 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004256 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002259 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006515 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012085 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3924 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3924 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 18 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 18 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 20 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 20 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 18 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 38 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 18 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits -system.cpu.l2cache.overall_hits::total 38 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 275 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 275 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 85 # 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-system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 293 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 293 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 105 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 105 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 293 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 440 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 293 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 440 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.938567 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.938567 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.809524 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.809524 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.938567 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.913636 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.938567 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.913636 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85785.714286 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85785.714286 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82878.181818 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82878.181818 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81688.235294 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81688.235294 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82878.181818 # average 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average number of cycles each access was blocked -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 6 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 275 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 275 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 79 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 79 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 121 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 396 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 121 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 396 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3183000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3183000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20041500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20041500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5712000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5712000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20041500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8895000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 28936500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20041500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8895000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 28936500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.938567 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.752381 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.752381 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.900000 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.900000 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75785.714286 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75785.714286 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72878.181818 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72878.181818 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72303.797468 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72303.797468 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72878.181818 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73512.396694 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73071.969697 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72878.181818 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73512.396694 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73071.969697 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 442 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 45 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 293 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 105 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 882 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18880 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28288 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 440 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.100000 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.300341 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 396 90.00% 90.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 44 10.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 440 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 223000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 439500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 223494 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 396 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 354 # Transaction distribution -system.membus.trans_dist::ReadExReq 42 # Transaction distribution -system.membus.trans_dist::ReadExResp 42 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 354 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 792 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 792 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 25344 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 396 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 396 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 396 # Request fanout histogram -system.membus.reqLayer0.occupancy 484000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2091500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.3 # Layer utilization (%) +sim_seconds 0.000019 +sim_ticks 18517500 +final_tick 18517500 +sim_freq 1000000000000 +host_inst_rate 45460 +host_op_rate 53229 +host_tick_rate 183240261 +host_mem_usage 280812 +host_seconds 0.10 +sim_insts 4592 +sim_ops 5378 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 18517500 +system.physmem.bytes_read::cpu.inst 17600 +system.physmem.bytes_read::cpu.data 7744 +system.physmem.bytes_read::total 25344 +system.physmem.bytes_inst_read::cpu.inst 17600 +system.physmem.bytes_inst_read::total 17600 +system.physmem.num_reads::cpu.inst 275 +system.physmem.num_reads::cpu.data 121 +system.physmem.num_reads::total 396 +system.physmem.bw_read::cpu.inst 950452275 +system.physmem.bw_read::cpu.data 418199001 +system.physmem.bw_read::total 1368651276 +system.physmem.bw_inst_read::cpu.inst 950452275 +system.physmem.bw_inst_read::total 950452275 +system.physmem.bw_total::cpu.inst 950452275 +system.physmem.bw_total::cpu.data 418199001 +system.physmem.bw_total::total 1368651276 +system.physmem.readReqs 396 +system.physmem.writeReqs 0 +system.physmem.readBursts 396 +system.physmem.writeBursts 0 +system.physmem.bytesReadDRAM 25344 +system.physmem.bytesReadWrQ 0 +system.physmem.bytesWritten 0 +system.physmem.bytesReadSys 25344 +system.physmem.bytesWrittenSys 0 +system.physmem.servicedByWrQ 0 +system.physmem.mergedWrBursts 0 +system.physmem.neitherReadNorWriteReqs 0 +system.physmem.perBankRdBursts::0 89 +system.physmem.perBankRdBursts::1 45 +system.physmem.perBankRdBursts::2 20 +system.physmem.perBankRdBursts::3 43 +system.physmem.perBankRdBursts::4 18 +system.physmem.perBankRdBursts::5 32 +system.physmem.perBankRdBursts::6 35 +system.physmem.perBankRdBursts::7 10 +system.physmem.perBankRdBursts::8 4 +system.physmem.perBankRdBursts::9 8 +system.physmem.perBankRdBursts::10 28 +system.physmem.perBankRdBursts::11 42 +system.physmem.perBankRdBursts::12 10 +system.physmem.perBankRdBursts::13 6 +system.physmem.perBankRdBursts::14 0 +system.physmem.perBankRdBursts::15 6 +system.physmem.perBankWrBursts::0 0 +system.physmem.perBankWrBursts::1 0 +system.physmem.perBankWrBursts::2 0 +system.physmem.perBankWrBursts::3 0 +system.physmem.perBankWrBursts::4 0 +system.physmem.perBankWrBursts::5 0 +system.physmem.perBankWrBursts::6 0 +system.physmem.perBankWrBursts::7 0 +system.physmem.perBankWrBursts::8 0 +system.physmem.perBankWrBursts::9 0 +system.physmem.perBankWrBursts::10 0 +system.physmem.perBankWrBursts::11 0 +system.physmem.perBankWrBursts::12 0 +system.physmem.perBankWrBursts::13 0 +system.physmem.perBankWrBursts::14 0 +system.physmem.perBankWrBursts::15 0 +system.physmem.numRdRetry 0 +system.physmem.numWrRetry 0 +system.physmem.totGap 18432000 +system.physmem.readPktSize::0 0 +system.physmem.readPktSize::1 0 +system.physmem.readPktSize::2 0 +system.physmem.readPktSize::3 0 +system.physmem.readPktSize::4 0 +system.physmem.readPktSize::5 0 +system.physmem.readPktSize::6 396 +system.physmem.writePktSize::0 0 +system.physmem.writePktSize::1 0 +system.physmem.writePktSize::2 0 +system.physmem.writePktSize::3 0 +system.physmem.writePktSize::4 0 +system.physmem.writePktSize::5 0 +system.physmem.writePktSize::6 0 +system.physmem.rdQLenPdf::0 204 +system.physmem.rdQLenPdf::1 121 +system.physmem.rdQLenPdf::2 52 +system.physmem.rdQLenPdf::3 14 +system.physmem.rdQLenPdf::4 4 +system.physmem.rdQLenPdf::5 1 +system.physmem.rdQLenPdf::6 0 +system.physmem.rdQLenPdf::7 0 +system.physmem.rdQLenPdf::8 0 +system.physmem.rdQLenPdf::9 0 +system.physmem.rdQLenPdf::10 0 +system.physmem.rdQLenPdf::11 0 +system.physmem.rdQLenPdf::12 0 +system.physmem.rdQLenPdf::13 0 +system.physmem.rdQLenPdf::14 0 +system.physmem.rdQLenPdf::15 0 +system.physmem.rdQLenPdf::16 0 +system.physmem.rdQLenPdf::17 0 +system.physmem.rdQLenPdf::18 0 +system.physmem.rdQLenPdf::19 0 +system.physmem.rdQLenPdf::20 0 +system.physmem.rdQLenPdf::21 0 +system.physmem.rdQLenPdf::22 0 +system.physmem.rdQLenPdf::23 0 +system.physmem.rdQLenPdf::24 0 +system.physmem.rdQLenPdf::25 0 +system.physmem.rdQLenPdf::26 0 +system.physmem.rdQLenPdf::27 0 +system.physmem.rdQLenPdf::28 0 +system.physmem.rdQLenPdf::29 0 +system.physmem.rdQLenPdf::30 0 +system.physmem.rdQLenPdf::31 0 +system.physmem.wrQLenPdf::0 0 +system.physmem.wrQLenPdf::1 0 +system.physmem.wrQLenPdf::2 0 +system.physmem.wrQLenPdf::3 0 +system.physmem.wrQLenPdf::4 0 +system.physmem.wrQLenPdf::5 0 +system.physmem.wrQLenPdf::6 0 +system.physmem.wrQLenPdf::7 0 +system.physmem.wrQLenPdf::8 0 +system.physmem.wrQLenPdf::9 0 +system.physmem.wrQLenPdf::10 0 +system.physmem.wrQLenPdf::11 0 +system.physmem.wrQLenPdf::12 0 +system.physmem.wrQLenPdf::13 0 +system.physmem.wrQLenPdf::14 0 +system.physmem.wrQLenPdf::15 0 +system.physmem.wrQLenPdf::16 0 +system.physmem.wrQLenPdf::17 0 +system.physmem.wrQLenPdf::18 0 +system.physmem.wrQLenPdf::19 0 +system.physmem.wrQLenPdf::20 0 +system.physmem.wrQLenPdf::21 0 +system.physmem.wrQLenPdf::22 0 +system.physmem.wrQLenPdf::23 0 +system.physmem.wrQLenPdf::24 0 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+system.physmem.wrQLenPdf::56 0 +system.physmem.wrQLenPdf::57 0 +system.physmem.wrQLenPdf::58 0 +system.physmem.wrQLenPdf::59 0 +system.physmem.wrQLenPdf::60 0 +system.physmem.wrQLenPdf::61 0 +system.physmem.wrQLenPdf::62 0 +system.physmem.wrQLenPdf::63 0 +system.physmem.bytesPerActivate::samples 59 +system.physmem.bytesPerActivate::mean 406.779661 +system.physmem.bytesPerActivate::gmean 269.610222 +system.physmem.bytesPerActivate::stdev 346.645206 +system.physmem.bytesPerActivate::0-127 11 18.64% 18.64% +system.physmem.bytesPerActivate::128-255 16 27.12% 45.76% +system.physmem.bytesPerActivate::256-383 7 11.86% 57.63% +system.physmem.bytesPerActivate::384-511 8 13.56% 71.19% +system.physmem.bytesPerActivate::512-639 1 1.69% 72.88% +system.physmem.bytesPerActivate::640-767 3 5.08% 77.97% +system.physmem.bytesPerActivate::768-895 2 3.39% 81.36% +system.physmem.bytesPerActivate::896-1023 2 3.39% 84.75% +system.physmem.bytesPerActivate::1024-1151 9 15.25% 100.00% +system.physmem.bytesPerActivate::total 59 +system.physmem.totQLat 5212000 +system.physmem.totMemAccLat 12637000 +system.physmem.totBusLat 1980000 +system.physmem.avgQLat 13161.62 +system.physmem.avgBusLat 5000.00 +system.physmem.avgMemAccLat 31911.62 +system.physmem.avgRdBW 1368.65 +system.physmem.avgWrBW 0.00 +system.physmem.avgRdBWSys 1368.65 +system.physmem.avgWrBWSys 0.00 +system.physmem.peakBW 12800.00 +system.physmem.busUtil 10.69 +system.physmem.busUtilRead 10.69 +system.physmem.busUtilWrite 0.00 +system.physmem.avgRdQLen 1.87 +system.physmem.avgWrQLen 0.00 +system.physmem.readRowHits 329 +system.physmem.writeRowHits 0 +system.physmem.readRowHitRate 83.08 +system.physmem.writeRowHitRate nan +system.physmem.avgGap 46545.45 +system.physmem.pageHitRate 83.08 +system.physmem_0.actEnergy 314160 +system.physmem_0.preEnergy 151800 +system.physmem_0.readEnergy 2084880 +system.physmem_0.writeEnergy 0 +system.physmem_0.refreshEnergy 1229280.000000 +system.physmem_0.actBackEnergy 3085980 +system.physmem_0.preBackEnergy 37920 +system.physmem_0.actPowerDownEnergy 5290170 +system.physmem_0.prePowerDownEnergy 19200 +system.physmem_0.selfRefreshEnergy 0 +system.physmem_0.totalEnergy 12213390 +system.physmem_0.averagePower 659.559336 +system.physmem_0.totalIdleTime 11496500 +system.physmem_0.memoryStateTime::IDLE 29500 +system.physmem_0.memoryStateTime::REF 520000 +system.physmem_0.memoryStateTime::SREF 0 +system.physmem_0.memoryStateTime::PRE_PDN 49250 +system.physmem_0.memoryStateTime::ACT 6316250 +system.physmem_0.memoryStateTime::ACT_PDN 11602500 +system.physmem_1.actEnergy 164220 +system.physmem_1.preEnergy 72105 +system.physmem_1.readEnergy 742560 +system.physmem_1.writeEnergy 0 +system.physmem_1.refreshEnergy 1229280.000000 +system.physmem_1.actBackEnergy 1457490 +system.physmem_1.preBackEnergy 66240 +system.physmem_1.actPowerDownEnergy 6092730 +system.physmem_1.prePowerDownEnergy 686400 +system.physmem_1.selfRefreshEnergy 0 +system.physmem_1.totalEnergy 10511025 +system.physmem_1.averagePower 567.626569 +system.physmem_1.totalIdleTime 15098500 +system.physmem_1.memoryStateTime::IDLE 116000 +system.physmem_1.memoryStateTime::REF 520000 +system.physmem_1.memoryStateTime::SREF 0 +system.physmem_1.memoryStateTime::PRE_PDN 1787250 +system.physmem_1.memoryStateTime::ACT 2733750 +system.physmem_1.memoryStateTime::ACT_PDN 13360500 +system.pwrStateResidencyTicks::UNDEFINED 18517500 +system.cpu.branchPred.lookups 2820 +system.cpu.branchPred.condPredicted 1728 +system.cpu.branchPred.condIncorrect 468 +system.cpu.branchPred.BTBLookups 2384 +system.cpu.branchPred.BTBHits 844 +system.cpu.branchPred.BTBCorrect 0 +system.cpu.branchPred.BTBHitPct 35.402685 +system.cpu.branchPred.usedRAS 322 +system.cpu.branchPred.RASInCorrect 70 +system.cpu.branchPred.indirectLookups 260 +system.cpu.branchPred.indirectHits 13 +system.cpu.branchPred.indirectMisses 247 +system.cpu.branchPredindirectMispredicted 64 +system.cpu_clk_domain.clock 500 +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 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73071.969697 +system.cpu.toL2Bus.snoop_filter.tot_requests 442 +system.cpu.toL2Bus.snoop_filter.hit_single_requests 45 +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 18517500 +system.cpu.toL2Bus.trans_dist::ReadResp 398 +system.cpu.toL2Bus.trans_dist::WritebackClean 2 +system.cpu.toL2Bus.trans_dist::ReadExReq 42 +system.cpu.toL2Bus.trans_dist::ReadExResp 42 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 293 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 105 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 588 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 +system.cpu.toL2Bus.pkt_count::total 882 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18880 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 +system.cpu.toL2Bus.pkt_size::total 28288 +system.cpu.toL2Bus.snoops 0 +system.cpu.toL2Bus.snoopTraffic 0 +system.cpu.toL2Bus.snoop_fanout::samples 440 +system.cpu.toL2Bus.snoop_fanout::mean 0.100000 +system.cpu.toL2Bus.snoop_fanout::stdev 0.300341 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 396 90.00% 90.00% +system.cpu.toL2Bus.snoop_fanout::1 44 10.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 1 +system.cpu.toL2Bus.snoop_fanout::total 440 +system.cpu.toL2Bus.reqLayer0.occupancy 223000 +system.cpu.toL2Bus.reqLayer0.utilization 1.2 +system.cpu.toL2Bus.respLayer0.occupancy 439500 +system.cpu.toL2Bus.respLayer0.utilization 2.4 +system.cpu.toL2Bus.respLayer1.occupancy 223494 +system.cpu.toL2Bus.respLayer1.utilization 1.2 +system.membus.snoop_filter.tot_requests 396 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 18517500 +system.membus.trans_dist::ReadResp 354 +system.membus.trans_dist::ReadExReq 42 +system.membus.trans_dist::ReadExResp 42 +system.membus.trans_dist::ReadSharedReq 354 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 792 +system.membus.pkt_count::total 792 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25344 +system.membus.pkt_size::total 25344 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 396 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 396 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 396 +system.membus.reqLayer0.occupancy 484000 +system.membus.reqLayer0.utilization 2.6 +system.membus.respLayer1.occupancy 2091500 +system.membus.respLayer1.utilization 11.3 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini index 3cdf3afd3..72771fa1e 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini @@ -65,7 +65,7 @@ SSITSize=1024 activity=0 backComSize=5 branchPred=system.cpu.branchPred -cachePorts=200 +cacheStorePorts=200 checker=Null clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 @@ -141,6 +141,7 @@ socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -626,8 +627,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -638,8 +637,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -807,7 +804,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -816,14 +813,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/arm/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr index bbcd9d751..707fed98b 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr @@ -1,3 +1,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout index d64ac9ed3..9ae67891c 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 29 2016 19:03:48 -gem5 started Nov 29 2016 19:06:55 -gem5 executing on zizzer, pid 5766 -command line: /z/powerjg/gem5-upstream/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/arm/linux/o3-timing +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 18:08:17 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 55753 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 20302000 because target called exit() +Exiting @ tick 20302000 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 6ea38295f..f88830f40 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,1179 +1,1179 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 20302000 # Number of ticks simulated -final_tick 20302000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 93691 # Simulator instruction rate (inst/s) -host_op_rate 109699 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 414022055 # Simulator tick rate (ticks/s) -host_mem_usage 265936 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -sim_insts 4592 # Number of instructions simulated -sim_ops 5378 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 18560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory -system.physmem.bytes_read::total 28416 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 18560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 18560 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 290 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 127 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory -system.physmem.num_reads::total 444 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 914195646 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 400354645 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 85114767 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1399665058 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 914195646 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 914195646 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 914195646 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 400354645 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 85114767 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1399665058 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 445 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 445 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28480 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28480 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 103 # Per bank write bursts -system.physmem.perBankRdBursts::1 48 # Per bank write bursts -system.physmem.perBankRdBursts::2 19 # Per bank write bursts -system.physmem.perBankRdBursts::3 45 # Per bank write bursts -system.physmem.perBankRdBursts::4 19 # Per bank write bursts -system.physmem.perBankRdBursts::5 37 # Per bank write bursts -system.physmem.perBankRdBursts::6 46 # Per bank write bursts -system.physmem.perBankRdBursts::7 10 # Per bank write bursts -system.physmem.perBankRdBursts::8 4 # Per bank write bursts -system.physmem.perBankRdBursts::9 8 # Per bank write bursts -system.physmem.perBankRdBursts::10 27 # Per bank write bursts -system.physmem.perBankRdBursts::11 47 # Per bank write bursts -system.physmem.perBankRdBursts::12 17 # Per bank write bursts -system.physmem.perBankRdBursts::13 8 # Per bank write bursts -system.physmem.perBankRdBursts::14 0 # Per bank write bursts -system.physmem.perBankRdBursts::15 7 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 20260500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 445 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 241 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 36 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 435.612903 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 295.844737 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 352.802892 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 8 12.90% 12.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16 25.81% 38.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 10 16.13% 54.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7 11.29% 66.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 3.23% 69.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 4.84% 74.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 3.23% 77.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4 6.45% 83.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10 16.13% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation -system.physmem.totQLat 6135000 # Total ticks spent queuing -system.physmem.totMemAccLat 14478750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2225000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13786.52 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32536.52 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1402.82 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1402.82 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.96 # Data bus utilization in percentage -system.physmem.busUtilRead 10.96 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 373 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.82 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 45529.21 # Average gap between requests -system.physmem.pageHitRate 83.82 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 349860 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 170775 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2334780 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3562500 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 28800 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 5660100 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 960 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 13337055 # Total energy per rank (pJ) -system.physmem_0.averagePower 656.916882 # Core power per rank (mW) -system.physmem_0.totalIdleTime 12261000 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 19000 # Time in different power states -system.physmem_0.memoryStateTime::REF 520000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 2500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 7351250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 12409250 # Time in different power states -system.physmem_1.actEnergy 164220 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 64515 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 842520 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1478010 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 68640 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 7415130 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 238560 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 11500875 # Total energy per rank (pJ) -system.physmem_1.averagePower 566.475803 # Core power per rank (mW) -system.physmem_1.totalIdleTime 16880000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 110000 # Time in different power states -system.physmem_1.memoryStateTime::REF 520000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 620500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 2792000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 16259500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2438 # Number of BP lookups -system.cpu.branchPred.condPredicted 1441 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 523 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 913 # Number of BTB lookups -system.cpu.branchPred.BTBHits 446 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 48.849945 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 286 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 57 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 163 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 13 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 150 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 59 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 20302000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 40605 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6162 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11460 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2438 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 745 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 8314 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1089 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 142 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 286 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 466 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 3900 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 180 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 15914 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.856227 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.206589 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9531 59.89% 59.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2501 15.72% 75.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 521 3.27% 78.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3361 21.12% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15914 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.060042 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.282231 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5816 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4410 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5171 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 385 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 538 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 162 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 10171 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1674 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 385 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6927 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1165 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2515 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4182 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 740 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 9091 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 462 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 25 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 28 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 631 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9449 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 41113 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 9997 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3955 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 29 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 332 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1823 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1287 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 8508 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7227 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 183 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3168 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 8218 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 15914 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.454128 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.844358 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11653 73.22% 73.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1987 12.49% 85.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1624 10.20% 95.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 608 3.82% 99.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 42 0.26% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 15914 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 414 28.79% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 469 32.61% 61.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 538 37.41% 98.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 98.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 17 1.18% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4537 62.78% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1601 22.15% 85.04% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1065 14.74% 99.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 16 0.22% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7227 # Type of FU issued -system.cpu.iq.rate 0.177983 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1438 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.198976 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31940 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 11705 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 6623 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 49 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8632 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 33 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 12 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 796 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 349 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 385 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 345 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 8559 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1823 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1287 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 60 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 320 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 380 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 6823 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1419 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 13 # number of nop insts executed -system.cpu.iew.exec_refs 2443 # number of memory reference insts executed -system.cpu.iew.exec_branches 1299 # Number of branches executed -system.cpu.iew.exec_stores 1024 # Number of stores executed -system.cpu.iew.exec_rate 0.168033 # Inst execution rate -system.cpu.iew.wb_sent 6684 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 6639 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2983 # num instructions producing a value -system.cpu.iew.wb_consumers 5430 # num instructions consuming a value -system.cpu.iew.wb_rate 0.163502 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.549355 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 2701 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 364 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 15346 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.350450 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 0.989791 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 12681 82.63% 82.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1400 9.12% 91.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 606 3.95% 95.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 298 1.94% 97.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 165 1.08% 98.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 80 0.52% 99.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 44 0.29% 99.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 28 0.18% 99.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 44 0.29% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 15346 # Number of insts commited each cycle -system.cpu.commit.committedInsts 4592 # Number of instructions committed -system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 1965 # Number of memory references committed -system.cpu.commit.loads 1027 # Number of loads committed -system.cpu.commit.membars 12 # Number of memory barriers committed -system.cpu.commit.branches 1008 # Number of branches committed -system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 4624 # Number of committed integer instructions. -system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 3406 63.33% 63.33% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 4 0.07% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 3 0.06% 63.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 922 17.14% 99.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 99.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 16 0.30% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 5378 # Class of committed instruction -system.cpu.commit.bw_lim_events 44 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 23224 # The number of ROB reads -system.cpu.rob.rob_writes 16731 # The number of ROB writes -system.cpu.timesIdled 212 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 24691 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 4592 # Number of Instructions Simulated -system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 8.842552 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.842552 # CPI: Total CPI of All Threads -system.cpu.ipc 0.113090 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.113090 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 6850 # number of integer regfile reads -system.cpu.int_regfile_writes 3795 # number of integer regfile writes -system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 24229 # number of cc regfile reads -system.cpu.cc_regfile_writes 2927 # number of cc regfile writes -system.cpu.misc_regfile_reads 2559 # number of misc regfile reads -system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.085192 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1923 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.447552 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.085192 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.164229 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.164229 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4715 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4715 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1181 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1181 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1903 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1903 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1903 # number of overall hits -system.cpu.dcache.overall_hits::total 1903 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 191 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 191 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 361 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 361 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 361 # number of overall misses -system.cpu.dcache.overall_misses::total 361 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12060000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12060000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8016500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8016500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 139000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 139000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20076500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20076500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20076500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20076500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1351 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1351 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2264 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2264 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2264 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2264 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.125833 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.125833 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.209200 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.209200 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.159452 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.159452 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.159452 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.159452 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70941.176471 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70941.176471 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41971.204188 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41971.204188 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 69500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 69500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55613.573407 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55613.573407 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55613.573407 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55613.573407 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 853 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 47.388889 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 1 # number of writebacks -system.cpu.dcache.writebacks::total 1 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 67 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 150 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 217 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 217 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 217 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 217 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7989500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7989500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2594500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2594500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10584000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10584000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10584000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10584000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076240 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076240 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063604 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.063604 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063604 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.063604 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77567.961165 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77567.961165 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63280.487805 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63280.487805 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73500 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 73500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 73500 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 44 # number of replacements -system.cpu.icache.tags.tagsinuse 137.523624 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 3532 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11.812709 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 137.523624 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.268601 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.268601 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 255 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 110 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 8095 # Number of tag accesses -system.cpu.icache.tags.data_accesses 8095 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 3532 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 3532 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 3532 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 3532 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 3532 # number of overall hits -system.cpu.icache.overall_hits::total 3532 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 366 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 366 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 366 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses -system.cpu.icache.overall_misses::total 366 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25091490 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25091490 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25091490 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25091490 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25091490 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25091490 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 3898 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 3898 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 3898 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 3898 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 3898 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 3898 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.093894 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.093894 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.093894 # miss rate for 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dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 17.362749 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 41 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.073171 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9.237342 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 8.125407 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 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-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1766926 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2280000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2280000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19864000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19864000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6912500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6912500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19864000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9192500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 29056500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19864000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9192500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1766926 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30823426 # number of overall MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.731707 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.969900 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.969900 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.951456 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.951456 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.969900 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.888889 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.943567 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.969900 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.888889 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 1.063205 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33338.226415 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 33338.226415 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68496.551724 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68496.551724 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70535.714286 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70535.714286 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68496.551724 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71816.406250 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69513.157895 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68496.551724 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71816.406250 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33338.226415 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65442.518047 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 488 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 74 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 12 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 26 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 24 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 2 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 45 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 69 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 299 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 642 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 288 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 930 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21952 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 69 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 512 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.134766 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.353072 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 445 86.91% 86.91% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 65 12.70% 99.61% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 2 0.39% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 512 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 289000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 448999 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 216995 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 445 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 35 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 414 # Transaction distribution -system.membus.trans_dist::ReadExReq 30 # Transaction distribution -system.membus.trans_dist::ReadExResp 30 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 415 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 889 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 889 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28416 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 28416 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 445 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 445 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 445 # Request fanout histogram -system.membus.reqLayer0.occupancy 554444 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 2338250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.5 # Layer utilization (%) +sim_seconds 0.000020 +sim_ticks 20302000 +final_tick 20302000 +sim_freq 1000000000000 +host_inst_rate 45535 +host_op_rate 53318 +host_tick_rate 201173118 +host_mem_usage 277864 +host_seconds 0.10 +sim_insts 4592 +sim_ops 5378 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 20302000 +system.physmem.bytes_read::cpu.inst 18560 +system.physmem.bytes_read::cpu.data 8128 +system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 +system.physmem.bytes_read::total 28416 +system.physmem.bytes_inst_read::cpu.inst 18560 +system.physmem.bytes_inst_read::total 18560 +system.physmem.num_reads::cpu.inst 290 +system.physmem.num_reads::cpu.data 127 +system.physmem.num_reads::cpu.l2cache.prefetcher 27 +system.physmem.num_reads::total 444 +system.physmem.bw_read::cpu.inst 914195646 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+system.physmem.bytesPerActivate::128-255 16 25.81% 38.71% +system.physmem.bytesPerActivate::256-383 10 16.13% 54.84% +system.physmem.bytesPerActivate::384-511 7 11.29% 66.13% +system.physmem.bytesPerActivate::512-639 2 3.23% 69.35% +system.physmem.bytesPerActivate::640-767 3 4.84% 74.19% +system.physmem.bytesPerActivate::768-895 2 3.23% 77.42% +system.physmem.bytesPerActivate::896-1023 4 6.45% 83.87% +system.physmem.bytesPerActivate::1024-1151 10 16.13% 100.00% +system.physmem.bytesPerActivate::total 62 +system.physmem.totQLat 6135000 +system.physmem.totMemAccLat 14478750 +system.physmem.totBusLat 2225000 +system.physmem.avgQLat 13786.52 +system.physmem.avgBusLat 5000.00 +system.physmem.avgMemAccLat 32536.52 +system.physmem.avgRdBW 1402.82 +system.physmem.avgWrBW 0.00 +system.physmem.avgRdBWSys 1402.82 +system.physmem.avgWrBWSys 0.00 +system.physmem.peakBW 12800.00 +system.physmem.busUtil 10.96 +system.physmem.busUtilRead 10.96 +system.physmem.busUtilWrite 0.00 +system.physmem.avgRdQLen 1.85 +system.physmem.avgWrQLen 0.00 +system.physmem.readRowHits 373 +system.physmem.writeRowHits 0 +system.physmem.readRowHitRate 83.82 +system.physmem.writeRowHitRate nan +system.physmem.avgGap 45529.21 +system.physmem.pageHitRate 83.82 +system.physmem_0.actEnergy 349860 +system.physmem_0.preEnergy 170775 +system.physmem_0.readEnergy 2334780 +system.physmem_0.writeEnergy 0 +system.physmem_0.refreshEnergy 1229280.000000 +system.physmem_0.actBackEnergy 3562500 +system.physmem_0.preBackEnergy 28800 +system.physmem_0.actPowerDownEnergy 5660100 +system.physmem_0.prePowerDownEnergy 960 +system.physmem_0.selfRefreshEnergy 0 +system.physmem_0.totalEnergy 13337055 +system.physmem_0.averagePower 656.916882 +system.physmem_0.totalIdleTime 12261000 +system.physmem_0.memoryStateTime::IDLE 19000 +system.physmem_0.memoryStateTime::REF 520000 +system.physmem_0.memoryStateTime::SREF 0 +system.physmem_0.memoryStateTime::PRE_PDN 2500 +system.physmem_0.memoryStateTime::ACT 7351250 +system.physmem_0.memoryStateTime::ACT_PDN 12409250 +system.physmem_1.actEnergy 164220 +system.physmem_1.preEnergy 64515 +system.physmem_1.readEnergy 842520 +system.physmem_1.writeEnergy 0 +system.physmem_1.refreshEnergy 1229280.000000 +system.physmem_1.actBackEnergy 1478010 +system.physmem_1.preBackEnergy 68640 +system.physmem_1.actPowerDownEnergy 7415130 +system.physmem_1.prePowerDownEnergy 238560 +system.physmem_1.selfRefreshEnergy 0 +system.physmem_1.totalEnergy 11500875 +system.physmem_1.averagePower 566.475803 +system.physmem_1.totalIdleTime 16880000 +system.physmem_1.memoryStateTime::IDLE 110000 +system.physmem_1.memoryStateTime::REF 520000 +system.physmem_1.memoryStateTime::SREF 0 +system.physmem_1.memoryStateTime::PRE_PDN 620500 +system.physmem_1.memoryStateTime::ACT 2792000 +system.physmem_1.memoryStateTime::ACT_PDN 16259500 +system.pwrStateResidencyTicks::UNDEFINED 20302000 +system.cpu.branchPred.lookups 2438 +system.cpu.branchPred.condPredicted 1441 +system.cpu.branchPred.condIncorrect 523 +system.cpu.branchPred.BTBLookups 913 +system.cpu.branchPred.BTBHits 446 +system.cpu.branchPred.BTBCorrect 0 +system.cpu.branchPred.BTBHitPct 48.849945 +system.cpu.branchPred.usedRAS 286 +system.cpu.branchPred.RASInCorrect 57 +system.cpu.branchPred.indirectLookups 163 +system.cpu.branchPred.indirectHits 13 +system.cpu.branchPred.indirectMisses 150 +system.cpu.branchPredindirectMispredicted 59 +system.cpu_clk_domain.clock 500 +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 20302000 +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 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+system.cpu.l2cache.overall_mshr_miss_latency::total 30823426 +system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf +system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.731707 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.969900 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.969900 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.951456 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.951456 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.969900 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.888889 +system.cpu.l2cache.demand_mshr_miss_rate::total 0.943567 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.969900 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.888889 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf +system.cpu.l2cache.overall_mshr_miss_rate::total 1.063205 +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33338.226415 +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 33338.226415 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76000 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76000 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68496.551724 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68496.551724 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70535.714286 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70535.714286 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68496.551724 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71816.406250 +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69513.157895 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68496.551724 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71816.406250 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33338.226415 +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65442.518047 +system.cpu.toL2Bus.snoop_filter.tot_requests 488 +system.cpu.toL2Bus.snoop_filter.hit_single_requests 74 +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 12 +system.cpu.toL2Bus.snoop_filter.tot_snoops 26 +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 24 +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 2 +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 20302000 +system.cpu.toL2Bus.trans_dist::ReadResp 401 +system.cpu.toL2Bus.trans_dist::WritebackClean 45 +system.cpu.toL2Bus.trans_dist::HardPFReq 69 +system.cpu.toL2Bus.trans_dist::ReadExReq 41 +system.cpu.toL2Bus.trans_dist::ReadExResp 41 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 299 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 642 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 288 +system.cpu.toL2Bus.pkt_count::total 930 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21952 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9216 +system.cpu.toL2Bus.pkt_size::total 31168 +system.cpu.toL2Bus.snoops 69 +system.cpu.toL2Bus.snoopTraffic 0 +system.cpu.toL2Bus.snoop_fanout::samples 512 +system.cpu.toL2Bus.snoop_fanout::mean 0.134766 +system.cpu.toL2Bus.snoop_fanout::stdev 0.353072 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 445 86.91% 86.91% +system.cpu.toL2Bus.snoop_fanout::1 65 12.70% 99.61% +system.cpu.toL2Bus.snoop_fanout::2 2 0.39% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 2 +system.cpu.toL2Bus.snoop_fanout::total 512 +system.cpu.toL2Bus.reqLayer0.occupancy 289000 +system.cpu.toL2Bus.reqLayer0.utilization 1.4 +system.cpu.toL2Bus.respLayer0.occupancy 448999 +system.cpu.toL2Bus.respLayer0.utilization 2.2 +system.cpu.toL2Bus.respLayer1.occupancy 216995 +system.cpu.toL2Bus.respLayer1.utilization 1.1 +system.membus.snoop_filter.tot_requests 445 +system.membus.snoop_filter.hit_single_requests 35 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 20302000 +system.membus.trans_dist::ReadResp 414 +system.membus.trans_dist::ReadExReq 30 +system.membus.trans_dist::ReadExResp 30 +system.membus.trans_dist::ReadSharedReq 415 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 889 +system.membus.pkt_count::total 889 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28416 +system.membus.pkt_size::total 28416 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 445 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 445 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 445 +system.membus.reqLayer0.occupancy 554444 +system.membus.reqLayer0.utilization 2.7 +system.membus.respLayer1.occupancy 2338250 +system.membus.respLayer1.utilization 11.5 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini index be532b0c0..3b9285ab6 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini @@ -90,6 +90,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -131,6 +132,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.checker.tracer updateOnError=false @@ -200,8 +202,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -212,8 +212,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -340,8 +338,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -352,8 +348,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -414,7 +408,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -423,14 +417,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/arm/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/arm/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -454,6 +449,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -465,7 +461,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -473,6 +469,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -481,6 +484,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -488,7 +492,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr index 2b0e974b5..d46032821 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr @@ -1,3 +1,4 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout index a4f08df89..6f0847911 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-ato gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:49:47 -gem5 executing on e108600-lin, pid 23301 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/arm/linux/simple-atomic-dummychecker +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 17:56:13 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54232 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/arm/linux/simple-atomic-dummychecker Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 2695000 because target called exit() +Exiting @ tick 2695000 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index cf15c6ad1..d2c8b968b 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -1,384 +1,384 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2695000 # Number of ticks simulated -final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 707147 # Simulator instruction rate (inst/s) -host_op_rate 826854 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 413753949 # Simulator tick rate (ticks/s) -host_mem_usage 259056 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 4592 # Number of instructions simulated -sim_ops 5378 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 18420 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory -system.physmem.bytes_read::total 22911 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 18420 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 18420 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory -system.physmem.bytes_written::total 3648 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4605 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1003 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5608 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory -system.physmem.num_writes::total 924 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 6834879406 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1666419295 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8501298701 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6834879406 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6834879406 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1353617811 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1353617811 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6834879406 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3020037106 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9854916512 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.inst_hits 0 # ITB inst hits -system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 0 # DTB read hits -system.cpu.checker.dtb.read_misses 0 # DTB read misses -system.cpu.checker.dtb.write_hits 0 # DTB write hits -system.cpu.checker.dtb.write_misses 0 # DTB write misses -system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 0 # DTB read accesses -system.cpu.checker.dtb.write_accesses 0 # DTB write accesses -system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 0 # DTB hits -system.cpu.checker.dtb.misses 0 # DTB misses -system.cpu.checker.dtb.accesses 0 # DTB accesses -system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.checker.itb.walker.walks 0 # Table walker walks requested -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.inst_hits 0 # ITB inst hits -system.cpu.checker.itb.inst_misses 0 # ITB inst misses -system.cpu.checker.itb.read_hits 0 # DTB read hits -system.cpu.checker.itb.read_misses 0 # DTB read misses -system.cpu.checker.itb.write_hits 0 # DTB write hits -system.cpu.checker.itb.write_misses 0 # DTB write misses -system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.checker.itb.read_accesses 0 # DTB read accesses -system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.itb.hits 0 # DTB hits -system.cpu.checker.itb.misses 0 # DTB misses -system.cpu.checker.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 13 # Number of system calls -system.cpu.checker.pwrStateResidencyTicks::ON 2695000 # Cumulative time (in ticks) in various power states -system.cpu.checker.numCycles 0 # number of cpu cycles simulated -system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.pwrStateResidencyTicks::ON 2695000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 5391 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 4592 # Number of instructions committed -system.cpu.committedOps 5378 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses -system.cpu.num_func_calls 203 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 722 # number of instructions that are conditional controls -system.cpu.num_int_insts 4624 # number of integer instructions -system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 7572 # number of times the integer registers were read -system.cpu.num_int_register_writes 2728 # number of times the integer registers were written -system.cpu.num_fp_register_reads 16 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 16175 # number of times the CC registers were read -system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written -system.cpu.num_mem_refs 1965 # number of memory refs -system.cpu.num_load_insts 1027 # Number of load instructions -system.cpu.num_store_insts 938 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 5390.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1008 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 3419 63.42% 63.42% # Class of executed instruction -system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.06% 63.55% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% # Class of executed instruction -system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction -system.cpu.op_class::MemWrite 922 17.10% 99.70% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 99.70% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 16 0.30% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5391 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 5597 # Transaction distribution -system.membus.trans_dist::ReadResp 5608 # Transaction distribution -system.membus.trans_dist::WriteReq 913 # Transaction distribution -system.membus.trans_dist::WriteResp 913 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution -system.membus.trans_dist::StoreCondReq 11 # Transaction distribution -system.membus.trans_dist::StoreCondResp 11 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9210 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 13064 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18420 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26559 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 6532 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 6532 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 6532 # Request fanout histogram +sim_seconds 0.000003 +sim_ticks 2695000 +final_tick 2695000 +sim_freq 1000000000000 +host_inst_rate 413531 +host_op_rate 483368 +host_tick_rate 241807981 +host_mem_usage 270560 +host_seconds 0.01 +sim_insts 4592 +sim_ops 5378 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 2695000 +system.physmem.bytes_read::cpu.inst 18420 +system.physmem.bytes_read::cpu.data 4491 +system.physmem.bytes_read::total 22911 +system.physmem.bytes_inst_read::cpu.inst 18420 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63.49% +system.cpu.op_class::FloatAdd 0 0.00% 63.49% +system.cpu.op_class::FloatCmp 0 0.00% 63.49% +system.cpu.op_class::FloatCvt 0 0.00% 63.49% +system.cpu.op_class::FloatMult 0 0.00% 63.49% +system.cpu.op_class::FloatMultAcc 0 0.00% 63.49% +system.cpu.op_class::FloatDiv 0 0.00% 63.49% +system.cpu.op_class::FloatMisc 0 0.00% 63.49% +system.cpu.op_class::FloatSqrt 0 0.00% 63.49% +system.cpu.op_class::SimdAdd 0 0.00% 63.49% +system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% +system.cpu.op_class::SimdAlu 0 0.00% 63.49% +system.cpu.op_class::SimdCmp 0 0.00% 63.49% +system.cpu.op_class::SimdCvt 0 0.00% 63.49% +system.cpu.op_class::SimdMisc 0 0.00% 63.49% +system.cpu.op_class::SimdMult 0 0.00% 63.49% +system.cpu.op_class::SimdMultAcc 0 0.00% 63.49% +system.cpu.op_class::SimdShift 0 0.00% 63.49% +system.cpu.op_class::SimdShiftAcc 0 0.00% 63.49% +system.cpu.op_class::SimdSqrt 0 0.00% 63.49% +system.cpu.op_class::SimdFloatAdd 0 0.00% 63.49% +system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% +system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% +system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% +system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% +system.cpu.op_class::SimdFloatMisc 3 0.06% 63.55% +system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% +system.cpu.op_class::MemRead 1027 19.05% 82.60% +system.cpu.op_class::MemWrite 922 17.10% 99.70% +system.cpu.op_class::FloatMemRead 0 0.00% 99.70% +system.cpu.op_class::FloatMemWrite 16 0.30% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 5391 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 2695000 +system.membus.trans_dist::ReadReq 5597 +system.membus.trans_dist::ReadResp 5608 +system.membus.trans_dist::WriteReq 913 +system.membus.trans_dist::WriteResp 913 +system.membus.trans_dist::LoadLockedReq 11 +system.membus.trans_dist::StoreCondReq 11 +system.membus.trans_dist::StoreCondResp 11 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9210 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 +system.membus.pkt_count::total 13064 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18420 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 +system.membus.pkt_size::total 26559 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 6532 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 6532 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 6532 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini index 8f8064fa0..c1120b4bf 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini @@ -90,6 +90,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -165,8 +166,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -177,8 +176,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -239,7 +236,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -248,14 +245,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/arm/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/arm/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -279,6 +277,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -290,7 +289,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -298,6 +297,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -306,6 +312,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -313,7 +320,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simerr index aadc3d011..c0b55d123 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simerr +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout index 813c1fdca..ffacc8975 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-ato gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:38:23 -gem5 executing on e108600-lin, pid 23087 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/arm/linux/simple-atomic +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 17:58:26 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54584 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 2695000 because target called exit() +Exiting @ tick 2695000 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index 18ea66efd..9a08bb729 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -1,260 +1,260 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2695000 # Number of ticks simulated -final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 709054 # Simulator instruction rate (inst/s) -host_op_rate 829008 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 414799236 # Simulator tick rate (ticks/s) -host_mem_usage 257780 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 4592 # Number of instructions simulated -sim_ops 5378 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 18420 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory -system.physmem.bytes_read::total 22911 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 18420 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 18420 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory -system.physmem.bytes_written::total 3648 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4605 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1003 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5608 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory -system.physmem.num_writes::total 924 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 6834879406 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1666419295 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8501298701 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6834879406 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6834879406 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1353617811 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1353617811 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6834879406 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3020037106 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9854916512 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 2695000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 5391 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 4592 # Number of instructions committed -system.cpu.committedOps 5378 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses -system.cpu.num_func_calls 203 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 722 # number of instructions that are conditional controls -system.cpu.num_int_insts 4624 # number of integer instructions -system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 7572 # number of times the integer registers were read -system.cpu.num_int_register_writes 2728 # number of times the integer registers were written -system.cpu.num_fp_register_reads 16 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 16175 # number of times the CC registers were read -system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written -system.cpu.num_mem_refs 1965 # number of memory refs -system.cpu.num_load_insts 1027 # Number of load instructions -system.cpu.num_store_insts 938 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 5390.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1008 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 3419 63.42% 63.42% # Class of executed instruction -system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.06% 63.55% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% # Class of executed instruction -system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction -system.cpu.op_class::MemWrite 922 17.10% 99.70% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 99.70% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 16 0.30% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5391 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 5597 # Transaction distribution -system.membus.trans_dist::ReadResp 5608 # Transaction distribution -system.membus.trans_dist::WriteReq 913 # Transaction distribution -system.membus.trans_dist::WriteResp 913 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution -system.membus.trans_dist::StoreCondReq 11 # Transaction distribution -system.membus.trans_dist::StoreCondResp 11 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9210 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 13064 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18420 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26559 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 6532 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 6532 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 6532 # Request fanout histogram +sim_seconds 0.000003 +sim_ticks 2695000 +final_tick 2695000 +sim_freq 1000000000000 +host_inst_rate 427927 +host_op_rate 500175 +host_tick_rate 250203319 +host_mem_usage 269284 +host_seconds 0.01 +sim_insts 4592 +sim_ops 5378 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 2695000 +system.physmem.bytes_read::cpu.inst 18420 +system.physmem.bytes_read::cpu.data 4491 +system.physmem.bytes_read::total 22911 +system.physmem.bytes_inst_read::cpu.inst 18420 +system.physmem.bytes_inst_read::total 18420 +system.physmem.bytes_written::cpu.data 3648 +system.physmem.bytes_written::total 3648 +system.physmem.num_reads::cpu.inst 4605 +system.physmem.num_reads::cpu.data 1003 +system.physmem.num_reads::total 5608 +system.physmem.num_writes::cpu.data 924 +system.physmem.num_writes::total 924 +system.physmem.bw_read::cpu.inst 6834879406 +system.physmem.bw_read::cpu.data 1666419295 +system.physmem.bw_read::total 8501298701 +system.physmem.bw_inst_read::cpu.inst 6834879406 +system.physmem.bw_inst_read::total 6834879406 +system.physmem.bw_write::cpu.data 1353617811 +system.physmem.bw_write::total 1353617811 +system.physmem.bw_total::cpu.inst 6834879406 +system.physmem.bw_total::cpu.data 3020037106 +system.physmem.bw_total::total 9854916512 +system.pwrStateResidencyTicks::UNDEFINED 2695000 +system.cpu_clk_domain.clock 500 +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.hits 0 +system.cpu.dstage2_mmu.stage2_tlb.misses 0 +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 +system.cpu.dtb.walker.walks 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dtb.walker.walkRequestOrigin::total 0 +system.cpu.dtb.inst_hits 0 +system.cpu.dtb.inst_misses 0 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.flush_tlb 0 +system.cpu.dtb.flush_tlb_mva 0 +system.cpu.dtb.flush_tlb_mva_asid 0 +system.cpu.dtb.flush_tlb_asid 0 +system.cpu.dtb.flush_entries 0 +system.cpu.dtb.align_faults 0 +system.cpu.dtb.prefetch_faults 0 +system.cpu.dtb.domain_faults 0 +system.cpu.dtb.perms_faults 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.inst_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.hits 0 +system.cpu.istage2_mmu.stage2_tlb.misses 0 +system.cpu.istage2_mmu.stage2_tlb.accesses 0 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 +system.cpu.itb.walker.walks 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.itb.walker.walkRequestOrigin::total 0 +system.cpu.itb.inst_hits 0 +system.cpu.itb.inst_misses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.flush_tlb 0 +system.cpu.itb.flush_tlb_mva 0 +system.cpu.itb.flush_tlb_mva_asid 0 +system.cpu.itb.flush_tlb_asid 0 +system.cpu.itb.flush_entries 0 +system.cpu.itb.align_faults 0 +system.cpu.itb.prefetch_faults 0 +system.cpu.itb.domain_faults 0 +system.cpu.itb.perms_faults 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.inst_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 13 +system.cpu.pwrStateResidencyTicks::ON 2695000 +system.cpu.numCycles 5391 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 4592 +system.cpu.committedOps 5378 +system.cpu.num_int_alu_accesses 4624 +system.cpu.num_fp_alu_accesses 16 +system.cpu.num_func_calls 203 +system.cpu.num_conditional_control_insts 722 +system.cpu.num_int_insts 4624 +system.cpu.num_fp_insts 16 +system.cpu.num_int_register_reads 7572 +system.cpu.num_int_register_writes 2728 +system.cpu.num_fp_register_reads 16 +system.cpu.num_fp_register_writes 0 +system.cpu.num_cc_register_reads 16175 +system.cpu.num_cc_register_writes 2432 +system.cpu.num_mem_refs 1965 +system.cpu.num_load_insts 1027 +system.cpu.num_store_insts 938 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 5391 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 1008 +system.cpu.op_class::No_OpClass 0 0.00% 0.00% +system.cpu.op_class::IntAlu 3419 63.42% 63.42% +system.cpu.op_class::IntMult 4 0.07% 63.49% +system.cpu.op_class::IntDiv 0 0.00% 63.49% +system.cpu.op_class::FloatAdd 0 0.00% 63.49% +system.cpu.op_class::FloatCmp 0 0.00% 63.49% +system.cpu.op_class::FloatCvt 0 0.00% 63.49% +system.cpu.op_class::FloatMult 0 0.00% 63.49% +system.cpu.op_class::FloatMultAcc 0 0.00% 63.49% +system.cpu.op_class::FloatDiv 0 0.00% 63.49% +system.cpu.op_class::FloatMisc 0 0.00% 63.49% +system.cpu.op_class::FloatSqrt 0 0.00% 63.49% +system.cpu.op_class::SimdAdd 0 0.00% 63.49% +system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% +system.cpu.op_class::SimdAlu 0 0.00% 63.49% +system.cpu.op_class::SimdCmp 0 0.00% 63.49% +system.cpu.op_class::SimdCvt 0 0.00% 63.49% +system.cpu.op_class::SimdMisc 0 0.00% 63.49% +system.cpu.op_class::SimdMult 0 0.00% 63.49% +system.cpu.op_class::SimdMultAcc 0 0.00% 63.49% +system.cpu.op_class::SimdShift 0 0.00% 63.49% +system.cpu.op_class::SimdShiftAcc 0 0.00% 63.49% +system.cpu.op_class::SimdSqrt 0 0.00% 63.49% +system.cpu.op_class::SimdFloatAdd 0 0.00% 63.49% +system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% +system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% +system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% +system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% +system.cpu.op_class::SimdFloatMisc 3 0.06% 63.55% +system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% +system.cpu.op_class::MemRead 1027 19.05% 82.60% +system.cpu.op_class::MemWrite 922 17.10% 99.70% +system.cpu.op_class::FloatMemRead 0 0.00% 99.70% +system.cpu.op_class::FloatMemWrite 16 0.30% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 5391 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 2695000 +system.membus.trans_dist::ReadReq 5597 +system.membus.trans_dist::ReadResp 5608 +system.membus.trans_dist::WriteReq 913 +system.membus.trans_dist::WriteResp 913 +system.membus.trans_dist::LoadLockedReq 11 +system.membus.trans_dist::StoreCondReq 11 +system.membus.trans_dist::StoreCondResp 11 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9210 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 +system.membus.pkt_count::total 13064 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18420 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 +system.membus.pkt_size::total 26559 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 6532 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 6532 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 6532 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini index b1081da03..4f88d60dc 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini @@ -87,6 +87,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -96,14 +97,14 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -117,6 +118,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -129,15 +131,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dstage2_mmu] type=ArmStage2MMU @@ -193,14 +196,14 @@ port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -214,6 +217,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -226,15 +230,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=ArmInterrupts @@ -253,8 +258,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -265,8 +268,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -325,14 +326,14 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -346,6 +347,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -358,15 +360,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -402,7 +405,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -411,14 +414,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/arm/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/arm/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -442,6 +446,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -453,7 +458,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -461,6 +466,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -469,6 +481,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -476,7 +489,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simerr b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simerr index aadc3d011..c0b55d123 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simerr +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout index 4f7f76cdc..b914fe569 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:38:23 -gem5 executing on e108600-lin, pid 23085 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/arm/linux/simple-timing +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 18:13:17 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 56989 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 28298500 because target called exit() +Exiting @ tick 28648500 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 3c58db434..76c17a485 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -1,630 +1,630 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000029 # Number of seconds simulated -sim_ticks 28648500 # Number of ticks simulated -final_tick 28648500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 484095 # Simulator instruction rate (inst/s) -host_op_rate 564461 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3030833923 # Simulator tick rate (ticks/s) -host_mem_usage 267516 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 4566 # Number of instructions simulated -sim_ops 5330 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory -system.physmem.bytes_read::total 22400 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory -system.physmem.num_reads::total 350 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 502644117 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 279246732 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 781890849 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 502644117 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 502644117 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 502644117 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 279246732 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 781890849 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 28648500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 57297 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 4566 # Number of instructions committed -system.cpu.committedOps 5330 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses -system.cpu.num_func_calls 203 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 722 # number of instructions that are conditional controls -system.cpu.num_int_insts 4624 # number of integer instructions -system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 7538 # number of times the integer registers were read -system.cpu.num_int_register_writes 2728 # number of times the integer registers were written -system.cpu.num_fp_register_reads 16 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 19187 # number of times the CC registers were read -system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written -system.cpu.num_mem_refs 1965 # number of memory refs -system.cpu.num_load_insts 1027 # Number of load instructions -system.cpu.num_store_insts 938 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 57296.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1008 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 3419 63.42% 63.42% # Class of executed instruction -system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.06% 63.55% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% # Class of executed instruction -system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction -system.cpu.op_class::MemWrite 922 17.10% 99.70% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 99.70% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 16 0.30% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5391 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.616265 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.616265 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020170 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020170 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 3995 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 3995 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 894 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 894 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1764 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1764 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1764 # number of overall hits -system.cpu.dcache.overall_hits::total 1764 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 141 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses -system.cpu.dcache.overall_misses::total 141 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5390000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5390000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2709000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2709000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 8099000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8099000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 8099000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8099000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 992 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1905 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1905 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098790 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098790 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.047097 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.074016 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.074016 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.074016 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.074016 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 57439.716312 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 57439.716312 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 57439.716312 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 57439.716312 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5292000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5292000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2666000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2666000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7958000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7958000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7958000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7958000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56439.716312 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 56439.716312 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56439.716312 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 56439.716312 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 113.995886 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 4365 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18.112033 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 113.995886 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.055662 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.055662 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.117188 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 9453 # Number of tag accesses -system.cpu.icache.tags.data_accesses 9453 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 4365 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4365 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4365 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4365 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4365 # number of overall hits -system.cpu.icache.overall_hits::total 4365 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 241 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses -system.cpu.icache.overall_misses::total 241 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14404500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14404500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14404500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14404500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14404500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14404500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 4606 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 4606 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 4606 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 4606 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 4606 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 4606 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052323 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.052323 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.052323 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.052323 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.052323 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.052323 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59769.709544 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 59769.709544 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 59769.709544 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 59769.709544 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 59769.709544 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 59769.709544 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1 # number of writebacks -system.cpu.icache.writebacks::total 1 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 241 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 241 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 241 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14163500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14163500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14163500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14163500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14163500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14163500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052323 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.052323 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.052323 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 58769.709544 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 58769.709544 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 58769.709544 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 58769.709544 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 58769.709544 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 58769.709544 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 180.559791 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.091429 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.285464 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 75.274327 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003213 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002297 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005510 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010681 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3406 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3406 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 16 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 16 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 16 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 32 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 16 # number of overall hits -system.cpu.l2cache.overall_hits::total 32 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 225 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 225 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 82 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 82 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 225 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 125 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 350 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses -system.cpu.l2cache.overall_misses::total 350 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2601500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2601500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13618000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 13618000 # number of ReadCleanReq miss cycles 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-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.933610 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.933610 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.836735 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.836735 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.933610 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.886525 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.916230 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.916230 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60524.444444 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60524.444444 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60524.444444 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60515.714286 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60524.444444 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60515.714286 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 225 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 225 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 82 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 82 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2171500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2171500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11368000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11368000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4141000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4141000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11368000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6312500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17680500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11368000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6312500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17680500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.933610 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.836735 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.916230 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.916230 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50524.444444 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50524.444444 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50524.444444 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50515.714286 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50524.444444 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50515.714286 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 383 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 32 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 241 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 98 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 483 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 765 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 24512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 382 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.083770 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.277405 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 350 91.62% 91.62% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 32 8.38% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 382 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 192500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 361500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 350 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 307 # Transaction distribution -system.membus.trans_dist::ReadExReq 43 # Transaction distribution -system.membus.trans_dist::ReadExResp 43 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 307 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 700 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 700 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22400 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22400 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 350 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 350 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 350 # Request fanout histogram -system.membus.reqLayer0.occupancy 355500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1750000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.1 # Layer utilization (%) +sim_seconds 0.000029 +sim_ticks 28648500 +final_tick 28648500 +sim_freq 1000000000000 +host_inst_rate 277751 +host_op_rate 323869 +host_tick_rate 1739012040 +host_mem_usage 279272 +host_seconds 0.02 +sim_insts 4566 +sim_ops 5330 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 28648500 +system.physmem.bytes_read::cpu.inst 14400 +system.physmem.bytes_read::cpu.data 8000 +system.physmem.bytes_read::total 22400 +system.physmem.bytes_inst_read::cpu.inst 14400 +system.physmem.bytes_inst_read::total 14400 +system.physmem.num_reads::cpu.inst 225 +system.physmem.num_reads::cpu.data 125 +system.physmem.num_reads::total 350 +system.physmem.bw_read::cpu.inst 502644117 +system.physmem.bw_read::cpu.data 279246732 +system.physmem.bw_read::total 781890849 +system.physmem.bw_inst_read::cpu.inst 502644117 +system.physmem.bw_inst_read::total 502644117 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+system.cpu.l2cache.ReadCleanReq_mshr_misses::total 225 +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 82 +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 82 +system.cpu.l2cache.demand_mshr_misses::cpu.inst 225 +system.cpu.l2cache.demand_mshr_misses::cpu.data 125 +system.cpu.l2cache.demand_mshr_misses::total 350 +system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 +system.cpu.l2cache.overall_mshr_misses::cpu.data 125 +system.cpu.l2cache.overall_mshr_misses::total 350 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2171500 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2171500 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11368000 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11368000 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4141000 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4141000 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11368000 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6312500 +system.cpu.l2cache.demand_mshr_miss_latency::total 17680500 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11368000 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6312500 +system.cpu.l2cache.overall_mshr_miss_latency::total 17680500 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.933610 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.933610 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.836735 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.836735 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.933610 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.886525 +system.cpu.l2cache.demand_mshr_miss_rate::total 0.916230 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.933610 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.886525 +system.cpu.l2cache.overall_mshr_miss_rate::total 0.916230 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50524.444444 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50524.444444 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50524.444444 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50515.714286 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50524.444444 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50515.714286 +system.cpu.toL2Bus.snoop_filter.tot_requests 383 +system.cpu.toL2Bus.snoop_filter.hit_single_requests 32 +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 28648500 +system.cpu.toL2Bus.trans_dist::ReadResp 339 +system.cpu.toL2Bus.trans_dist::WritebackClean 1 +system.cpu.toL2Bus.trans_dist::ReadExReq 43 +system.cpu.toL2Bus.trans_dist::ReadExResp 43 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 241 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 98 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 483 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 +system.cpu.toL2Bus.pkt_count::total 765 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15488 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 +system.cpu.toL2Bus.pkt_size::total 24512 +system.cpu.toL2Bus.snoops 0 +system.cpu.toL2Bus.snoopTraffic 0 +system.cpu.toL2Bus.snoop_fanout::samples 382 +system.cpu.toL2Bus.snoop_fanout::mean 0.083770 +system.cpu.toL2Bus.snoop_fanout::stdev 0.277405 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 350 91.62% 91.62% +system.cpu.toL2Bus.snoop_fanout::1 32 8.38% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 1 +system.cpu.toL2Bus.snoop_fanout::total 382 +system.cpu.toL2Bus.reqLayer0.occupancy 192500 +system.cpu.toL2Bus.reqLayer0.utilization 0.7 +system.cpu.toL2Bus.respLayer0.occupancy 361500 +system.cpu.toL2Bus.respLayer0.utilization 1.3 +system.cpu.toL2Bus.respLayer1.occupancy 211500 +system.cpu.toL2Bus.respLayer1.utilization 0.7 +system.membus.snoop_filter.tot_requests 350 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 28648500 +system.membus.trans_dist::ReadResp 307 +system.membus.trans_dist::ReadExReq 43 +system.membus.trans_dist::ReadExResp 43 +system.membus.trans_dist::ReadSharedReq 307 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 700 +system.membus.pkt_count::total 700 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22400 +system.membus.pkt_size::total 22400 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 350 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 350 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 350 +system.membus.reqLayer0.occupancy 355500 +system.membus.reqLayer0.utilization 1.2 +system.membus.respLayer1.occupancy 1750000 +system.membus.respLayer1.utilization 6.1 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini index 70198a6d7..c234169e9 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini @@ -66,7 +66,7 @@ UnifiedTLB=true activity=0 backComSize=5 branchPred=system.cpu.branchPred -cachePorts=200 +cacheStorePorts=200 checker=Null clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 @@ -140,6 +140,7 @@ socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -716,7 +717,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -725,14 +726,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/hello/bin/power/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/power/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simerr b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simerr index bbcd9d751..707fed98b 100755 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simerr +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simerr @@ -1,3 +1,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout index 5b262649f..a796e3972 100755 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 29 2016 18:37:43 -gem5 started Nov 29 2016 18:37:59 -gem5 executing on zizzer, pid 53433 -command line: /z/powerjg/gem5-upstream/build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/power/linux/o3-timing +gem5 compiled Apr 3 2017 19:22:30 +gem5 started Apr 3 2017 19:22:48 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 103796 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 21268000 because target called exit() +Exiting @ tick 21189000 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 804710aed..189de9f2f 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,1012 +1,1012 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 21189000 # Number of ticks simulated -final_tick 21189000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 143245 # Simulator instruction rate (inst/s) -host_op_rate 143198 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 523712790 # Simulator tick rate (ticks/s) -host_mem_usage 249592 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -sim_insts 5792 # Number of instructions simulated -sim_ops 5792 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 21824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 6528 # Number of bytes read from this memory -system.physmem.bytes_read::total 28352 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 21824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 21824 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 341 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 102 # Number of read requests responded to by this memory -system.physmem.num_reads::total 443 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1029968380 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 308084383 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1338052763 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1029968380 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1029968380 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1029968380 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 308084383 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1338052763 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 444 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 444 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28416 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28416 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 71 # Per bank write bursts -system.physmem.perBankRdBursts::1 42 # Per bank write bursts -system.physmem.perBankRdBursts::2 55 # Per bank write bursts -system.physmem.perBankRdBursts::3 58 # Per bank write bursts -system.physmem.perBankRdBursts::4 53 # Per bank write bursts -system.physmem.perBankRdBursts::5 61 # Per bank write bursts -system.physmem.perBankRdBursts::6 52 # Per bank write bursts -system.physmem.perBankRdBursts::7 10 # Per bank write bursts -system.physmem.perBankRdBursts::8 9 # Per bank write bursts -system.physmem.perBankRdBursts::9 28 # Per bank write bursts -system.physmem.perBankRdBursts::10 1 # Per bank write bursts -system.physmem.perBankRdBursts::11 0 # Per bank write bursts -system.physmem.perBankRdBursts::12 0 # Per bank write bursts -system.physmem.perBankRdBursts::13 0 # Per bank write bursts -system.physmem.perBankRdBursts::14 4 # Per bank write bursts -system.physmem.perBankRdBursts::15 0 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21128500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 444 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 235 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 76 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 348.631579 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 212.894378 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 337.912685 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24 31.58% 31.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17 22.37% 53.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 12 15.79% 69.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2 2.63% 72.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 3.95% 76.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4 5.26% 81.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 2.63% 84.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3 3.95% 88.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9 11.84% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 76 # Bytes accessed per row activation -system.physmem.totQLat 5920000 # Total ticks spent queuing -system.physmem.totMemAccLat 14245000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2220000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13333.33 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32083.33 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1341.07 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1341.07 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.48 # Data bus utilization in percentage -system.physmem.busUtilRead 10.48 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 358 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.63 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 47586.71 # Average gap between requests -system.physmem.pageHitRate 80.63 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 528360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 254265 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2870280 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3925590 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 28320 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 5657820 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 38400 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 14532315 # Total energy per rank (pJ) -system.physmem_0.averagePower 685.810052 # Core power per rank (mW) -system.physmem_0.totalIdleTime 12505250 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 17500 # Time in different power states -system.physmem_0.memoryStateTime::REF 520000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 100250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 8146250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 12405000 # Time in different power states -system.physmem_1.actEnergy 85680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 34155 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 299880 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 759810 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1412160 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 6380010 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 712320 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 10913295 # Total energy per rank (pJ) -system.physmem_1.averagePower 515.021000 # Core power per rank (mW) -system.physmem_1.totalIdleTime 13660000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 3594000 # Time in different power states -system.physmem_1.memoryStateTime::REF 520000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 1854750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1229000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 13991250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2458 # Number of BP lookups -system.cpu.branchPred.condPredicted 2033 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 409 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2104 # Number of BTB lookups -system.cpu.branchPred.BTBHits 724 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 34.410646 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 228 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 36 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 135 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 18 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 117 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 37 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 9 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 21189000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 42379 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7639 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13455 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2458 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 970 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4277 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 847 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 146 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1865 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 287 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12512 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.075368 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.471061 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10164 81.23% 81.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 163 1.30% 82.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 210 1.68% 84.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 146 1.17% 85.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 247 1.97% 87.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 148 1.18% 88.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 304 2.43% 90.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 158 1.26% 92.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 972 7.77% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12512 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.058000 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.317492 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7217 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2933 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1957 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 130 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 275 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 791 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 149 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11520 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 456 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 275 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7386 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 930 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 461 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1904 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1556 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11074 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 22 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1496 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9775 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 17991 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 17965 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 4777 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 27 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 402 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1923 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1570 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 55 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 32 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10204 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 65 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8807 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 41 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4477 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3567 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 49 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12512 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.703884 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.500750 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9387 75.02% 75.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 964 7.70% 82.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 667 5.33% 88.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 467 3.73% 91.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 439 3.51% 95.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 290 2.32% 97.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 213 1.70% 99.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 56 0.45% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 29 0.23% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12512 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 12 6.22% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 87 45.08% 51.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 83 43.01% 94.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 94.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 11 5.70% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5542 62.93% 62.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1815 20.61% 83.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1422 16.15% 99.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 2 0.02% 99.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 24 0.27% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8807 # Type of FU issued -system.cpu.iq.rate 0.207815 # Inst issue rate -system.cpu.iq.fu_busy_cnt 193 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021914 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30293 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14716 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8133 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 67 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8961 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 39 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 84 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 962 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 524 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 275 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 818 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 73 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10269 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 43 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1923 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1570 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 53 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 60 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 71 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 256 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 327 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8488 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1719 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 319 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3083 # number of memory reference insts executed -system.cpu.iew.exec_branches 1364 # Number of branches executed -system.cpu.iew.exec_stores 1364 # Number of stores executed -system.cpu.iew.exec_rate 0.200288 # Inst execution rate -system.cpu.iew.wb_sent 8262 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8160 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4466 # num instructions producing a value -system.cpu.iew.wb_consumers 7207 # num instructions consuming a value -system.cpu.iew.wb_rate 0.192548 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.619675 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 4479 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 270 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11808 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.490515 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.351526 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9643 81.66% 81.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 845 7.16% 88.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 531 4.50% 93.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 215 1.82% 95.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 177 1.50% 96.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 110 0.93% 97.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 132 1.12% 98.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 50 0.42% 99.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 105 0.89% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11808 # Number of insts commited each cycle -system.cpu.commit.committedInsts 5792 # Number of instructions committed -system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 2007 # Number of memory references committed -system.cpu.commit.loads 961 # Number of loads committed -system.cpu.commit.membars 7 # Number of memory barriers committed -system.cpu.commit.branches 1037 # Number of branches committed -system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. -system.cpu.commit.int_insts 5698 # Number of committed integer instructions. -system.cpu.commit.function_calls 103 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 3783 65.31% 65.31% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 0 0.00% 65.31% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 65.31% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 2 0.03% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 960 16.57% 81.92% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 1027 17.73% 99.65% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 1 0.02% 99.67% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 19 0.33% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 5792 # Class of committed instruction -system.cpu.commit.bw_lim_events 105 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 21974 # The number of ROB reads -system.cpu.rob.rob_writes 21247 # The number of ROB writes -system.cpu.timesIdled 227 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 29867 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 5792 # Number of Instructions Simulated -system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.316816 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.316816 # CPI: Total CPI of All Threads -system.cpu.ipc 0.136671 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.136671 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13468 # number of integer regfile reads -system.cpu.int_regfile_writes 7187 # number of integer regfile writes -system.cpu.fp_regfile_reads 25 # number of floating regfile reads -system.cpu.fp_regfile_writes 2 # number of floating regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 66.953799 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2204 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 104 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 21.192308 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 66.953799 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.016346 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.016346 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 104 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 80 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.025391 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5386 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5386 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1483 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1483 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 721 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 721 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2204 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2204 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2204 # number of overall hits -system.cpu.dcache.overall_hits::total 2204 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 112 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 112 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 325 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 325 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 437 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 437 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 437 # number of overall misses -system.cpu.dcache.overall_misses::total 437 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8129500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8129500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 32497996 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 32497996 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 40627496 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 40627496 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 40627496 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 40627496 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1595 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1595 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2641 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2641 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2641 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2641 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070219 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.070219 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.310707 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.310707 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.165468 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.165468 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.165468 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.165468 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72584.821429 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72584.821429 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99993.833846 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 99993.833846 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 92969.098398 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 92969.098398 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 92969.098398 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 92969.098398 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 749 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 9 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.222222 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 54 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 54 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 278 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 278 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 332 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 332 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 332 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 332 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 58 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 58 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses 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Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.170410 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4079 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4079 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1435 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1435 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1435 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1435 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1435 # number of overall hits -system.cpu.icache.overall_hits::total 1435 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 430 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 430 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 430 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 430 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 430 # number of overall misses -system.cpu.icache.overall_misses::total 430 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 33426000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 33426000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 33426000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 33426000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 33426000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 33426000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1865 # number of ReadReq accesses(hits+misses) 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-system.cpu.icache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28154000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 28154000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28154000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 28154000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28154000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 28154000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.187668 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.187668 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.187668 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.187668 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.187668 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.187668 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 80440 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 80440 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80440 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 80440 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80440 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 80440 # average overall mshr miss latency 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for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.977143 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.977143 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.965517 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.965517 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.977143 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.980952 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.978022 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.977143 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.980952 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.978022 # miss rate for overall accesses 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average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 90577.669903 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82848.314607 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 342 # 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-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4150500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 24128000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 24128000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4159000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4159000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24128000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8309500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 32437500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24128000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8309500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 32437500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.977143 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.977143 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.965517 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.965517 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.977143 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980952 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.978022 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.977143 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980952 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.978022 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88308.510638 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88308.510638 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70549.707602 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70549.707602 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74267.857143 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74267.857143 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70549.707602 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80674.757282 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72893.258427 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70549.707602 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80674.757282 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72893.258427 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 455 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 10 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 350 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 58 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 209 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 908 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6656 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 455 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.021978 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.146773 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 445 97.80% 97.80% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 10 2.20% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 455 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 227500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 523500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 156000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 444 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 396 # Transaction distribution -system.membus.trans_dist::ReadExReq 47 # Transaction distribution -system.membus.trans_dist::ReadExResp 47 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 397 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 887 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28352 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 28352 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 444 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 444 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 444 # Request fanout histogram -system.membus.reqLayer0.occupancy 553000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2325750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.0 # Layer utilization (%) +sim_seconds 0.000021 +sim_ticks 21189000 +final_tick 21189000 +sim_freq 1000000000000 +host_inst_rate 70012 +host_op_rate 69995 +host_tick_rate 256014000 +host_mem_usage 260844 +host_seconds 0.08 +sim_insts 5792 +sim_ops 5792 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 21189000 +system.physmem.bytes_read::cpu.inst 21824 +system.physmem.bytes_read::cpu.data 6528 +system.physmem.bytes_read::total 28352 +system.physmem.bytes_inst_read::cpu.inst 21824 +system.physmem.bytes_inst_read::total 21824 +system.physmem.num_reads::cpu.inst 341 +system.physmem.num_reads::cpu.data 102 +system.physmem.num_reads::total 443 +system.physmem.bw_read::cpu.inst 1029968380 +system.physmem.bw_read::cpu.data 308084383 +system.physmem.bw_read::total 1338052763 +system.physmem.bw_inst_read::cpu.inst 1029968380 +system.physmem.bw_inst_read::total 1029968380 +system.physmem.bw_total::cpu.inst 1029968380 +system.physmem.bw_total::cpu.data 308084383 +system.physmem.bw_total::total 1338052763 +system.physmem.readReqs 444 +system.physmem.writeReqs 0 +system.physmem.readBursts 444 +system.physmem.writeBursts 0 +system.physmem.bytesReadDRAM 28416 +system.physmem.bytesReadWrQ 0 +system.physmem.bytesWritten 0 +system.physmem.bytesReadSys 28416 +system.physmem.bytesWrittenSys 0 +system.physmem.servicedByWrQ 0 +system.physmem.mergedWrBursts 0 +system.physmem.neitherReadNorWriteReqs 0 +system.physmem.perBankRdBursts::0 71 +system.physmem.perBankRdBursts::1 42 +system.physmem.perBankRdBursts::2 55 +system.physmem.perBankRdBursts::3 58 +system.physmem.perBankRdBursts::4 53 +system.physmem.perBankRdBursts::5 61 +system.physmem.perBankRdBursts::6 52 +system.physmem.perBankRdBursts::7 10 +system.physmem.perBankRdBursts::8 9 +system.physmem.perBankRdBursts::9 28 +system.physmem.perBankRdBursts::10 1 +system.physmem.perBankRdBursts::11 0 +system.physmem.perBankRdBursts::12 0 +system.physmem.perBankRdBursts::13 0 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+system.physmem.writePktSize::0 0 +system.physmem.writePktSize::1 0 +system.physmem.writePktSize::2 0 +system.physmem.writePktSize::3 0 +system.physmem.writePktSize::4 0 +system.physmem.writePktSize::5 0 +system.physmem.writePktSize::6 0 +system.physmem.rdQLenPdf::0 235 +system.physmem.rdQLenPdf::1 144 +system.physmem.rdQLenPdf::2 45 +system.physmem.rdQLenPdf::3 14 +system.physmem.rdQLenPdf::4 5 +system.physmem.rdQLenPdf::5 1 +system.physmem.rdQLenPdf::6 0 +system.physmem.rdQLenPdf::7 0 +system.physmem.rdQLenPdf::8 0 +system.physmem.rdQLenPdf::9 0 +system.physmem.rdQLenPdf::10 0 +system.physmem.rdQLenPdf::11 0 +system.physmem.rdQLenPdf::12 0 +system.physmem.rdQLenPdf::13 0 +system.physmem.rdQLenPdf::14 0 +system.physmem.rdQLenPdf::15 0 +system.physmem.rdQLenPdf::16 0 +system.physmem.rdQLenPdf::17 0 +system.physmem.rdQLenPdf::18 0 +system.physmem.rdQLenPdf::19 0 +system.physmem.rdQLenPdf::20 0 +system.physmem.rdQLenPdf::21 0 +system.physmem.rdQLenPdf::22 0 +system.physmem.rdQLenPdf::23 0 +system.physmem.rdQLenPdf::24 0 +system.physmem.rdQLenPdf::25 0 +system.physmem.rdQLenPdf::26 0 +system.physmem.rdQLenPdf::27 0 +system.physmem.rdQLenPdf::28 0 +system.physmem.rdQLenPdf::29 0 +system.physmem.rdQLenPdf::30 0 +system.physmem.rdQLenPdf::31 0 +system.physmem.wrQLenPdf::0 0 +system.physmem.wrQLenPdf::1 0 +system.physmem.wrQLenPdf::2 0 +system.physmem.wrQLenPdf::3 0 +system.physmem.wrQLenPdf::4 0 +system.physmem.wrQLenPdf::5 0 +system.physmem.wrQLenPdf::6 0 +system.physmem.wrQLenPdf::7 0 +system.physmem.wrQLenPdf::8 0 +system.physmem.wrQLenPdf::9 0 +system.physmem.wrQLenPdf::10 0 +system.physmem.wrQLenPdf::11 0 +system.physmem.wrQLenPdf::12 0 +system.physmem.wrQLenPdf::13 0 +system.physmem.wrQLenPdf::14 0 +system.physmem.wrQLenPdf::15 0 +system.physmem.wrQLenPdf::16 0 +system.physmem.wrQLenPdf::17 0 +system.physmem.wrQLenPdf::18 0 +system.physmem.wrQLenPdf::19 0 +system.physmem.wrQLenPdf::20 0 +system.physmem.wrQLenPdf::21 0 +system.physmem.wrQLenPdf::22 0 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+system.physmem.wrQLenPdf::54 0 +system.physmem.wrQLenPdf::55 0 +system.physmem.wrQLenPdf::56 0 +system.physmem.wrQLenPdf::57 0 +system.physmem.wrQLenPdf::58 0 +system.physmem.wrQLenPdf::59 0 +system.physmem.wrQLenPdf::60 0 +system.physmem.wrQLenPdf::61 0 +system.physmem.wrQLenPdf::62 0 +system.physmem.wrQLenPdf::63 0 +system.physmem.bytesPerActivate::samples 76 +system.physmem.bytesPerActivate::mean 348.631579 +system.physmem.bytesPerActivate::gmean 212.894378 +system.physmem.bytesPerActivate::stdev 337.912685 +system.physmem.bytesPerActivate::0-127 24 31.58% 31.58% +system.physmem.bytesPerActivate::128-255 17 22.37% 53.95% +system.physmem.bytesPerActivate::256-383 12 15.79% 69.74% +system.physmem.bytesPerActivate::384-511 2 2.63% 72.37% +system.physmem.bytesPerActivate::512-639 3 3.95% 76.32% +system.physmem.bytesPerActivate::640-767 4 5.26% 81.58% +system.physmem.bytesPerActivate::768-895 2 2.63% 84.21% +system.physmem.bytesPerActivate::896-1023 3 3.95% 88.16% +system.physmem.bytesPerActivate::1024-1151 9 11.84% 100.00% +system.physmem.bytesPerActivate::total 76 +system.physmem.totQLat 5920000 +system.physmem.totMemAccLat 14245000 +system.physmem.totBusLat 2220000 +system.physmem.avgQLat 13333.33 +system.physmem.avgBusLat 5000.00 +system.physmem.avgMemAccLat 32083.33 +system.physmem.avgRdBW 1341.07 +system.physmem.avgWrBW 0.00 +system.physmem.avgRdBWSys 1341.07 +system.physmem.avgWrBWSys 0.00 +system.physmem.peakBW 12800.00 +system.physmem.busUtil 10.48 +system.physmem.busUtilRead 10.48 +system.physmem.busUtilWrite 0.00 +system.physmem.avgRdQLen 1.82 +system.physmem.avgWrQLen 0.00 +system.physmem.readRowHits 358 +system.physmem.writeRowHits 0 +system.physmem.readRowHitRate 80.63 +system.physmem.writeRowHitRate nan +system.physmem.avgGap 47586.71 +system.physmem.pageHitRate 80.63 +system.physmem_0.actEnergy 528360 +system.physmem_0.preEnergy 254265 +system.physmem_0.readEnergy 2870280 +system.physmem_0.writeEnergy 0 +system.physmem_0.refreshEnergy 1229280.000000 +system.physmem_0.actBackEnergy 3925590 +system.physmem_0.preBackEnergy 28320 +system.physmem_0.actPowerDownEnergy 5657820 +system.physmem_0.prePowerDownEnergy 38400 +system.physmem_0.selfRefreshEnergy 0 +system.physmem_0.totalEnergy 14532315 +system.physmem_0.averagePower 685.810052 +system.physmem_0.totalIdleTime 12505250 +system.physmem_0.memoryStateTime::IDLE 17500 +system.physmem_0.memoryStateTime::REF 520000 +system.physmem_0.memoryStateTime::SREF 0 +system.physmem_0.memoryStateTime::PRE_PDN 100250 +system.physmem_0.memoryStateTime::ACT 8146250 +system.physmem_0.memoryStateTime::ACT_PDN 12405000 +system.physmem_1.actEnergy 85680 +system.physmem_1.preEnergy 34155 +system.physmem_1.readEnergy 299880 +system.physmem_1.writeEnergy 0 +system.physmem_1.refreshEnergy 1229280.000000 +system.physmem_1.actBackEnergy 759810 +system.physmem_1.preBackEnergy 1412160 +system.physmem_1.actPowerDownEnergy 6380010 +system.physmem_1.prePowerDownEnergy 712320 +system.physmem_1.selfRefreshEnergy 0 +system.physmem_1.totalEnergy 10913295 +system.physmem_1.averagePower 515.021000 +system.physmem_1.totalIdleTime 13660000 +system.physmem_1.memoryStateTime::IDLE 3594000 +system.physmem_1.memoryStateTime::REF 520000 +system.physmem_1.memoryStateTime::SREF 0 +system.physmem_1.memoryStateTime::PRE_PDN 1854750 +system.physmem_1.memoryStateTime::ACT 1229000 +system.physmem_1.memoryStateTime::ACT_PDN 13991250 +system.pwrStateResidencyTicks::UNDEFINED 21189000 +system.cpu.branchPred.lookups 2458 +system.cpu.branchPred.condPredicted 2033 +system.cpu.branchPred.condIncorrect 409 +system.cpu.branchPred.BTBLookups 2104 +system.cpu.branchPred.BTBHits 724 +system.cpu.branchPred.BTBCorrect 0 +system.cpu.branchPred.BTBHitPct 34.410646 +system.cpu.branchPred.usedRAS 228 +system.cpu.branchPred.RASInCorrect 36 +system.cpu.branchPred.indirectLookups 135 +system.cpu.branchPred.indirectHits 18 +system.cpu.branchPred.indirectMisses 117 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0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 444 +system.membus.reqLayer0.occupancy 553000 +system.membus.reqLayer0.utilization 2.6 +system.membus.respLayer1.occupancy 2325750 +system.membus.respLayer1.utilization 11.0 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini index b654cdd15..a94f4dc46 100644 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini @@ -89,6 +89,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -119,7 +120,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -128,14 +129,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/power/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/power/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -159,6 +161,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -170,7 +173,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -178,6 +181,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -186,6 +196,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -193,7 +204,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr index aadc3d011..c0b55d123 100755 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout index cbf63eeba..e1a395fe5 100755 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/POWER/tests/opt/quick/se/00.hello/power/linux/simple gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:27:08 -gem5 started Jul 21 2016 14:27:33 -gem5 executing on e108600-lin, pid 28000 -command line: /work/curdun01/gem5-external.hg/build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/power/linux/simple-atomic +gem5 compiled Apr 3 2017 19:22:30 +gem5 started Apr 3 2017 19:22:48 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 103795 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/power/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 2896000 because target called exit() +Exiting @ tick 2896000 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt index d149f60ec..ecd255c85 100644 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt @@ -1,153 +1,153 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2896000 # Number of ticks simulated -final_tick 2896000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1025115 # Simulator instruction rate (inst/s) -host_op_rate 1023244 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 510651564 # Simulator tick rate (ticks/s) -host_mem_usage 238048 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 5793 # Number of instructions simulated -sim_ops 5793 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2896000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 23172 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 3720 # Number of bytes read from this memory -system.physmem.bytes_read::total 26892 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 23172 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 23172 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 4209 # Number of bytes written to this memory -system.physmem.bytes_written::total 4209 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 5793 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 961 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6754 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 1046 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1046 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 8001381215 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1284530387 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9285911602 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8001381215 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8001381215 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1453383978 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1453383978 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8001381215 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2737914365 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10739295580 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 2896000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 9 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 2896000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 5793 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5793 # Number of instructions committed -system.cpu.committedOps 5793 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 5698 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 22 # Number of float alu accesses -system.cpu.num_func_calls 200 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 895 # number of instructions that are conditional controls -system.cpu.num_int_insts 5698 # number of integer instructions -system.cpu.num_fp_insts 22 # number of float instructions -system.cpu.num_int_register_reads 9529 # number of times the integer registers were read -system.cpu.num_int_register_writes 4996 # number of times the integer registers were written -system.cpu.num_fp_register_reads 20 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2 # number of times the floating registers were written -system.cpu.num_mem_refs 2007 # number of memory refs -system.cpu.num_load_insts 961 # Number of load instructions -system.cpu.num_store_insts 1046 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 5792.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1037 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 3784 65.32% 65.32% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 65.32% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 65.32% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.03% 65.35% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::MemRead 960 16.57% 81.93% # Class of executed instruction -system.cpu.op_class::MemWrite 1027 17.73% 99.65% # Class of executed instruction -system.cpu.op_class::FloatMemRead 1 0.02% 99.67% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 19 0.33% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5793 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2896000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 6754 # Transaction distribution -system.membus.trans_dist::ReadResp 6754 # Transaction distribution -system.membus.trans_dist::WriteReq 1046 # Transaction distribution -system.membus.trans_dist::WriteResp 1046 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 11586 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4014 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 15600 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 23172 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 7929 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 31101 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 7800 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7800 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7800 # Request fanout histogram +sim_seconds 0.000003 +sim_ticks 2896000 +final_tick 2896000 +sim_freq 1000000000000 +host_inst_rate 591136 +host_op_rate 589882 +host_tick_rate 294306849 +host_mem_usage 250080 +host_seconds 0.01 +sim_insts 5793 +sim_ops 5793 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 2896000 +system.physmem.bytes_read::cpu.inst 23172 +system.physmem.bytes_read::cpu.data 3720 +system.physmem.bytes_read::total 26892 +system.physmem.bytes_inst_read::cpu.inst 23172 +system.physmem.bytes_inst_read::total 23172 +system.physmem.bytes_written::cpu.data 4209 +system.physmem.bytes_written::total 4209 +system.physmem.num_reads::cpu.inst 5793 +system.physmem.num_reads::cpu.data 961 +system.physmem.num_reads::total 6754 +system.physmem.num_writes::cpu.data 1046 +system.physmem.num_writes::total 1046 +system.physmem.bw_read::cpu.inst 8001381215 +system.physmem.bw_read::cpu.data 1284530387 +system.physmem.bw_read::total 9285911602 +system.physmem.bw_inst_read::cpu.inst 8001381215 +system.physmem.bw_inst_read::total 8001381215 +system.physmem.bw_write::cpu.data 1453383978 +system.physmem.bw_write::total 1453383978 +system.physmem.bw_total::cpu.inst 8001381215 +system.physmem.bw_total::cpu.data 2737914365 +system.physmem.bw_total::total 10739295580 +system.pwrStateResidencyTicks::UNDEFINED 2896000 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 9 +system.cpu.pwrStateResidencyTicks::ON 2896000 +system.cpu.numCycles 5793 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 5793 +system.cpu.committedOps 5793 +system.cpu.num_int_alu_accesses 5698 +system.cpu.num_fp_alu_accesses 22 +system.cpu.num_func_calls 200 +system.cpu.num_conditional_control_insts 895 +system.cpu.num_int_insts 5698 +system.cpu.num_fp_insts 22 +system.cpu.num_int_register_reads 9529 +system.cpu.num_int_register_writes 4996 +system.cpu.num_fp_register_reads 20 +system.cpu.num_fp_register_writes 2 +system.cpu.num_mem_refs 2007 +system.cpu.num_load_insts 961 +system.cpu.num_store_insts 1046 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 5793 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 1037 +system.cpu.op_class::No_OpClass 0 0.00% 0.00% +system.cpu.op_class::IntAlu 3784 65.32% 65.32% +system.cpu.op_class::IntMult 0 0.00% 65.32% +system.cpu.op_class::IntDiv 0 0.00% 65.32% +system.cpu.op_class::FloatAdd 2 0.03% 65.35% +system.cpu.op_class::FloatCmp 0 0.00% 65.35% +system.cpu.op_class::FloatCvt 0 0.00% 65.35% +system.cpu.op_class::FloatMult 0 0.00% 65.35% +system.cpu.op_class::FloatMultAcc 0 0.00% 65.35% +system.cpu.op_class::FloatDiv 0 0.00% 65.35% +system.cpu.op_class::FloatMisc 0 0.00% 65.35% +system.cpu.op_class::FloatSqrt 0 0.00% 65.35% +system.cpu.op_class::SimdAdd 0 0.00% 65.35% +system.cpu.op_class::SimdAddAcc 0 0.00% 65.35% +system.cpu.op_class::SimdAlu 0 0.00% 65.35% +system.cpu.op_class::SimdCmp 0 0.00% 65.35% +system.cpu.op_class::SimdCvt 0 0.00% 65.35% +system.cpu.op_class::SimdMisc 0 0.00% 65.35% +system.cpu.op_class::SimdMult 0 0.00% 65.35% +system.cpu.op_class::SimdMultAcc 0 0.00% 65.35% +system.cpu.op_class::SimdShift 0 0.00% 65.35% +system.cpu.op_class::SimdShiftAcc 0 0.00% 65.35% +system.cpu.op_class::SimdSqrt 0 0.00% 65.35% +system.cpu.op_class::SimdFloatAdd 0 0.00% 65.35% +system.cpu.op_class::SimdFloatAlu 0 0.00% 65.35% +system.cpu.op_class::SimdFloatCmp 0 0.00% 65.35% +system.cpu.op_class::SimdFloatCvt 0 0.00% 65.35% +system.cpu.op_class::SimdFloatDiv 0 0.00% 65.35% +system.cpu.op_class::SimdFloatMisc 0 0.00% 65.35% +system.cpu.op_class::SimdFloatMult 0 0.00% 65.35% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.35% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.35% +system.cpu.op_class::MemRead 960 16.57% 81.93% +system.cpu.op_class::MemWrite 1027 17.73% 99.65% +system.cpu.op_class::FloatMemRead 1 0.02% 99.67% +system.cpu.op_class::FloatMemWrite 19 0.33% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 5793 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 2896000 +system.membus.trans_dist::ReadReq 6754 +system.membus.trans_dist::ReadResp 6754 +system.membus.trans_dist::WriteReq 1046 +system.membus.trans_dist::WriteResp 1046 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 11586 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4014 +system.membus.pkt_count::total 15600 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 23172 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 7929 +system.membus.pkt_size::total 31101 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 7800 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 7800 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 7800 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini index c79232133..90a496871 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini @@ -88,6 +88,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -118,7 +119,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -127,14 +128,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/sparc/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -158,6 +160,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -169,7 +172,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -177,6 +180,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -185,6 +195,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -192,7 +203,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simerr index aadc3d011..c0b55d123 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simerr +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout index 0783a6d90..cac26c8a8 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout @@ -3,11 +3,10 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:30:06 -gem5 started Jul 21 2016 14:30:36 -gem5 executing on e108600-lin, pid 38676 -command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/sparc/linux/simple-atomic +gem5 compiled Apr 3 2017 18:41:19 +gem5 started Apr 3 2017 18:41:40 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 64886 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 2694500 because target called exit() +Hello World!Exiting @ tick 2694500 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt index 22810bda7..6ce9e512f 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt @@ -1,135 +1,135 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2694500 # Number of ticks simulated -final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 818529 # Simulator instruction rate (inst/s) -host_op_rate 815458 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 411063520 # Simulator tick rate (ticks/s) -host_mem_usage 239556 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 5327 # Number of instructions simulated -sim_ops 5327 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2694500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 21480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 4602 # Number of bytes read from this memory -system.physmem.bytes_read::total 26082 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 21480 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 21480 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 5065 # Number of bytes written to this memory -system.physmem.bytes_written::total 5065 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 5370 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 715 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6085 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 673 # Number of write requests responded to by this memory -system.physmem.num_writes::total 673 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7971794396 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1707923548 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9679717944 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7971794396 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7971794396 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1879755057 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1879755057 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7971794396 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3587678605 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11559473001 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 2694500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.numSyscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 2694500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 5390 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5327 # Number of instructions committed -system.cpu.committedOps 5327 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4505 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 146 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 773 # number of instructions that are conditional controls -system.cpu.num_int_insts 4505 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 10598 # number of times the integer registers were read -system.cpu.num_int_register_writes 4846 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 1401 # number of memory refs -system.cpu.num_load_insts 723 # Number of load instructions -system.cpu.num_store_insts 678 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 5389.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1121 # Number of branches fetched -system.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction -system.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::MemRead 723 13.46% 87.37% # Class of executed instruction -system.cpu.op_class::MemWrite 678 12.63% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5370 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2694500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 6085 # Transaction distribution -system.membus.trans_dist::ReadResp 6085 # Transaction distribution -system.membus.trans_dist::WriteReq 673 # Transaction distribution -system.membus.trans_dist::WriteResp 673 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 10740 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 2776 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 13516 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 21480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 9667 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 31147 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 6758 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 6758 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 6758 # Request fanout histogram +sim_seconds 0.000003 +sim_ticks 2694500 +final_tick 2694500 +sim_freq 1000000000000 +host_inst_rate 549051 +host_op_rate 547755 +host_tick_rate 276495662 +host_mem_usage 251832 +host_seconds 0.01 +sim_insts 5327 +sim_ops 5327 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 2694500 +system.physmem.bytes_read::cpu.inst 21480 +system.physmem.bytes_read::cpu.data 4602 +system.physmem.bytes_read::total 26082 +system.physmem.bytes_inst_read::cpu.inst 21480 +system.physmem.bytes_inst_read::total 21480 +system.physmem.bytes_written::cpu.data 5065 +system.physmem.bytes_written::total 5065 +system.physmem.num_reads::cpu.inst 5370 +system.physmem.num_reads::cpu.data 715 +system.physmem.num_reads::total 6085 +system.physmem.num_writes::cpu.data 673 +system.physmem.num_writes::total 673 +system.physmem.bw_read::cpu.inst 7971794396 +system.physmem.bw_read::cpu.data 1707923548 +system.physmem.bw_read::total 9679717944 +system.physmem.bw_inst_read::cpu.inst 7971794396 +system.physmem.bw_inst_read::total 7971794396 +system.physmem.bw_write::cpu.data 1879755057 +system.physmem.bw_write::total 1879755057 +system.physmem.bw_total::cpu.inst 7971794396 +system.physmem.bw_total::cpu.data 3587678605 +system.physmem.bw_total::total 11559473001 +system.pwrStateResidencyTicks::UNDEFINED 2694500 +system.cpu_clk_domain.clock 500 +system.cpu.workload.numSyscalls 11 +system.cpu.pwrStateResidencyTicks::ON 2694500 +system.cpu.numCycles 5390 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 5327 +system.cpu.committedOps 5327 +system.cpu.num_int_alu_accesses 4505 +system.cpu.num_fp_alu_accesses 0 +system.cpu.num_func_calls 146 +system.cpu.num_conditional_control_insts 773 +system.cpu.num_int_insts 4505 +system.cpu.num_fp_insts 0 +system.cpu.num_int_register_reads 10598 +system.cpu.num_int_register_writes 4846 +system.cpu.num_fp_register_reads 0 +system.cpu.num_fp_register_writes 0 +system.cpu.num_mem_refs 1401 +system.cpu.num_load_insts 723 +system.cpu.num_store_insts 678 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 5390 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 1121 +system.cpu.op_class::No_OpClass 173 3.22% 3.22% +system.cpu.op_class::IntAlu 3796 70.69% 73.91% +system.cpu.op_class::IntMult 0 0.00% 73.91% +system.cpu.op_class::IntDiv 0 0.00% 73.91% +system.cpu.op_class::FloatAdd 0 0.00% 73.91% +system.cpu.op_class::FloatCmp 0 0.00% 73.91% +system.cpu.op_class::FloatCvt 0 0.00% 73.91% +system.cpu.op_class::FloatMult 0 0.00% 73.91% +system.cpu.op_class::FloatMultAcc 0 0.00% 73.91% +system.cpu.op_class::FloatDiv 0 0.00% 73.91% +system.cpu.op_class::FloatMisc 0 0.00% 73.91% +system.cpu.op_class::FloatSqrt 0 0.00% 73.91% +system.cpu.op_class::SimdAdd 0 0.00% 73.91% +system.cpu.op_class::SimdAddAcc 0 0.00% 73.91% +system.cpu.op_class::SimdAlu 0 0.00% 73.91% +system.cpu.op_class::SimdCmp 0 0.00% 73.91% +system.cpu.op_class::SimdCvt 0 0.00% 73.91% +system.cpu.op_class::SimdMisc 0 0.00% 73.91% +system.cpu.op_class::SimdMult 0 0.00% 73.91% +system.cpu.op_class::SimdMultAcc 0 0.00% 73.91% +system.cpu.op_class::SimdShift 0 0.00% 73.91% +system.cpu.op_class::SimdShiftAcc 0 0.00% 73.91% +system.cpu.op_class::SimdSqrt 0 0.00% 73.91% +system.cpu.op_class::SimdFloatAdd 0 0.00% 73.91% +system.cpu.op_class::SimdFloatAlu 0 0.00% 73.91% +system.cpu.op_class::SimdFloatCmp 0 0.00% 73.91% +system.cpu.op_class::SimdFloatCvt 0 0.00% 73.91% +system.cpu.op_class::SimdFloatDiv 0 0.00% 73.91% +system.cpu.op_class::SimdFloatMisc 0 0.00% 73.91% +system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% +system.cpu.op_class::MemRead 723 13.46% 87.37% +system.cpu.op_class::MemWrite 678 12.63% 100.00% +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 5370 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 2694500 +system.membus.trans_dist::ReadReq 6085 +system.membus.trans_dist::ReadResp 6085 +system.membus.trans_dist::WriteReq 673 +system.membus.trans_dist::WriteResp 673 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 10740 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 2776 +system.membus.pkt_count::total 13516 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 21480 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 9667 +system.membus.pkt_size::total 31147 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 6758 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 6758 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 6758 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini index 7609bf228..74133b340 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini @@ -85,6 +85,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -122,7 +123,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -131,14 +132,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/sparc/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -297,6 +299,7 @@ type=RubyDirectoryMemory eventq_index=0 numa_high_bit=5 size=268435456 +system=system version=0 [system.ruby.dir_cntrl0.dmaRequestToDir] diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr index f6f6f15a5..95500d55b 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr @@ -7,4 +7,5 @@ warn: rounding error > tolerance warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout index 36ed80c84..8d604768a 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout @@ -3,11 +3,10 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 13 2016 20:43:27 -gem5 started Oct 13 2016 20:46:33 -gem5 executing on e108600-lin, pid 17405 -command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/sparc/linux/simple-timing-ruby +gem5 compiled Apr 3 2017 18:41:19 +gem5 started Apr 3 2017 18:41:37 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 64825 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/sparc/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 86746 because target called exit() +Hello World!Exiting @ tick 86746 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt index 05934eae0..83a3d1ad4 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt @@ -1,355 +1,355 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000087 # Number of seconds simulated -sim_ticks 86746 # Number of ticks simulated -final_tick 86746 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 122857 # Simulator instruction rate (inst/s) -host_op_rate 122829 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1999767 # Simulator tick rate (ticks/s) -host_mem_usage 415460 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -sim_insts 5327 # Number of instructions simulated -sim_ops 5327 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 82496 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 82496 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 82240 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 82240 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 1289 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 1289 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 1285 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 1285 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 951006386 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 951006386 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 948055242 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 948055242 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1899061628 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1899061628 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 1289 # Number of read requests accepted -system.mem_ctrls.writeReqs 1285 # Number of write requests accepted -system.mem_ctrls.readBursts 1289 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 1285 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 44800 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 37696 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 45504 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 82496 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 82240 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 589 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 555 # Number of DRAM write bursts merged with an existing one -system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 28 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 17 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 8 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 119 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 121 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 141 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 55 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 31 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 13 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 62 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 21 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 61 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 14 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 8 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 28 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 18 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 1 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 8 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 118 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 114 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 141 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 61 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 35 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 14 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 62 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 23 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 64 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 16 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 8 # Per bank write bursts -system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 86680 # Total gap between requests -system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 1289 # Read request sizes (log2) -system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 1285 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 700 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 3 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 3 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 35 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 45 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 45 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 49 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 49 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 46 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 44 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 44 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 44 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 44 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 44 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 44 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 44 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 44 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 44 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 44 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 247 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 359.384615 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 236.451062 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 319.751749 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 54 21.86% 21.86% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 65 26.32% 48.18% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 38 15.38% 63.56% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 27 10.93% 74.49% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 8 3.24% 77.73% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 10 4.05% 81.78% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 11 4.45% 86.23% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 9 3.64% 89.88% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 25 10.12% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 247 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 44 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 15.840909 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 15.640724 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 3.183849 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-13 2 4.55% 4.55% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 21 47.73% 52.27% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 18 40.91% 93.18% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 2 4.55% 97.73% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::34-35 1 2.27% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 44 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 44 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.159091 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.147705 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.644951 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 41 93.18% 93.18% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 1 2.27% 95.45% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 2 4.55% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 44 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 12987 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 26287 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3500 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 18.55 # Average queueing delay per DRAM burst -system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 37.55 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 516.45 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 524.57 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 951.01 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 948.06 # Average system write bandwidth in MiByte/s -system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 8.13 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.03 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 4.10 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 25.18 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 508 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 652 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 72.57 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 89.32 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 33.68 # Average gap between requests -system.mem_ctrls.pageHitRate 81.12 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 1099560 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 587328 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 4969440 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 3574656 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 6761040.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 10338432 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 148224 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.actPowerDownEnergy 27605784 # Energy for active power-down per rank (pJ) -system.mem_ctrls_0.prePowerDownEnergy 1209216 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrls_0.totalEnergy 56293680 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 648.948424 # Core power per rank (mW) -system.mem_ctrls_0.totalIdleTime 63519 # Total Idle time Per DRAM Rank -system.mem_ctrls_0.memoryStateTime::IDLE 64 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 2860 # Time in different power states -system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 3149 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 20134 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 60539 # Time in different power states -system.mem_ctrls_1.actEnergy 692580 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 367080 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 3027360 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 2363616 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 6761040.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 9621600 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 296448 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.actPowerDownEnergy 26302992 # Energy for active power-down per rank (pJ) -system.mem_ctrls_1.prePowerDownEnergy 2761728 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrls_1.totalEnergy 52194444 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 601.692804 # Core power per rank (mW) -system.mem_ctrls_1.totalIdleTime 64843 # Total Idle time Per DRAM Rank -system.mem_ctrls_1.memoryStateTime::IDLE 422 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 2860 # Time in different power states -system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 7192 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 18590 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 57682 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states -system.cpu.clk_domain.clock 1 # Clock period in ticks -system.cpu.workload.numSyscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 86746 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 86746 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5327 # Number of instructions committed -system.cpu.committedOps 5327 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4505 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 146 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 773 # number of instructions that are conditional controls -system.cpu.num_int_insts 4505 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 10598 # number of times the integer registers were read -system.cpu.num_int_register_writes 4845 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 1401 # number of memory refs -system.cpu.num_load_insts 723 # Number of load instructions -system.cpu.num_store_insts 678 # Number of store instructions -system.cpu.num_idle_cycles 0.999988 # Number of idle cycles -system.cpu.num_busy_cycles 86745.000012 # Number of busy cycles -system.cpu.not_idle_fraction 0.999988 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000012 # Percentage of idle cycles -system.cpu.Branches 1121 # Number of branches fetched -system.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction -system.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::MemRead 723 13.46% 87.37% # Class of executed instruction -system.cpu.op_class::MemWrite 678 12.63% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5370 # Class of executed instruction -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states -system.ruby.delayHist::bucket_size 1 # delay histogram for all message -system.ruby.delayHist::max_bucket 9 # delay histogram for all message -system.ruby.delayHist::samples 2574 # delay histogram for all message -system.ruby.delayHist | 2574 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 2574 # delay histogram for all message +sim_seconds 0.000087 +sim_ticks 86746 +final_tick 86746 +sim_freq 1000000000 +host_inst_rate 50496 +host_op_rate 50484 +host_tick_rate 821944 +host_mem_usage 426428 +host_seconds 0.11 +sim_insts 5327 +sim_ops 5327 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1 +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 86746 +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 82496 +system.mem_ctrls.bytes_read::total 82496 +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 82240 +system.mem_ctrls.bytes_written::total 82240 +system.mem_ctrls.num_reads::ruby.dir_cntrl0 1289 +system.mem_ctrls.num_reads::total 1289 +system.mem_ctrls.num_writes::ruby.dir_cntrl0 1285 +system.mem_ctrls.num_writes::total 1285 +system.mem_ctrls.bw_read::ruby.dir_cntrl0 951006386 +system.mem_ctrls.bw_read::total 951006386 +system.mem_ctrls.bw_write::ruby.dir_cntrl0 948055242 +system.mem_ctrls.bw_write::total 948055242 +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1899061628 +system.mem_ctrls.bw_total::total 1899061628 +system.mem_ctrls.readReqs 1289 +system.mem_ctrls.writeReqs 1285 +system.mem_ctrls.readBursts 1289 +system.mem_ctrls.writeBursts 1285 +system.mem_ctrls.bytesReadDRAM 44800 +system.mem_ctrls.bytesReadWrQ 37696 +system.mem_ctrls.bytesWritten 45504 +system.mem_ctrls.bytesReadSys 82496 +system.mem_ctrls.bytesWrittenSys 82240 +system.mem_ctrls.servicedByWrQ 589 +system.mem_ctrls.mergedWrBursts 555 +system.mem_ctrls.neitherReadNorWriteReqs 0 +system.mem_ctrls.perBankRdBursts::0 28 +system.mem_ctrls.perBankRdBursts::1 17 +system.mem_ctrls.perBankRdBursts::2 1 +system.mem_ctrls.perBankRdBursts::3 8 +system.mem_ctrls.perBankRdBursts::4 0 +system.mem_ctrls.perBankRdBursts::5 119 +system.mem_ctrls.perBankRdBursts::6 121 +system.mem_ctrls.perBankRdBursts::7 141 +system.mem_ctrls.perBankRdBursts::8 55 +system.mem_ctrls.perBankRdBursts::9 31 +system.mem_ctrls.perBankRdBursts::10 13 +system.mem_ctrls.perBankRdBursts::11 62 +system.mem_ctrls.perBankRdBursts::12 21 +system.mem_ctrls.perBankRdBursts::13 61 +system.mem_ctrls.perBankRdBursts::14 14 +system.mem_ctrls.perBankRdBursts::15 8 +system.mem_ctrls.perBankWrBursts::0 28 +system.mem_ctrls.perBankWrBursts::1 18 +system.mem_ctrls.perBankWrBursts::2 1 +system.mem_ctrls.perBankWrBursts::3 8 +system.mem_ctrls.perBankWrBursts::4 0 +system.mem_ctrls.perBankWrBursts::5 118 +system.mem_ctrls.perBankWrBursts::6 114 +system.mem_ctrls.perBankWrBursts::7 141 +system.mem_ctrls.perBankWrBursts::8 61 +system.mem_ctrls.perBankWrBursts::9 35 +system.mem_ctrls.perBankWrBursts::10 14 +system.mem_ctrls.perBankWrBursts::11 62 +system.mem_ctrls.perBankWrBursts::12 23 +system.mem_ctrls.perBankWrBursts::13 64 +system.mem_ctrls.perBankWrBursts::14 16 +system.mem_ctrls.perBankWrBursts::15 8 +system.mem_ctrls.numRdRetry 0 +system.mem_ctrls.numWrRetry 0 +system.mem_ctrls.totGap 86680 +system.mem_ctrls.readPktSize::0 0 +system.mem_ctrls.readPktSize::1 0 +system.mem_ctrls.readPktSize::2 0 +system.mem_ctrls.readPktSize::3 0 +system.mem_ctrls.readPktSize::4 0 +system.mem_ctrls.readPktSize::5 0 +system.mem_ctrls.readPktSize::6 1289 +system.mem_ctrls.writePktSize::0 0 +system.mem_ctrls.writePktSize::1 0 +system.mem_ctrls.writePktSize::2 0 +system.mem_ctrls.writePktSize::3 0 +system.mem_ctrls.writePktSize::4 0 +system.mem_ctrls.writePktSize::5 0 +system.mem_ctrls.writePktSize::6 1285 +system.mem_ctrls.rdQLenPdf::0 700 +system.mem_ctrls.rdQLenPdf::1 0 +system.mem_ctrls.rdQLenPdf::2 0 +system.mem_ctrls.rdQLenPdf::3 0 +system.mem_ctrls.rdQLenPdf::4 0 +system.mem_ctrls.rdQLenPdf::5 0 +system.mem_ctrls.rdQLenPdf::6 0 +system.mem_ctrls.rdQLenPdf::7 0 +system.mem_ctrls.rdQLenPdf::8 0 +system.mem_ctrls.rdQLenPdf::9 0 +system.mem_ctrls.rdQLenPdf::10 0 +system.mem_ctrls.rdQLenPdf::11 0 +system.mem_ctrls.rdQLenPdf::12 0 +system.mem_ctrls.rdQLenPdf::13 0 +system.mem_ctrls.rdQLenPdf::14 0 +system.mem_ctrls.rdQLenPdf::15 0 +system.mem_ctrls.rdQLenPdf::16 0 +system.mem_ctrls.rdQLenPdf::17 0 +system.mem_ctrls.rdQLenPdf::18 0 +system.mem_ctrls.rdQLenPdf::19 0 +system.mem_ctrls.rdQLenPdf::20 0 +system.mem_ctrls.rdQLenPdf::21 0 +system.mem_ctrls.rdQLenPdf::22 0 +system.mem_ctrls.rdQLenPdf::23 0 +system.mem_ctrls.rdQLenPdf::24 0 +system.mem_ctrls.rdQLenPdf::25 0 +system.mem_ctrls.rdQLenPdf::26 0 +system.mem_ctrls.rdQLenPdf::27 0 +system.mem_ctrls.rdQLenPdf::28 0 +system.mem_ctrls.rdQLenPdf::29 0 +system.mem_ctrls.rdQLenPdf::30 0 +system.mem_ctrls.rdQLenPdf::31 0 +system.mem_ctrls.wrQLenPdf::0 1 +system.mem_ctrls.wrQLenPdf::1 1 +system.mem_ctrls.wrQLenPdf::2 1 +system.mem_ctrls.wrQLenPdf::3 1 +system.mem_ctrls.wrQLenPdf::4 1 +system.mem_ctrls.wrQLenPdf::5 1 +system.mem_ctrls.wrQLenPdf::6 1 +system.mem_ctrls.wrQLenPdf::7 1 +system.mem_ctrls.wrQLenPdf::8 1 +system.mem_ctrls.wrQLenPdf::9 1 +system.mem_ctrls.wrQLenPdf::10 1 +system.mem_ctrls.wrQLenPdf::11 1 +system.mem_ctrls.wrQLenPdf::12 1 +system.mem_ctrls.wrQLenPdf::13 1 +system.mem_ctrls.wrQLenPdf::14 1 +system.mem_ctrls.wrQLenPdf::15 3 +system.mem_ctrls.wrQLenPdf::16 3 +system.mem_ctrls.wrQLenPdf::17 35 +system.mem_ctrls.wrQLenPdf::18 45 +system.mem_ctrls.wrQLenPdf::19 45 +system.mem_ctrls.wrQLenPdf::20 49 +system.mem_ctrls.wrQLenPdf::21 49 +system.mem_ctrls.wrQLenPdf::22 46 +system.mem_ctrls.wrQLenPdf::23 44 +system.mem_ctrls.wrQLenPdf::24 44 +system.mem_ctrls.wrQLenPdf::25 44 +system.mem_ctrls.wrQLenPdf::26 44 +system.mem_ctrls.wrQLenPdf::27 44 +system.mem_ctrls.wrQLenPdf::28 44 +system.mem_ctrls.wrQLenPdf::29 44 +system.mem_ctrls.wrQLenPdf::30 44 +system.mem_ctrls.wrQLenPdf::31 44 +system.mem_ctrls.wrQLenPdf::32 44 +system.mem_ctrls.wrQLenPdf::33 0 +system.mem_ctrls.wrQLenPdf::34 0 +system.mem_ctrls.wrQLenPdf::35 0 +system.mem_ctrls.wrQLenPdf::36 0 +system.mem_ctrls.wrQLenPdf::37 0 +system.mem_ctrls.wrQLenPdf::38 0 +system.mem_ctrls.wrQLenPdf::39 0 +system.mem_ctrls.wrQLenPdf::40 0 +system.mem_ctrls.wrQLenPdf::41 0 +system.mem_ctrls.wrQLenPdf::42 0 +system.mem_ctrls.wrQLenPdf::43 0 +system.mem_ctrls.wrQLenPdf::44 0 +system.mem_ctrls.wrQLenPdf::45 0 +system.mem_ctrls.wrQLenPdf::46 0 +system.mem_ctrls.wrQLenPdf::47 0 +system.mem_ctrls.wrQLenPdf::48 0 +system.mem_ctrls.wrQLenPdf::49 0 +system.mem_ctrls.wrQLenPdf::50 0 +system.mem_ctrls.wrQLenPdf::51 0 +system.mem_ctrls.wrQLenPdf::52 0 +system.mem_ctrls.wrQLenPdf::53 0 +system.mem_ctrls.wrQLenPdf::54 0 +system.mem_ctrls.wrQLenPdf::55 0 +system.mem_ctrls.wrQLenPdf::56 0 +system.mem_ctrls.wrQLenPdf::57 0 +system.mem_ctrls.wrQLenPdf::58 0 +system.mem_ctrls.wrQLenPdf::59 0 +system.mem_ctrls.wrQLenPdf::60 0 +system.mem_ctrls.wrQLenPdf::61 0 +system.mem_ctrls.wrQLenPdf::62 0 +system.mem_ctrls.wrQLenPdf::63 0 +system.mem_ctrls.bytesPerActivate::samples 247 +system.mem_ctrls.bytesPerActivate::mean 359.384615 +system.mem_ctrls.bytesPerActivate::gmean 236.451062 +system.mem_ctrls.bytesPerActivate::stdev 319.751749 +system.mem_ctrls.bytesPerActivate::0-127 54 21.86% 21.86% +system.mem_ctrls.bytesPerActivate::128-255 65 26.32% 48.18% +system.mem_ctrls.bytesPerActivate::256-383 38 15.38% 63.56% +system.mem_ctrls.bytesPerActivate::384-511 27 10.93% 74.49% +system.mem_ctrls.bytesPerActivate::512-639 8 3.24% 77.73% +system.mem_ctrls.bytesPerActivate::640-767 10 4.05% 81.78% +system.mem_ctrls.bytesPerActivate::768-895 11 4.45% 86.23% +system.mem_ctrls.bytesPerActivate::896-1023 9 3.64% 89.88% +system.mem_ctrls.bytesPerActivate::1024-1151 25 10.12% 100.00% +system.mem_ctrls.bytesPerActivate::total 247 +system.mem_ctrls.rdPerTurnAround::samples 44 +system.mem_ctrls.rdPerTurnAround::mean 15.840909 +system.mem_ctrls.rdPerTurnAround::gmean 15.640724 +system.mem_ctrls.rdPerTurnAround::stdev 3.183849 +system.mem_ctrls.rdPerTurnAround::12-13 2 4.55% 4.55% +system.mem_ctrls.rdPerTurnAround::14-15 21 47.73% 52.27% +system.mem_ctrls.rdPerTurnAround::16-17 18 40.91% 93.18% +system.mem_ctrls.rdPerTurnAround::18-19 2 4.55% 97.73% +system.mem_ctrls.rdPerTurnAround::34-35 1 2.27% 100.00% +system.mem_ctrls.rdPerTurnAround::total 44 +system.mem_ctrls.wrPerTurnAround::samples 44 +system.mem_ctrls.wrPerTurnAround::mean 16.159091 +system.mem_ctrls.wrPerTurnAround::gmean 16.147705 +system.mem_ctrls.wrPerTurnAround::stdev 0.644951 +system.mem_ctrls.wrPerTurnAround::16 41 93.18% 93.18% +system.mem_ctrls.wrPerTurnAround::17 1 2.27% 95.45% +system.mem_ctrls.wrPerTurnAround::19 2 4.55% 100.00% +system.mem_ctrls.wrPerTurnAround::total 44 +system.mem_ctrls.totQLat 12987 +system.mem_ctrls.totMemAccLat 26287 +system.mem_ctrls.totBusLat 3500 +system.mem_ctrls.avgQLat 18.55 +system.mem_ctrls.avgBusLat 5.00 +system.mem_ctrls.avgMemAccLat 37.55 +system.mem_ctrls.avgRdBW 516.45 +system.mem_ctrls.avgWrBW 524.57 +system.mem_ctrls.avgRdBWSys 951.01 +system.mem_ctrls.avgWrBWSys 948.06 +system.mem_ctrls.peakBW 12800.00 +system.mem_ctrls.busUtil 8.13 +system.mem_ctrls.busUtilRead 4.03 +system.mem_ctrls.busUtilWrite 4.10 +system.mem_ctrls.avgRdQLen 1.00 +system.mem_ctrls.avgWrQLen 25.18 +system.mem_ctrls.readRowHits 508 +system.mem_ctrls.writeRowHits 652 +system.mem_ctrls.readRowHitRate 72.57 +system.mem_ctrls.writeRowHitRate 89.32 +system.mem_ctrls.avgGap 33.68 +system.mem_ctrls.pageHitRate 81.12 +system.mem_ctrls_0.actEnergy 1099560 +system.mem_ctrls_0.preEnergy 587328 +system.mem_ctrls_0.readEnergy 4969440 +system.mem_ctrls_0.writeEnergy 3574656 +system.mem_ctrls_0.refreshEnergy 6761040.000000 +system.mem_ctrls_0.actBackEnergy 10338432 +system.mem_ctrls_0.preBackEnergy 148224 +system.mem_ctrls_0.actPowerDownEnergy 27605784 +system.mem_ctrls_0.prePowerDownEnergy 1209216 +system.mem_ctrls_0.selfRefreshEnergy 0 +system.mem_ctrls_0.totalEnergy 56293680 +system.mem_ctrls_0.averagePower 648.948424 +system.mem_ctrls_0.totalIdleTime 63519 +system.mem_ctrls_0.memoryStateTime::IDLE 64 +system.mem_ctrls_0.memoryStateTime::REF 2860 +system.mem_ctrls_0.memoryStateTime::SREF 0 +system.mem_ctrls_0.memoryStateTime::PRE_PDN 3149 +system.mem_ctrls_0.memoryStateTime::ACT 20134 +system.mem_ctrls_0.memoryStateTime::ACT_PDN 60539 +system.mem_ctrls_1.actEnergy 692580 +system.mem_ctrls_1.preEnergy 367080 +system.mem_ctrls_1.readEnergy 3027360 +system.mem_ctrls_1.writeEnergy 2363616 +system.mem_ctrls_1.refreshEnergy 6761040.000000 +system.mem_ctrls_1.actBackEnergy 9621600 +system.mem_ctrls_1.preBackEnergy 296448 +system.mem_ctrls_1.actPowerDownEnergy 26302992 +system.mem_ctrls_1.prePowerDownEnergy 2761728 +system.mem_ctrls_1.selfRefreshEnergy 0 +system.mem_ctrls_1.totalEnergy 52194444 +system.mem_ctrls_1.averagePower 601.692804 +system.mem_ctrls_1.totalIdleTime 64843 +system.mem_ctrls_1.memoryStateTime::IDLE 422 +system.mem_ctrls_1.memoryStateTime::REF 2860 +system.mem_ctrls_1.memoryStateTime::SREF 0 +system.mem_ctrls_1.memoryStateTime::PRE_PDN 7192 +system.mem_ctrls_1.memoryStateTime::ACT 18590 +system.mem_ctrls_1.memoryStateTime::ACT_PDN 57682 +system.pwrStateResidencyTicks::UNDEFINED 86746 +system.cpu.clk_domain.clock 1 +system.cpu.workload.numSyscalls 11 +system.cpu.pwrStateResidencyTicks::ON 86746 +system.cpu.numCycles 86746 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 5327 +system.cpu.committedOps 5327 +system.cpu.num_int_alu_accesses 4505 +system.cpu.num_fp_alu_accesses 0 +system.cpu.num_func_calls 146 +system.cpu.num_conditional_control_insts 773 +system.cpu.num_int_insts 4505 +system.cpu.num_fp_insts 0 +system.cpu.num_int_register_reads 10598 +system.cpu.num_int_register_writes 4845 +system.cpu.num_fp_register_reads 0 +system.cpu.num_fp_register_writes 0 +system.cpu.num_mem_refs 1401 +system.cpu.num_load_insts 723 +system.cpu.num_store_insts 678 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 86746 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 1121 +system.cpu.op_class::No_OpClass 173 3.22% 3.22% +system.cpu.op_class::IntAlu 3796 70.69% 73.91% +system.cpu.op_class::IntMult 0 0.00% 73.91% +system.cpu.op_class::IntDiv 0 0.00% 73.91% +system.cpu.op_class::FloatAdd 0 0.00% 73.91% +system.cpu.op_class::FloatCmp 0 0.00% 73.91% +system.cpu.op_class::FloatCvt 0 0.00% 73.91% +system.cpu.op_class::FloatMult 0 0.00% 73.91% +system.cpu.op_class::FloatMultAcc 0 0.00% 73.91% +system.cpu.op_class::FloatDiv 0 0.00% 73.91% +system.cpu.op_class::FloatMisc 0 0.00% 73.91% +system.cpu.op_class::FloatSqrt 0 0.00% 73.91% +system.cpu.op_class::SimdAdd 0 0.00% 73.91% +system.cpu.op_class::SimdAddAcc 0 0.00% 73.91% +system.cpu.op_class::SimdAlu 0 0.00% 73.91% +system.cpu.op_class::SimdCmp 0 0.00% 73.91% +system.cpu.op_class::SimdCvt 0 0.00% 73.91% +system.cpu.op_class::SimdMisc 0 0.00% 73.91% +system.cpu.op_class::SimdMult 0 0.00% 73.91% +system.cpu.op_class::SimdMultAcc 0 0.00% 73.91% +system.cpu.op_class::SimdShift 0 0.00% 73.91% +system.cpu.op_class::SimdShiftAcc 0 0.00% 73.91% +system.cpu.op_class::SimdSqrt 0 0.00% 73.91% +system.cpu.op_class::SimdFloatAdd 0 0.00% 73.91% +system.cpu.op_class::SimdFloatAlu 0 0.00% 73.91% +system.cpu.op_class::SimdFloatCmp 0 0.00% 73.91% +system.cpu.op_class::SimdFloatCvt 0 0.00% 73.91% +system.cpu.op_class::SimdFloatDiv 0 0.00% 73.91% +system.cpu.op_class::SimdFloatMisc 0 0.00% 73.91% +system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% +system.cpu.op_class::MemRead 723 13.46% 87.37% +system.cpu.op_class::MemWrite 678 12.63% 100.00% +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 5370 +system.ruby.clk_domain.clock 1 +system.ruby.pwrStateResidencyTicks::UNDEFINED 86746 +system.ruby.delayHist::bucket_size 1 +system.ruby.delayHist::max_bucket 9 +system.ruby.delayHist::samples 2574 +system.ruby.delayHist | 2574 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.delayHist::total 2574 system.ruby.outstanding_req_hist_seqr::bucket_size 1 system.ruby.outstanding_req_hist_seqr::max_bucket 9 system.ruby.outstanding_req_hist_seqr::samples 6759 @@ -381,36 +381,36 @@ system.ruby.miss_latency_hist_seqr::stdev 35.397665 system.ruby.miss_latency_hist_seqr | 610 47.32% 47.32% | 633 49.11% 96.43% | 36 2.79% 99.22% | 1 0.08% 99.30% | 6 0.47% 99.77% | 2 0.16% 99.92% | 0 0.00% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 1289 system.ruby.Directory.incomplete_times_seqr 1288 -system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.014813 # Average number of messages in buffer -system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.995735 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.029672 # Average number of messages in buffer -system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.745697 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.014859 # Average number of messages in buffer -system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999205 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.029672 # Average number of messages in buffer -system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999216 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.cacheMemory.demand_hits 5469 # Number of cache demand hits -system.ruby.l1_cntrl0.cacheMemory.demand_misses 1289 # Number of cache demand misses -system.ruby.l1_cntrl0.cacheMemory.demand_accesses 6758 # Number of cache demand accesses -system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.014813 # Average number of messages in buffer -system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.969659 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.077916 # Average number of messages in buffer -system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999988 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.059345 # Average number of messages in buffer -system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999931 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.014859 # Average number of messages in buffer -system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.993948 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.014813 # Average number of messages in buffer -system.ruby.network.routers0.port_buffers03.avg_stall_time 5.974063 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.014859 # Average number of messages in buffer -system.ruby.network.routers0.port_buffers04.avg_stall_time 5.994882 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.088925 # Average number of messages in buffer -system.ruby.network.routers0.port_buffers07.avg_stall_time 6.746619 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states +system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.014813 +system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.995735 +system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.029672 +system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.745697 +system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.014859 +system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999205 +system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.029672 +system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999216 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 86746 +system.ruby.l1_cntrl0.cacheMemory.demand_hits 5469 +system.ruby.l1_cntrl0.cacheMemory.demand_misses 1289 +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 6758 +system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.014813 +system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.969659 +system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.077916 +system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999988 +system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.059345 +system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999931 +system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.014859 +system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.993948 +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 86746 +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 86746 +system.ruby.memctrl_clk_domain.clock 3 +system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.014813 +system.ruby.network.routers0.port_buffers03.avg_stall_time 5.974063 +system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.014859 +system.ruby.network.routers0.port_buffers04.avg_stall_time 5.994882 +system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.088925 +system.ruby.network.routers0.port_buffers07.avg_stall_time 6.746619 +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 86746 system.ruby.network.routers0.percent_links_utilized 7.418209 system.ruby.network.routers0.msg_count.Control::2 1289 system.ruby.network.routers0.msg_count.Data::2 1285 @@ -420,13 +420,13 @@ system.ruby.network.routers0.msg_bytes.Control::2 10312 system.ruby.network.routers0.msg_bytes.Data::2 92520 system.ruby.network.routers0.msg_bytes.Response_Data::4 92808 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 10280 -system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.029672 # Average number of messages in buffer -system.ruby.network.routers1.port_buffers02.avg_stall_time 10.745928 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.014813 # Average number of messages in buffer -system.ruby.network.routers1.port_buffers06.avg_stall_time 1.991446 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.014859 # Average number of messages in buffer -system.ruby.network.routers1.port_buffers07.avg_stall_time 1.998386 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.029672 +system.ruby.network.routers1.port_buffers02.avg_stall_time 10.745928 +system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.014813 +system.ruby.network.routers1.port_buffers06.avg_stall_time 1.991446 +system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.014859 +system.ruby.network.routers1.port_buffers07.avg_stall_time 1.998386 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 86746 system.ruby.network.routers1.percent_links_utilized 7.418209 system.ruby.network.routers1.msg_count.Control::2 1289 system.ruby.network.routers1.msg_count.Data::2 1285 @@ -436,25 +436,25 @@ system.ruby.network.routers1.msg_bytes.Control::2 10312 system.ruby.network.routers1.msg_bytes.Data::2 92520 system.ruby.network.routers1.msg_bytes.Response_Data::4 92808 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 10280 -system.ruby.network.int_link_buffers02.avg_buf_msgs 0.029672 # Average number of messages in buffer -system.ruby.network.int_link_buffers02.avg_stall_time 7.746481 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers08.avg_buf_msgs 0.014813 # Average number of messages in buffer -system.ruby.network.int_link_buffers08.avg_stall_time 2.987135 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers09.avg_buf_msgs 0.014859 # Average number of messages in buffer -system.ruby.network.int_link_buffers09.avg_stall_time 2.997545 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers13.avg_buf_msgs 0.014813 # Average number of messages in buffer -system.ruby.network.int_link_buffers13.avg_stall_time 4.978443 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers14.avg_buf_msgs 0.014859 # Average number of messages in buffer -system.ruby.network.int_link_buffers14.avg_stall_time 4.995792 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers17.avg_buf_msgs 0.029672 # Average number of messages in buffer -system.ruby.network.int_link_buffers17.avg_stall_time 9.746135 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.014813 # Average number of messages in buffer -system.ruby.network.routers2.port_buffers03.avg_stall_time 3.982801 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.014859 # Average number of messages in buffer -system.ruby.network.routers2.port_buffers04.avg_stall_time 3.996680 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.029672 # Average number of messages in buffer -system.ruby.network.routers2.port_buffers07.avg_stall_time 8.746320 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states +system.ruby.network.int_link_buffers02.avg_buf_msgs 0.029672 +system.ruby.network.int_link_buffers02.avg_stall_time 7.746481 +system.ruby.network.int_link_buffers08.avg_buf_msgs 0.014813 +system.ruby.network.int_link_buffers08.avg_stall_time 2.987135 +system.ruby.network.int_link_buffers09.avg_buf_msgs 0.014859 +system.ruby.network.int_link_buffers09.avg_stall_time 2.997545 +system.ruby.network.int_link_buffers13.avg_buf_msgs 0.014813 +system.ruby.network.int_link_buffers13.avg_stall_time 4.978443 +system.ruby.network.int_link_buffers14.avg_buf_msgs 0.014859 +system.ruby.network.int_link_buffers14.avg_stall_time 4.995792 +system.ruby.network.int_link_buffers17.avg_buf_msgs 0.029672 +system.ruby.network.int_link_buffers17.avg_stall_time 9.746135 +system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.014813 +system.ruby.network.routers2.port_buffers03.avg_stall_time 3.982801 +system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.014859 +system.ruby.network.routers2.port_buffers04.avg_stall_time 3.996680 +system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.029672 +system.ruby.network.routers2.port_buffers07.avg_stall_time 8.746320 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 86746 system.ruby.network.routers2.percent_links_utilized 7.418209 system.ruby.network.routers2.msg_count.Control::2 1289 system.ruby.network.routers2.msg_count.Data::2 1285 @@ -464,7 +464,7 @@ system.ruby.network.routers2.msg_bytes.Control::2 10312 system.ruby.network.routers2.msg_bytes.Data::2 92520 system.ruby.network.routers2.msg_bytes.Response_Data::4 92808 system.ruby.network.routers2.msg_bytes.Writeback_Control::3 10280 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 86746 system.ruby.network.msg_count.Control 3867 system.ruby.network.msg_count.Data 3855 system.ruby.network.msg_count.Response_Data 3867 @@ -473,7 +473,7 @@ system.ruby.network.msg_byte.Control 30936 system.ruby.network.msg_byte.Data 277560 system.ruby.network.msg_byte.Response_Data 278424 system.ruby.network.msg_byte.Writeback_Control 30840 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 86746 system.ruby.network.routers0.throttle0.link_utilization 7.427432 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1289 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1285 @@ -504,16 +504,16 @@ system.ruby.network.routers2.throttle1.msg_count.Control::2 1289 system.ruby.network.routers2.throttle1.msg_count.Data::2 1285 system.ruby.network.routers2.throttle1.msg_bytes.Control::2 10312 system.ruby.network.routers2.throttle1.msg_bytes.Data::2 92520 -system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 1289 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 1289 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 1289 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 1285 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 1285 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 1285 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_1::bucket_size 1 +system.ruby.delayVCHist.vnet_1::max_bucket 9 +system.ruby.delayVCHist.vnet_1::samples 1289 +system.ruby.delayVCHist.vnet_1 | 1289 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.delayVCHist.vnet_1::total 1289 +system.ruby.delayVCHist.vnet_2::bucket_size 1 +system.ruby.delayVCHist.vnet_2::max_bucket 9 +system.ruby.delayVCHist.vnet_2::samples 1285 +system.ruby.delayVCHist.vnet_2 | 1285 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.delayVCHist.vnet_2::total 1285 system.ruby.LD.latency_hist_seqr::bucket_size 64 system.ruby.LD.latency_hist_seqr::max_bucket 639 system.ruby.LD.latency_hist_seqr::samples 715 diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini index 467bc0996..48a2ce7b0 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -85,6 +85,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -94,14 +95,14 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -115,6 +116,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -127,15 +129,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dtb] type=SparcTLB @@ -145,14 +148,14 @@ size=64 [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -166,6 +169,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -178,15 +182,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=SparcInterrupts @@ -204,14 +209,14 @@ size=64 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -225,6 +230,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -237,15 +243,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -281,7 +288,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -290,14 +297,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/sparc/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -321,6 +329,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -332,7 +341,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -340,6 +349,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -348,6 +364,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -355,7 +372,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simerr b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simerr index aadc3d011..c0b55d123 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simerr +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout index a65457027..55314358f 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout @@ -3,11 +3,10 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:30:06 -gem5 started Jul 21 2016 14:30:36 -gem5 executing on e108600-lin, pid 38670 -command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/sparc/linux/simple-timing +gem5 compiled Apr 3 2017 18:41:19 +gem5 started Apr 3 2017 18:41:41 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 64913 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 30526500 because target called exit() +Hello World!Exiting @ tick 30915500 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index 7d03d8b84..058393673 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -1,497 +1,497 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000031 # Number of seconds simulated -sim_ticks 30915500 # Number of ticks simulated -final_tick 30915500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 536275 # Simulator instruction rate (inst/s) -host_op_rate 534981 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3098223884 # Simulator tick rate (ticks/s) -host_mem_usage 250312 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 5327 # Number of instructions simulated -sim_ops 5327 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory -system.physmem.bytes_read::total 24896 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 16320 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 16320 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory -system.physmem.num_reads::total 389 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 527890540 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 277401304 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 805291844 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 527890540 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 527890540 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 527890540 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 277401304 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 805291844 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.numSyscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 30915500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 61831 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5327 # Number of instructions committed -system.cpu.committedOps 5327 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4505 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 146 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 773 # number of instructions that are conditional controls -system.cpu.num_int_insts 4505 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 10598 # number of times the integer registers were read -system.cpu.num_int_register_writes 4845 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 1401 # number of memory refs -system.cpu.num_load_insts 723 # Number of load instructions -system.cpu.num_store_insts 678 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 61830.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1121 # Number of branches fetched -system.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction -system.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::MemRead 723 13.46% 87.37% # Class of executed instruction -system.cpu.op_class::MemWrite 678 12.63% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5370 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 81.942328 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 81.942328 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020005 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020005 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits -system.cpu.dcache.overall_hits::total 1253 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 54 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 54 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses -system.cpu.dcache.overall_misses::total 135 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3353000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3353000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5103000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5103000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 8456000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8456000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 8456000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8456000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075524 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.075524 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.120357 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.120357 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.097262 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62092.592593 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62092.592593 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62637.037037 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62637.037037 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62637.037037 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62637.037037 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3299000 # number of ReadReq MSHR miss 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Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 197.305193 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 389 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.007712 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.297024 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 81.008169 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003549 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002472 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006021 # Average percentage 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-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.285347 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.960784 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.285347 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 392 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 3 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 311 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 257 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 54 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 514 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 784 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 25088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 392 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.007653 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.087258 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 389 99.23% 99.23% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3 0.77% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 392 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 196000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 385500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 202500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 389 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 308 # Transaction distribution -system.membus.trans_dist::ReadExReq 81 # Transaction distribution -system.membus.trans_dist::ReadExResp 81 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 308 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 778 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 778 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24896 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 24896 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 389 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 389 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 389 # Request fanout histogram -system.membus.reqLayer0.occupancy 389500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1945000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.3 # Layer utilization (%) +sim_seconds 0.000031 +sim_ticks 30915500 +final_tick 30915500 +sim_freq 1000000000000 +host_inst_rate 330902 +host_op_rate 330442 +host_tick_rate 1915496347 +host_mem_usage 261572 +host_seconds 0.02 +sim_insts 5327 +sim_ops 5327 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 30915500 +system.physmem.bytes_read::cpu.inst 16320 +system.physmem.bytes_read::cpu.data 8576 +system.physmem.bytes_read::total 24896 +system.physmem.bytes_inst_read::cpu.inst 16320 +system.physmem.bytes_inst_read::total 16320 +system.physmem.num_reads::cpu.inst 255 +system.physmem.num_reads::cpu.data 134 +system.physmem.num_reads::total 389 +system.physmem.bw_read::cpu.inst 527890540 +system.physmem.bw_read::cpu.data 277401304 +system.physmem.bw_read::total 805291844 +system.physmem.bw_inst_read::cpu.inst 527890540 +system.physmem.bw_inst_read::total 527890540 +system.physmem.bw_total::cpu.inst 527890540 +system.physmem.bw_total::cpu.data 277401304 +system.physmem.bw_total::total 805291844 +system.pwrStateResidencyTicks::UNDEFINED 30915500 +system.cpu_clk_domain.clock 500 +system.cpu.workload.numSyscalls 11 +system.cpu.pwrStateResidencyTicks::ON 30915500 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+system.cpu.toL2Bus.pkt_count::total 784 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16448 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8640 +system.cpu.toL2Bus.pkt_size::total 25088 +system.cpu.toL2Bus.snoops 0 +system.cpu.toL2Bus.snoopTraffic 0 +system.cpu.toL2Bus.snoop_fanout::samples 392 +system.cpu.toL2Bus.snoop_fanout::mean 0.007653 +system.cpu.toL2Bus.snoop_fanout::stdev 0.087258 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 389 99.23% 99.23% +system.cpu.toL2Bus.snoop_fanout::1 3 0.77% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 1 +system.cpu.toL2Bus.snoop_fanout::total 392 +system.cpu.toL2Bus.reqLayer0.occupancy 196000 +system.cpu.toL2Bus.reqLayer0.utilization 0.6 +system.cpu.toL2Bus.respLayer0.occupancy 385500 +system.cpu.toL2Bus.respLayer0.utilization 1.2 +system.cpu.toL2Bus.respLayer1.occupancy 202500 +system.cpu.toL2Bus.respLayer1.utilization 0.7 +system.membus.snoop_filter.tot_requests 389 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 30915500 +system.membus.trans_dist::ReadResp 308 +system.membus.trans_dist::ReadExReq 81 +system.membus.trans_dist::ReadExResp 81 +system.membus.trans_dist::ReadSharedReq 308 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 778 +system.membus.pkt_count::total 778 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24896 +system.membus.pkt_size::total 24896 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 389 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 389 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 389 +system.membus.reqLayer0.occupancy 389500 +system.membus.reqLayer0.utilization 1.3 +system.membus.respLayer1.occupancy 1945000 +system.membus.respLayer1.utilization 6.3 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini index 5809007c6..b5dc4aa3b 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=timing @@ -65,7 +66,7 @@ SSITSize=1024 activity=0 backComSize=5 branchPred=system.cpu.branchPred -cachePorts=200 +cacheStorePorts=200 checker=Null clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 @@ -139,6 +140,7 @@ socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -764,7 +766,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -773,14 +775,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/x86/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr index bbcd9d751..707fed98b 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr @@ -1,3 +1,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout index 5ab7e4cb5..d96836b29 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 29 2016 18:55:59 -gem5 started Nov 29 2016 18:56:21 -gem5 executing on zizzer, pid 719 -command line: /z/powerjg/gem5-upstream/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/x86/linux/o3-timing +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:21 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87180 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 22466500 because target called exit() +Exiting @ tick 22516500 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index a160b1441..f96155fcc 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,995 +1,995 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000023 # Number of seconds simulated -sim_ticks 22516500 # Number of ticks simulated -final_tick 22516500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 69174 # Simulator instruction rate (inst/s) -host_op_rate 125309 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 289442861 # Simulator tick rate (ticks/s) -host_mem_usage 271352 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host -sim_insts 5380 # Number of instructions simulated -sim_ops 9747 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 17728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26688 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17728 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 277 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140 # Number of read requests responded to by this memory -system.physmem.num_reads::total 417 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 787333733 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 397930407 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1185264140 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 787333733 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 787333733 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 787333733 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 397930407 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1185264140 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 417 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 417 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26688 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26688 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 31 # Per bank write bursts -system.physmem.perBankRdBursts::1 1 # Per bank write bursts -system.physmem.perBankRdBursts::2 5 # Per bank write bursts -system.physmem.perBankRdBursts::3 8 # Per bank write bursts -system.physmem.perBankRdBursts::4 51 # Per bank write bursts -system.physmem.perBankRdBursts::5 44 # Per bank write bursts -system.physmem.perBankRdBursts::6 21 # Per bank write bursts -system.physmem.perBankRdBursts::7 36 # Per bank write bursts -system.physmem.perBankRdBursts::8 24 # Per bank write bursts -system.physmem.perBankRdBursts::9 71 # Per bank write bursts -system.physmem.perBankRdBursts::10 64 # Per bank write bursts -system.physmem.perBankRdBursts::11 16 # Per bank write bursts -system.physmem.perBankRdBursts::12 2 # Per bank write bursts -system.physmem.perBankRdBursts::13 20 # Per bank write bursts -system.physmem.perBankRdBursts::14 6 # Per bank write bursts -system.physmem.perBankRdBursts::15 17 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22387500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 417 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 242 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 128 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 37 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 98 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 239.673469 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 154.283411 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 255.721287 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 41 41.84% 41.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22 22.45% 64.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 16 16.33% 80.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7 7.14% 87.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1 1.02% 88.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 3.06% 91.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 2.04% 93.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 2.04% 95.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4 4.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 98 # Bytes accessed per row activation -system.physmem.totQLat 6651000 # Total ticks spent queuing -system.physmem.totMemAccLat 14469750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2085000 # Total ticks spent in databus transfers -system.physmem.avgQLat 15949.64 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 34699.64 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1185.26 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1185.26 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 9.26 # Data bus utilization in percentage -system.physmem.busUtilRead 9.26 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.67 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 307 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.62 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 53687.05 # Average gap between requests -system.physmem.pageHitRate 73.62 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 307020 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 140415 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1406580 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2488050 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 28320 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 7581570 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 138720 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 13319955 # Total energy per rank (pJ) -system.physmem_0.averagePower 591.537915 # Core power per rank (mW) -system.physmem_0.totalIdleTime 16888750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 17500 # Time in different power states -system.physmem_0.memoryStateTime::REF 520000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 361000 # Time in different power states -system.physmem_0.memoryStateTime::ACT 4997500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 16620500 # Time in different power states -system.physmem_1.actEnergy 478380 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 231495 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1570800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2961150 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 80160 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 7211640 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 13762905 # Total energy per rank (pJ) -system.physmem_1.averagePower 611.209282 # Core power per rank (mW) -system.physmem_1.totalIdleTime 15691750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 103000 # Time in different power states -system.physmem_1.memoryStateTime::REF 520000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 6065500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 15828000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 3542 # Number of BP lookups -system.cpu.branchPred.condPredicted 3542 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 576 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 3006 # Number of BTB lookups -system.cpu.branchPred.BTBHits 0 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 386 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 97 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 3006 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 514 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 2492 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 416 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 22516500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 45034 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12047 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16169 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3542 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 900 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 10333 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1321 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 74 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1582 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 15 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 2077 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 274 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 24737 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.175931 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.701309 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 20389 82.42% 82.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 178 0.72% 83.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 168 0.68% 83.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 246 0.99% 84.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 215 0.87% 85.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 220 0.89% 86.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 262 1.06% 87.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 167 0.68% 88.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2892 11.69% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 24737 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.078652 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.359040 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12032 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8141 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3437 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 467 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 660 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 26977 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 660 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 12302 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2135 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1085 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3589 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4966 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 25351 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 77 # Number of times rename has blocked due to IQ full -system.cpu.rename.SQFullEvents 4831 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 28444 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 61768 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 35524 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 17381 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 24 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1430 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2685 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1593 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 22118 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 18234 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 157 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 12393 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 17118 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 24737 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.737114 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.712019 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 19548 79.02% 79.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1204 4.87% 83.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 865 3.50% 87.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 579 2.34% 89.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 831 3.36% 93.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 615 2.49% 95.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 628 2.54% 98.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 340 1.37% 99.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 127 0.51% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 24737 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 218 79.85% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 40 14.65% 94.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 15 5.49% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 14605 80.10% 80.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6 0.03% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2269 12.44% 92.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1341 7.35% 99.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 4 0.02% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 18234 # Type of FU issued -system.cpu.iq.rate 0.404894 # Inst issue rate -system.cpu.iq.fu_busy_cnt 273 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014972 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 61627 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 34538 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 16576 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 18501 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 199 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1632 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 658 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 660 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1518 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 153 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 22140 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 9 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2685 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1593 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 22 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 152 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 127 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 676 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 803 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 17166 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2051 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1068 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3303 # number of memory reference insts executed -system.cpu.iew.exec_branches 1740 # Number of branches executed -system.cpu.iew.exec_stores 1252 # Number of stores executed -system.cpu.iew.exec_rate 0.381179 # Inst execution rate -system.cpu.iew.wb_sent 16892 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 16580 # cumulative count of insts written-back -system.cpu.iew.wb_producers 11141 # num instructions producing a value -system.cpu.iew.wb_consumers 17351 # num instructions consuming a value -system.cpu.iew.wb_rate 0.368166 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.642096 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 12392 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 648 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 22646 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.430407 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.314219 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 19391 85.63% 85.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1011 4.46% 90.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 560 2.47% 92.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 726 3.21% 95.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 383 1.69% 97.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 128 0.57% 98.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 118 0.52% 98.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 74 0.33% 98.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 255 1.13% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 22646 # Number of insts commited each cycle -system.cpu.commit.committedInsts 5380 # Number of instructions committed -system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 1988 # Number of memory references committed -system.cpu.commit.loads 1053 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 1208 # Number of branches committed -system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 9653 # Number of committed integer instructions. -system.cpu.commit.function_calls 106 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 1 0.01% 0.01% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 7748 79.49% 79.50% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 3 0.03% 79.53% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 7 0.07% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 1053 10.80% 90.41% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 935 9.59% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 9747 # Class of committed instruction -system.cpu.commit.bw_lim_events 255 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 44530 # The number of ROB reads -system.cpu.rob.rob_writes 46401 # The number of ROB writes -system.cpu.timesIdled 157 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 20297 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 5380 # Number of Instructions Simulated -system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 8.370632 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.370632 # CPI: Total CPI of All Threads -system.cpu.ipc 0.119465 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.119465 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 21947 # number of integer regfile reads -system.cpu.int_regfile_writes 13377 # number of integer regfile writes -system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.cc_regfile_reads 8355 # number of cc regfile reads -system.cpu.cc_regfile_writes 5130 # number of cc regfile writes -system.cpu.misc_regfile_reads 7644 # number of misc regfile reads -system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 81.908470 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2549 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 140 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 18.207143 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 81.908470 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.019997 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.019997 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 140 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.034180 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5608 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5608 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1687 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1687 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 862 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 862 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2549 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2549 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2549 # number of overall hits -system.cpu.dcache.overall_hits::total 2549 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 112 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 112 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 185 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 185 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 185 # number of overall misses -system.cpu.dcache.overall_misses::total 185 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9812000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9812000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 6772000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 6772000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16584000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16584000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16584000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16584000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1799 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1799 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2734 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2734 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2734 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2734 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.062257 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.062257 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.078075 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.078075 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.067666 # miss rate for demand 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89643.243243 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 29 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 45 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 45 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 45 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 45 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 67 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 67 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 140 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 140 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 140 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6419000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6419000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6699000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6699000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13118000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13118000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13118000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13118000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.037243 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.037243 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.078075 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.078075 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051207 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051207 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051207 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051207 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 95805.970149 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 95805.970149 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 91767.123288 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 91767.123288 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 93700 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 93700 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 93700 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 93700 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 130.523512 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1695 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 278 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.097122 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 130.523512 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.063732 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.063732 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 278 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.135742 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4432 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4432 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1695 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1695 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1695 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1695 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1695 # number of overall hits -system.cpu.icache.overall_hits::total 1695 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 382 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 382 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 382 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 382 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 382 # number of overall misses -system.cpu.icache.overall_misses::total 382 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 30098500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30098500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 30098500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30098500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 30098500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30098500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2077 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2077 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2077 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2077 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2077 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2077 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183919 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.183919 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.183919 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.183919 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.183919 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.183919 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 78791.884817 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 78791.884817 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 78791.884817 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 78791.884817 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 78791.884817 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 78791.884817 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 159 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 104 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 104 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 104 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 104 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 104 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 104 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 278 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 278 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 278 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23308500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23308500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23308500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23308500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23308500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23308500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133847 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.133847 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133847 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.133847 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133847 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.133847 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83843.525180 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83843.525180 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83843.525180 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 83843.525180 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83843.525180 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 83843.525180 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 212.529421 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 417 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.002398 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.555666 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 81.973755 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003984 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002502 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006486 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 417 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 236 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012726 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3761 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3761 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits -system.cpu.l2cache.overall_hits::total 1 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 277 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 277 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 67 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 67 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 277 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 140 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 417 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 277 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 140 # number of overall misses -system.cpu.l2cache.overall_misses::total 417 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6589500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6589500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22879500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 22879500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6317500 # number of ReadSharedReq miss cycles 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-system.cpu.l2cache.ReadCleanReq_accesses::total 278 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 67 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 67 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 278 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 140 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 418 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 278 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 140 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 418 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996403 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996403 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996403 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.997608 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996403 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.997608 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90267.123288 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90267.123288 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82597.472924 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82597.472924 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 94291.044776 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 94291.044776 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82597.472924 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92192.857143 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 85818.944844 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82597.472924 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92192.857143 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 85818.944844 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 277 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 277 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 67 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 67 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 277 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 140 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 417 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 277 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 417 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5859500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5859500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20109500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20109500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5647500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5647500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20109500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11507000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 31616500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20109500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11507000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 31616500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996403 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997608 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997608 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80267.123288 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80267.123288 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72597.472924 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72597.472924 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 84291.044776 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 84291.044776 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72597.472924 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82192.857143 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75818.944844 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72597.472924 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82192.857143 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75818.944844 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 345 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 278 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 67 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 556 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 280 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17792 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8960 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.002392 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.048912 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 417 99.76% 99.76% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1 0.24% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 417000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 210000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 417 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 344 # Transaction distribution -system.membus.trans_dist::ReadExReq 73 # Transaction distribution -system.membus.trans_dist::ReadExResp 73 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 344 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 834 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 834 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 834 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26688 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26688 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 417 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 417 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 417 # Request fanout histogram -system.membus.reqLayer0.occupancy 504000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 2226500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 9.9 # Layer utilization (%) +sim_seconds 0.000023 +sim_ticks 22516500 +final_tick 22516500 +sim_freq 1000000000000 +host_inst_rate 26720 +host_op_rate 48405 +host_tick_rate 111808950 +host_mem_usage 281880 +host_seconds 0.20 +sim_insts 5380 +sim_ops 9747 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 22516500 +system.physmem.bytes_read::cpu.inst 17728 +system.physmem.bytes_read::cpu.data 8960 +system.physmem.bytes_read::total 26688 +system.physmem.bytes_inst_read::cpu.inst 17728 +system.physmem.bytes_inst_read::total 17728 +system.physmem.num_reads::cpu.inst 277 +system.physmem.num_reads::cpu.data 140 +system.physmem.num_reads::total 417 +system.physmem.bw_read::cpu.inst 787333733 +system.physmem.bw_read::cpu.data 397930407 +system.physmem.bw_read::total 1185264140 +system.physmem.bw_inst_read::cpu.inst 787333733 +system.physmem.bw_inst_read::total 787333733 +system.physmem.bw_total::cpu.inst 787333733 +system.physmem.bw_total::cpu.data 397930407 +system.physmem.bw_total::total 1185264140 +system.physmem.readReqs 417 +system.physmem.writeReqs 0 +system.physmem.readBursts 417 +system.physmem.writeBursts 0 +system.physmem.bytesReadDRAM 26688 +system.physmem.bytesReadWrQ 0 +system.physmem.bytesWritten 0 +system.physmem.bytesReadSys 26688 +system.physmem.bytesWrittenSys 0 +system.physmem.servicedByWrQ 0 +system.physmem.mergedWrBursts 0 +system.physmem.neitherReadNorWriteReqs 0 +system.physmem.perBankRdBursts::0 31 +system.physmem.perBankRdBursts::1 1 +system.physmem.perBankRdBursts::2 5 +system.physmem.perBankRdBursts::3 8 +system.physmem.perBankRdBursts::4 51 +system.physmem.perBankRdBursts::5 44 +system.physmem.perBankRdBursts::6 21 +system.physmem.perBankRdBursts::7 36 +system.physmem.perBankRdBursts::8 24 +system.physmem.perBankRdBursts::9 71 +system.physmem.perBankRdBursts::10 64 +system.physmem.perBankRdBursts::11 16 +system.physmem.perBankRdBursts::12 2 +system.physmem.perBankRdBursts::13 20 +system.physmem.perBankRdBursts::14 6 +system.physmem.perBankRdBursts::15 17 +system.physmem.perBankWrBursts::0 0 +system.physmem.perBankWrBursts::1 0 +system.physmem.perBankWrBursts::2 0 +system.physmem.perBankWrBursts::3 0 +system.physmem.perBankWrBursts::4 0 +system.physmem.perBankWrBursts::5 0 +system.physmem.perBankWrBursts::6 0 +system.physmem.perBankWrBursts::7 0 +system.physmem.perBankWrBursts::8 0 +system.physmem.perBankWrBursts::9 0 +system.physmem.perBankWrBursts::10 0 +system.physmem.perBankWrBursts::11 0 +system.physmem.perBankWrBursts::12 0 +system.physmem.perBankWrBursts::13 0 +system.physmem.perBankWrBursts::14 0 +system.physmem.perBankWrBursts::15 0 +system.physmem.numRdRetry 0 +system.physmem.numWrRetry 0 +system.physmem.totGap 22387500 +system.physmem.readPktSize::0 0 +system.physmem.readPktSize::1 0 +system.physmem.readPktSize::2 0 +system.physmem.readPktSize::3 0 +system.physmem.readPktSize::4 0 +system.physmem.readPktSize::5 0 +system.physmem.readPktSize::6 417 +system.physmem.writePktSize::0 0 +system.physmem.writePktSize::1 0 +system.physmem.writePktSize::2 0 +system.physmem.writePktSize::3 0 +system.physmem.writePktSize::4 0 +system.physmem.writePktSize::5 0 +system.physmem.writePktSize::6 0 +system.physmem.rdQLenPdf::0 242 +system.physmem.rdQLenPdf::1 128 +system.physmem.rdQLenPdf::2 37 +system.physmem.rdQLenPdf::3 9 +system.physmem.rdQLenPdf::4 1 +system.physmem.rdQLenPdf::5 0 +system.physmem.rdQLenPdf::6 0 +system.physmem.rdQLenPdf::7 0 +system.physmem.rdQLenPdf::8 0 +system.physmem.rdQLenPdf::9 0 +system.physmem.rdQLenPdf::10 0 +system.physmem.rdQLenPdf::11 0 +system.physmem.rdQLenPdf::12 0 +system.physmem.rdQLenPdf::13 0 +system.physmem.rdQLenPdf::14 0 +system.physmem.rdQLenPdf::15 0 +system.physmem.rdQLenPdf::16 0 +system.physmem.rdQLenPdf::17 0 +system.physmem.rdQLenPdf::18 0 +system.physmem.rdQLenPdf::19 0 +system.physmem.rdQLenPdf::20 0 +system.physmem.rdQLenPdf::21 0 +system.physmem.rdQLenPdf::22 0 +system.physmem.rdQLenPdf::23 0 +system.physmem.rdQLenPdf::24 0 +system.physmem.rdQLenPdf::25 0 +system.physmem.rdQLenPdf::26 0 +system.physmem.rdQLenPdf::27 0 +system.physmem.rdQLenPdf::28 0 +system.physmem.rdQLenPdf::29 0 +system.physmem.rdQLenPdf::30 0 +system.physmem.rdQLenPdf::31 0 +system.physmem.wrQLenPdf::0 0 +system.physmem.wrQLenPdf::1 0 +system.physmem.wrQLenPdf::2 0 +system.physmem.wrQLenPdf::3 0 +system.physmem.wrQLenPdf::4 0 +system.physmem.wrQLenPdf::5 0 +system.physmem.wrQLenPdf::6 0 +system.physmem.wrQLenPdf::7 0 +system.physmem.wrQLenPdf::8 0 +system.physmem.wrQLenPdf::9 0 +system.physmem.wrQLenPdf::10 0 +system.physmem.wrQLenPdf::11 0 +system.physmem.wrQLenPdf::12 0 +system.physmem.wrQLenPdf::13 0 +system.physmem.wrQLenPdf::14 0 +system.physmem.wrQLenPdf::15 0 +system.physmem.wrQLenPdf::16 0 +system.physmem.wrQLenPdf::17 0 +system.physmem.wrQLenPdf::18 0 +system.physmem.wrQLenPdf::19 0 +system.physmem.wrQLenPdf::20 0 +system.physmem.wrQLenPdf::21 0 +system.physmem.wrQLenPdf::22 0 +system.physmem.wrQLenPdf::23 0 +system.physmem.wrQLenPdf::24 0 +system.physmem.wrQLenPdf::25 0 +system.physmem.wrQLenPdf::26 0 +system.physmem.wrQLenPdf::27 0 +system.physmem.wrQLenPdf::28 0 +system.physmem.wrQLenPdf::29 0 +system.physmem.wrQLenPdf::30 0 +system.physmem.wrQLenPdf::31 0 +system.physmem.wrQLenPdf::32 0 +system.physmem.wrQLenPdf::33 0 +system.physmem.wrQLenPdf::34 0 +system.physmem.wrQLenPdf::35 0 +system.physmem.wrQLenPdf::36 0 +system.physmem.wrQLenPdf::37 0 +system.physmem.wrQLenPdf::38 0 +system.physmem.wrQLenPdf::39 0 +system.physmem.wrQLenPdf::40 0 +system.physmem.wrQLenPdf::41 0 +system.physmem.wrQLenPdf::42 0 +system.physmem.wrQLenPdf::43 0 +system.physmem.wrQLenPdf::44 0 +system.physmem.wrQLenPdf::45 0 +system.physmem.wrQLenPdf::46 0 +system.physmem.wrQLenPdf::47 0 +system.physmem.wrQLenPdf::48 0 +system.physmem.wrQLenPdf::49 0 +system.physmem.wrQLenPdf::50 0 +system.physmem.wrQLenPdf::51 0 +system.physmem.wrQLenPdf::52 0 +system.physmem.wrQLenPdf::53 0 +system.physmem.wrQLenPdf::54 0 +system.physmem.wrQLenPdf::55 0 +system.physmem.wrQLenPdf::56 0 +system.physmem.wrQLenPdf::57 0 +system.physmem.wrQLenPdf::58 0 +system.physmem.wrQLenPdf::59 0 +system.physmem.wrQLenPdf::60 0 +system.physmem.wrQLenPdf::61 0 +system.physmem.wrQLenPdf::62 0 +system.physmem.wrQLenPdf::63 0 +system.physmem.bytesPerActivate::samples 98 +system.physmem.bytesPerActivate::mean 239.673469 +system.physmem.bytesPerActivate::gmean 154.283411 +system.physmem.bytesPerActivate::stdev 255.721287 +system.physmem.bytesPerActivate::0-127 41 41.84% 41.84% +system.physmem.bytesPerActivate::128-255 22 22.45% 64.29% +system.physmem.bytesPerActivate::256-383 16 16.33% 80.61% +system.physmem.bytesPerActivate::384-511 7 7.14% 87.76% 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+system.membus.trans_dist::ReadExResp 73 +system.membus.trans_dist::ReadSharedReq 344 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 834 +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 834 +system.membus.pkt_count::total 834 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26688 +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26688 +system.membus.pkt_size::total 26688 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 417 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 417 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 417 +system.membus.reqLayer0.occupancy 504000 +system.membus.reqLayer0.utilization 2.2 +system.membus.respLayer1.occupancy 2226500 +system.membus.respLayer1.utilization 9.9 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini index 62043a3c5..8968a4ed6 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=atomic @@ -88,6 +89,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -167,7 +169,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -176,14 +178,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/x86/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/x86/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -207,6 +210,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -218,7 +222,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -226,6 +230,13 @@ width=16 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -234,6 +245,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -241,7 +253,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr index aadc3d011..c0b55d123 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout index bd2d6df6a..8dcc9cbbd 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-ato gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:35:23 -gem5 started Jul 21 2016 14:36:19 -gem5 executing on e108600-lin, pid 18561 -command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/x86/linux/simple-atomic +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:21 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87156 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 5615000 because target called exit() +Exiting @ tick 5615000 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt index 54ef40828..2360c7c26 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -1,145 +1,145 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000006 # Number of seconds simulated -sim_ticks 5615000 # Number of ticks simulated -final_tick 5615000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 340881 # Simulator instruction rate (inst/s) -host_op_rate 616836 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 354943212 # Simulator tick rate (ticks/s) -host_mem_usage 258192 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -sim_insts 5381 # Number of instructions simulated -sim_ops 9748 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 5615000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 54912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7066 # Number of bytes read from this memory -system.physmem.bytes_read::total 61978 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 54912 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 54912 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 7112 # Number of bytes written to this memory -system.physmem.bytes_written::total 7112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 6864 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1053 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7917 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 935 # Number of write requests responded to by this memory -system.physmem.num_writes::total 935 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 9779519145 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1258414960 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 11037934105 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 9779519145 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 9779519145 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1266607302 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1266607302 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 9779519145 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2525022262 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 12304541407 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 5615000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 5615000 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 5615000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 5615000 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 5615000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 11231 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5381 # Number of instructions committed -system.cpu.committedOps 9748 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 209 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls -system.cpu.num_int_insts 9654 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 18335 # number of times the integer registers were read -system.cpu.num_int_register_writes 7527 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 6487 # number of times the CC registers were read -system.cpu.num_cc_register_writes 3536 # number of times the CC registers were written -system.cpu.num_mem_refs 1988 # number of memory refs -system.cpu.num_load_insts 1053 # Number of load instructions -system.cpu.num_store_insts 935 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 11230.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1208 # Number of branches fetched -system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction -system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction -system.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction -system.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction -system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 9748 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 5615000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 7917 # Transaction distribution -system.membus.trans_dist::ReadResp 7917 # Transaction distribution -system.membus.trans_dist::WriteReq 935 # Transaction distribution -system.membus.trans_dist::WriteResp 935 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 13728 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.icache_port::total 13728 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3976 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::total 3976 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 17704 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 54912 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::total 54912 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 14178 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::total 14178 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 69090 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 8852 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 8852 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 8852 # Request fanout histogram +sim_seconds 0.000006 +sim_ticks 5615000 +final_tick 5615000 +sim_freq 1000000000000 +host_inst_rate 289662 +host_op_rate 524226 +host_tick_rate 301675446 +host_mem_usage 269844 +host_seconds 0.02 +sim_insts 5381 +sim_ops 9748 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 5615000 +system.physmem.bytes_read::cpu.inst 54912 +system.physmem.bytes_read::cpu.data 7066 +system.physmem.bytes_read::total 61978 +system.physmem.bytes_inst_read::cpu.inst 54912 +system.physmem.bytes_inst_read::total 54912 +system.physmem.bytes_written::cpu.data 7112 +system.physmem.bytes_written::total 7112 +system.physmem.num_reads::cpu.inst 6864 +system.physmem.num_reads::cpu.data 1053 +system.physmem.num_reads::total 7917 +system.physmem.num_writes::cpu.data 935 +system.physmem.num_writes::total 935 +system.physmem.bw_read::cpu.inst 9779519145 +system.physmem.bw_read::cpu.data 1258414960 +system.physmem.bw_read::total 11037934105 +system.physmem.bw_inst_read::cpu.inst 9779519145 +system.physmem.bw_inst_read::total 9779519145 +system.physmem.bw_write::cpu.data 1266607302 +system.physmem.bw_write::total 1266607302 +system.physmem.bw_total::cpu.inst 9779519145 +system.physmem.bw_total::cpu.data 2525022262 +system.physmem.bw_total::total 12304541407 +system.pwrStateResidencyTicks::UNDEFINED 5615000 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 5615000 +system.cpu.apic_clk_domain.clock 8000 +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 5615000 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 5615000 +system.cpu.workload.numSyscalls 11 +system.cpu.pwrStateResidencyTicks::ON 5615000 +system.cpu.numCycles 11231 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 5381 +system.cpu.committedOps 9748 +system.cpu.num_int_alu_accesses 9654 +system.cpu.num_fp_alu_accesses 0 +system.cpu.num_func_calls 209 +system.cpu.num_conditional_control_insts 899 +system.cpu.num_int_insts 9654 +system.cpu.num_fp_insts 0 +system.cpu.num_int_register_reads 18335 +system.cpu.num_int_register_writes 7527 +system.cpu.num_fp_register_reads 0 +system.cpu.num_fp_register_writes 0 +system.cpu.num_cc_register_reads 6487 +system.cpu.num_cc_register_writes 3536 +system.cpu.num_mem_refs 1988 +system.cpu.num_load_insts 1053 +system.cpu.num_store_insts 935 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 11231 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 1208 +system.cpu.op_class::No_OpClass 1 0.01% 0.01% +system.cpu.op_class::IntAlu 7749 79.49% 79.50% +system.cpu.op_class::IntMult 3 0.03% 79.53% +system.cpu.op_class::IntDiv 7 0.07% 79.61% +system.cpu.op_class::FloatAdd 0 0.00% 79.61% +system.cpu.op_class::FloatCmp 0 0.00% 79.61% +system.cpu.op_class::FloatCvt 0 0.00% 79.61% +system.cpu.op_class::FloatMult 0 0.00% 79.61% +system.cpu.op_class::FloatMultAcc 0 0.00% 79.61% +system.cpu.op_class::FloatDiv 0 0.00% 79.61% +system.cpu.op_class::FloatMisc 0 0.00% 79.61% +system.cpu.op_class::FloatSqrt 0 0.00% 79.61% +system.cpu.op_class::SimdAdd 0 0.00% 79.61% +system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% +system.cpu.op_class::SimdAlu 0 0.00% 79.61% +system.cpu.op_class::SimdCmp 0 0.00% 79.61% +system.cpu.op_class::SimdCvt 0 0.00% 79.61% +system.cpu.op_class::SimdMisc 0 0.00% 79.61% +system.cpu.op_class::SimdMult 0 0.00% 79.61% +system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% +system.cpu.op_class::SimdShift 0 0.00% 79.61% +system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% +system.cpu.op_class::SimdSqrt 0 0.00% 79.61% +system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% +system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% +system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% +system.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% +system.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% +system.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% +system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% +system.cpu.op_class::MemRead 1053 10.80% 90.41% +system.cpu.op_class::MemWrite 935 9.59% 100.00% +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 9748 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 5615000 +system.membus.trans_dist::ReadReq 7917 +system.membus.trans_dist::ReadResp 7917 +system.membus.trans_dist::WriteReq 935 +system.membus.trans_dist::WriteResp 935 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 13728 +system.membus.pkt_count_system.cpu.icache_port::total 13728 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3976 +system.membus.pkt_count_system.cpu.dcache_port::total 3976 +system.membus.pkt_count::total 17704 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 54912 +system.membus.pkt_size_system.cpu.icache_port::total 54912 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 14178 +system.membus.pkt_size_system.cpu.dcache_port::total 14178 +system.membus.pkt_size::total 69090 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 8852 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 8852 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 8852 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini index 49adea038..155aa9c1d 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=timing @@ -85,6 +86,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -171,7 +173,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -180,14 +182,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/x86/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/x86/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -346,6 +349,7 @@ type=RubyDirectoryMemory eventq_index=0 numa_high_bit=5 size=268435456 +system=system version=0 [system.ruby.dir_cntrl0.dmaRequestToDir] diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr index f6f6f15a5..95500d55b 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr @@ -7,4 +7,5 @@ warn: rounding error > tolerance warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout index 60c5b94b3..18eac1046 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 21:09:01 -gem5 executing on e108600-lin, pid 17636 -command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/x86/linux/simple-timing-ruby +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:22 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87199 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/x86/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 91859 because target called exit() +Exiting @ tick 91859 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index 843ed7643..f79527e54 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -1,369 +1,369 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000092 # Number of seconds simulated -sim_ticks 91859 # Number of ticks simulated -final_tick 91859 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 94122 # Simulator instruction rate (inst/s) -host_op_rate 170479 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1606243 # Simulator tick rate (ticks/s) -host_mem_usage 432368 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -sim_insts 5381 # Number of instructions simulated -sim_ops 9748 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 88128 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 88128 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 87872 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 87872 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 1377 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 1377 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 1373 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 1373 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 959383403 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 959383403 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 956596523 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 956596523 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1915979926 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1915979926 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 1377 # Number of read requests accepted -system.mem_ctrls.writeReqs 1373 # Number of write requests accepted -system.mem_ctrls.readBursts 1377 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 1373 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 41408 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 46720 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 41728 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 88128 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 87872 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 730 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 702 # Number of DRAM write bursts merged with an existing one -system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 60 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 2 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 6 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 10 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 51 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 53 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 39 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 57 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 28 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 129 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 115 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 24 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 2 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 28 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 8 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 35 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 55 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 2 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 6 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 8 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 52 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 48 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 38 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 60 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 28 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 130 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 123 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 24 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 2 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 31 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 8 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 37 # Per bank write bursts -system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 91773 # Total gap between requests -system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 1377 # Read request sizes (log2) -system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::5 0 # 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length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 263 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 304.669202 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 201.653389 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 284.735596 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 72 27.38% 27.38% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 68 25.86% 53.23% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 44 16.73% 69.96% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 29 11.03% 80.99% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 12 4.56% 85.55% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 9 3.42% 88.97% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 6 2.28% 91.25% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 3 1.14% 92.40% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 20 7.60% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 263 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 40 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 16.100000 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 15.846587 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 3.484765 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-13 3 7.50% 7.50% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 12 30.00% 37.50% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 19 47.50% 85.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 4 10.00% 95.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::20-21 1 2.50% 97.50% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::34-35 1 2.50% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 40 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 40 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.300000 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.281263 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.822753 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 35 87.50% 87.50% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 3 7.50% 95.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 2 5.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 40 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 12721 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 25014 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3235 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 19.66 # Average queueing delay per DRAM burst -system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 38.66 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 450.78 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 454.26 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 959.38 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 956.60 # Average system write bandwidth in MiByte/s -system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 7.07 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 3.52 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 3.55 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 25.84 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 435 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 591 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 67.23 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 88.08 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 33.37 # Average gap between requests -system.mem_ctrls.pageHitRate 77.85 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 664020 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 340032 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 3175872 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 2246688 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 7375680.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 10273224 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 269568 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.actPowerDownEnergy 25208136 # Energy for active power-down per rank (pJ) -system.mem_ctrls_0.prePowerDownEnergy 4818816 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_0.selfRefreshEnergy 743760.000000 # Energy for self refresh per rank (pJ) -system.mem_ctrls_0.totalEnergy 55115796 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 600.004311 # Core power per rank (mW) -system.mem_ctrls_0.totalIdleTime 68393 # Total Idle time Per DRAM Rank -system.mem_ctrls_0.memoryStateTime::IDLE 346 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 3126 # Time in different power states -system.mem_ctrls_0.memoryStateTime::SREF 798 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 12549 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 19759 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 55281 # Time in different power states -system.mem_ctrls_1.actEnergy 1285200 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 676200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 4215456 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 3198816 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 6761040.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 9576912 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 183552 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.actPowerDownEnergy 28147512 # Energy for active power-down per rank (pJ) -system.mem_ctrls_1.prePowerDownEnergy 3322368 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrls_1.totalEnergy 57367056 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 624.512089 # Core power per rank (mW) -system.mem_ctrls_1.totalIdleTime 70328 # Total Idle time Per DRAM Rank -system.mem_ctrls_1.memoryStateTime::IDLE 150 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 2866 # Time in different power states -system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 8652 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 18464 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 61727 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states -system.cpu.clk_domain.clock 1 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 16 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 91859 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 91859 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5381 # Number of instructions committed -system.cpu.committedOps 9748 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 209 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls -system.cpu.num_int_insts 9654 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 18335 # number of times the integer registers were read -system.cpu.num_int_register_writes 7527 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 6487 # number of times the CC registers were read -system.cpu.num_cc_register_writes 3536 # number of times the CC registers were written -system.cpu.num_mem_refs 1988 # number of memory refs -system.cpu.num_load_insts 1053 # Number of load instructions -system.cpu.num_store_insts 935 # Number of store instructions -system.cpu.num_idle_cycles 0.999989 # Number of idle cycles -system.cpu.num_busy_cycles 91858.000011 # Number of busy cycles -system.cpu.not_idle_fraction 0.999989 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000011 # Percentage of idle cycles -system.cpu.Branches 1208 # Number of branches fetched -system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction -system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction -system.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction -system.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction -system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 9748 # Class of executed instruction -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states -system.ruby.delayHist::bucket_size 1 # delay histogram for all message -system.ruby.delayHist::max_bucket 9 # delay histogram for all message -system.ruby.delayHist::samples 2750 # delay histogram for all message -system.ruby.delayHist | 2750 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 2750 # delay histogram for all message +sim_seconds 0.000092 +sim_ticks 91859 +final_tick 91859 +sim_freq 1000000000 +host_inst_rate 44912 +host_op_rate 81347 +host_tick_rate 766447 +host_mem_usage 444688 +host_seconds 0.12 +sim_insts 5381 +sim_ops 9748 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1 +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 91859 +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 88128 +system.mem_ctrls.bytes_read::total 88128 +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 87872 +system.mem_ctrls.bytes_written::total 87872 +system.mem_ctrls.num_reads::ruby.dir_cntrl0 1377 +system.mem_ctrls.num_reads::total 1377 +system.mem_ctrls.num_writes::ruby.dir_cntrl0 1373 +system.mem_ctrls.num_writes::total 1373 +system.mem_ctrls.bw_read::ruby.dir_cntrl0 959383403 +system.mem_ctrls.bw_read::total 959383403 +system.mem_ctrls.bw_write::ruby.dir_cntrl0 956596523 +system.mem_ctrls.bw_write::total 956596523 +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1915979926 +system.mem_ctrls.bw_total::total 1915979926 +system.mem_ctrls.readReqs 1377 +system.mem_ctrls.writeReqs 1373 +system.mem_ctrls.readBursts 1377 +system.mem_ctrls.writeBursts 1373 +system.mem_ctrls.bytesReadDRAM 41408 +system.mem_ctrls.bytesReadWrQ 46720 +system.mem_ctrls.bytesWritten 41728 +system.mem_ctrls.bytesReadSys 88128 +system.mem_ctrls.bytesWrittenSys 87872 +system.mem_ctrls.servicedByWrQ 730 +system.mem_ctrls.mergedWrBursts 702 +system.mem_ctrls.neitherReadNorWriteReqs 0 +system.mem_ctrls.perBankRdBursts::0 60 +system.mem_ctrls.perBankRdBursts::1 2 +system.mem_ctrls.perBankRdBursts::2 6 +system.mem_ctrls.perBankRdBursts::3 10 +system.mem_ctrls.perBankRdBursts::4 51 +system.mem_ctrls.perBankRdBursts::5 53 +system.mem_ctrls.perBankRdBursts::6 39 +system.mem_ctrls.perBankRdBursts::7 57 +system.mem_ctrls.perBankRdBursts::8 28 +system.mem_ctrls.perBankRdBursts::9 129 +system.mem_ctrls.perBankRdBursts::10 115 +system.mem_ctrls.perBankRdBursts::11 24 +system.mem_ctrls.perBankRdBursts::12 2 +system.mem_ctrls.perBankRdBursts::13 28 +system.mem_ctrls.perBankRdBursts::14 8 +system.mem_ctrls.perBankRdBursts::15 35 +system.mem_ctrls.perBankWrBursts::0 55 +system.mem_ctrls.perBankWrBursts::1 2 +system.mem_ctrls.perBankWrBursts::2 6 +system.mem_ctrls.perBankWrBursts::3 8 +system.mem_ctrls.perBankWrBursts::4 52 +system.mem_ctrls.perBankWrBursts::5 48 +system.mem_ctrls.perBankWrBursts::6 38 +system.mem_ctrls.perBankWrBursts::7 60 +system.mem_ctrls.perBankWrBursts::8 28 +system.mem_ctrls.perBankWrBursts::9 130 +system.mem_ctrls.perBankWrBursts::10 123 +system.mem_ctrls.perBankWrBursts::11 24 +system.mem_ctrls.perBankWrBursts::12 2 +system.mem_ctrls.perBankWrBursts::13 31 +system.mem_ctrls.perBankWrBursts::14 8 +system.mem_ctrls.perBankWrBursts::15 37 +system.mem_ctrls.numRdRetry 0 +system.mem_ctrls.numWrRetry 0 +system.mem_ctrls.totGap 91773 +system.mem_ctrls.readPktSize::0 0 +system.mem_ctrls.readPktSize::1 0 +system.mem_ctrls.readPktSize::2 0 +system.mem_ctrls.readPktSize::3 0 +system.mem_ctrls.readPktSize::4 0 +system.mem_ctrls.readPktSize::5 0 +system.mem_ctrls.readPktSize::6 1377 +system.mem_ctrls.writePktSize::0 0 +system.mem_ctrls.writePktSize::1 0 +system.mem_ctrls.writePktSize::2 0 +system.mem_ctrls.writePktSize::3 0 +system.mem_ctrls.writePktSize::4 0 +system.mem_ctrls.writePktSize::5 0 +system.mem_ctrls.writePktSize::6 1373 +system.mem_ctrls.rdQLenPdf::0 647 +system.mem_ctrls.rdQLenPdf::1 0 +system.mem_ctrls.rdQLenPdf::2 0 +system.mem_ctrls.rdQLenPdf::3 0 +system.mem_ctrls.rdQLenPdf::4 0 +system.mem_ctrls.rdQLenPdf::5 0 +system.mem_ctrls.rdQLenPdf::6 0 +system.mem_ctrls.rdQLenPdf::7 0 +system.mem_ctrls.rdQLenPdf::8 0 +system.mem_ctrls.rdQLenPdf::9 0 +system.mem_ctrls.rdQLenPdf::10 0 +system.mem_ctrls.rdQLenPdf::11 0 +system.mem_ctrls.rdQLenPdf::12 0 +system.mem_ctrls.rdQLenPdf::13 0 +system.mem_ctrls.rdQLenPdf::14 0 +system.mem_ctrls.rdQLenPdf::15 0 +system.mem_ctrls.rdQLenPdf::16 0 +system.mem_ctrls.rdQLenPdf::17 0 +system.mem_ctrls.rdQLenPdf::18 0 +system.mem_ctrls.rdQLenPdf::19 0 +system.mem_ctrls.rdQLenPdf::20 0 +system.mem_ctrls.rdQLenPdf::21 0 +system.mem_ctrls.rdQLenPdf::22 0 +system.mem_ctrls.rdQLenPdf::23 0 +system.mem_ctrls.rdQLenPdf::24 0 +system.mem_ctrls.rdQLenPdf::25 0 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+system.mem_ctrls.wrQLenPdf::23 40 +system.mem_ctrls.wrQLenPdf::24 40 +system.mem_ctrls.wrQLenPdf::25 40 +system.mem_ctrls.wrQLenPdf::26 40 +system.mem_ctrls.wrQLenPdf::27 40 +system.mem_ctrls.wrQLenPdf::28 40 +system.mem_ctrls.wrQLenPdf::29 40 +system.mem_ctrls.wrQLenPdf::30 40 +system.mem_ctrls.wrQLenPdf::31 40 +system.mem_ctrls.wrQLenPdf::32 40 +system.mem_ctrls.wrQLenPdf::33 0 +system.mem_ctrls.wrQLenPdf::34 0 +system.mem_ctrls.wrQLenPdf::35 0 +system.mem_ctrls.wrQLenPdf::36 0 +system.mem_ctrls.wrQLenPdf::37 0 +system.mem_ctrls.wrQLenPdf::38 0 +system.mem_ctrls.wrQLenPdf::39 0 +system.mem_ctrls.wrQLenPdf::40 0 +system.mem_ctrls.wrQLenPdf::41 0 +system.mem_ctrls.wrQLenPdf::42 0 +system.mem_ctrls.wrQLenPdf::43 0 +system.mem_ctrls.wrQLenPdf::44 0 +system.mem_ctrls.wrQLenPdf::45 0 +system.mem_ctrls.wrQLenPdf::46 0 +system.mem_ctrls.wrQLenPdf::47 0 +system.mem_ctrls.wrQLenPdf::48 0 +system.mem_ctrls.wrQLenPdf::49 0 +system.mem_ctrls.wrQLenPdf::50 0 +system.mem_ctrls.wrQLenPdf::51 0 +system.mem_ctrls.wrQLenPdf::52 0 +system.mem_ctrls.wrQLenPdf::53 0 +system.mem_ctrls.wrQLenPdf::54 0 +system.mem_ctrls.wrQLenPdf::55 0 +system.mem_ctrls.wrQLenPdf::56 0 +system.mem_ctrls.wrQLenPdf::57 0 +system.mem_ctrls.wrQLenPdf::58 0 +system.mem_ctrls.wrQLenPdf::59 0 +system.mem_ctrls.wrQLenPdf::60 0 +system.mem_ctrls.wrQLenPdf::61 0 +system.mem_ctrls.wrQLenPdf::62 0 +system.mem_ctrls.wrQLenPdf::63 0 +system.mem_ctrls.bytesPerActivate::samples 263 +system.mem_ctrls.bytesPerActivate::mean 304.669202 +system.mem_ctrls.bytesPerActivate::gmean 201.653389 +system.mem_ctrls.bytesPerActivate::stdev 284.735596 +system.mem_ctrls.bytesPerActivate::0-127 72 27.38% 27.38% +system.mem_ctrls.bytesPerActivate::128-255 68 25.86% 53.23% +system.mem_ctrls.bytesPerActivate::256-383 44 16.73% 69.96% +system.mem_ctrls.bytesPerActivate::384-511 29 11.03% 80.99% +system.mem_ctrls.bytesPerActivate::512-639 12 4.56% 85.55% +system.mem_ctrls.bytesPerActivate::640-767 9 3.42% 88.97% +system.mem_ctrls.bytesPerActivate::768-895 6 2.28% 91.25% +system.mem_ctrls.bytesPerActivate::896-1023 3 1.14% 92.40% +system.mem_ctrls.bytesPerActivate::1024-1151 20 7.60% 100.00% +system.mem_ctrls.bytesPerActivate::total 263 +system.mem_ctrls.rdPerTurnAround::samples 40 +system.mem_ctrls.rdPerTurnAround::mean 16.100000 +system.mem_ctrls.rdPerTurnAround::gmean 15.846587 +system.mem_ctrls.rdPerTurnAround::stdev 3.484765 +system.mem_ctrls.rdPerTurnAround::12-13 3 7.50% 7.50% +system.mem_ctrls.rdPerTurnAround::14-15 12 30.00% 37.50% +system.mem_ctrls.rdPerTurnAround::16-17 19 47.50% 85.00% +system.mem_ctrls.rdPerTurnAround::18-19 4 10.00% 95.00% +system.mem_ctrls.rdPerTurnAround::20-21 1 2.50% 97.50% +system.mem_ctrls.rdPerTurnAround::34-35 1 2.50% 100.00% +system.mem_ctrls.rdPerTurnAround::total 40 +system.mem_ctrls.wrPerTurnAround::samples 40 +system.mem_ctrls.wrPerTurnAround::mean 16.300000 +system.mem_ctrls.wrPerTurnAround::gmean 16.281263 +system.mem_ctrls.wrPerTurnAround::stdev 0.822753 +system.mem_ctrls.wrPerTurnAround::16 35 87.50% 87.50% +system.mem_ctrls.wrPerTurnAround::18 3 7.50% 95.00% +system.mem_ctrls.wrPerTurnAround::19 2 5.00% 100.00% +system.mem_ctrls.wrPerTurnAround::total 40 +system.mem_ctrls.totQLat 12721 +system.mem_ctrls.totMemAccLat 25014 +system.mem_ctrls.totBusLat 3235 +system.mem_ctrls.avgQLat 19.66 +system.mem_ctrls.avgBusLat 5.00 +system.mem_ctrls.avgMemAccLat 38.66 +system.mem_ctrls.avgRdBW 450.78 +system.mem_ctrls.avgWrBW 454.26 +system.mem_ctrls.avgRdBWSys 959.38 +system.mem_ctrls.avgWrBWSys 956.60 +system.mem_ctrls.peakBW 12800.00 +system.mem_ctrls.busUtil 7.07 +system.mem_ctrls.busUtilRead 3.52 +system.mem_ctrls.busUtilWrite 3.55 +system.mem_ctrls.avgRdQLen 1.00 +system.mem_ctrls.avgWrQLen 25.84 +system.mem_ctrls.readRowHits 435 +system.mem_ctrls.writeRowHits 591 +system.mem_ctrls.readRowHitRate 67.23 +system.mem_ctrls.writeRowHitRate 88.08 +system.mem_ctrls.avgGap 33.37 +system.mem_ctrls.pageHitRate 77.85 +system.mem_ctrls_0.actEnergy 664020 +system.mem_ctrls_0.preEnergy 340032 +system.mem_ctrls_0.readEnergy 3175872 +system.mem_ctrls_0.writeEnergy 2246688 +system.mem_ctrls_0.refreshEnergy 7375680.000000 +system.mem_ctrls_0.actBackEnergy 10273224 +system.mem_ctrls_0.preBackEnergy 269568 +system.mem_ctrls_0.actPowerDownEnergy 25208136 +system.mem_ctrls_0.prePowerDownEnergy 4818816 +system.mem_ctrls_0.selfRefreshEnergy 743760.000000 +system.mem_ctrls_0.totalEnergy 55115796 +system.mem_ctrls_0.averagePower 600.004311 +system.mem_ctrls_0.totalIdleTime 68393 +system.mem_ctrls_0.memoryStateTime::IDLE 346 +system.mem_ctrls_0.memoryStateTime::REF 3126 +system.mem_ctrls_0.memoryStateTime::SREF 798 +system.mem_ctrls_0.memoryStateTime::PRE_PDN 12549 +system.mem_ctrls_0.memoryStateTime::ACT 19759 +system.mem_ctrls_0.memoryStateTime::ACT_PDN 55281 +system.mem_ctrls_1.actEnergy 1285200 +system.mem_ctrls_1.preEnergy 676200 +system.mem_ctrls_1.readEnergy 4215456 +system.mem_ctrls_1.writeEnergy 3198816 +system.mem_ctrls_1.refreshEnergy 6761040.000000 +system.mem_ctrls_1.actBackEnergy 9576912 +system.mem_ctrls_1.preBackEnergy 183552 +system.mem_ctrls_1.actPowerDownEnergy 28147512 +system.mem_ctrls_1.prePowerDownEnergy 3322368 +system.mem_ctrls_1.selfRefreshEnergy 0 +system.mem_ctrls_1.totalEnergy 57367056 +system.mem_ctrls_1.averagePower 624.512089 +system.mem_ctrls_1.totalIdleTime 70328 +system.mem_ctrls_1.memoryStateTime::IDLE 150 +system.mem_ctrls_1.memoryStateTime::REF 2866 +system.mem_ctrls_1.memoryStateTime::SREF 0 +system.mem_ctrls_1.memoryStateTime::PRE_PDN 8652 +system.mem_ctrls_1.memoryStateTime::ACT 18464 +system.mem_ctrls_1.memoryStateTime::ACT_PDN 61727 +system.pwrStateResidencyTicks::UNDEFINED 91859 +system.cpu.clk_domain.clock 1 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 91859 +system.cpu.apic_clk_domain.clock 16 +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 91859 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 91859 +system.cpu.workload.numSyscalls 11 +system.cpu.pwrStateResidencyTicks::ON 91859 +system.cpu.numCycles 91859 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 5381 +system.cpu.committedOps 9748 +system.cpu.num_int_alu_accesses 9654 +system.cpu.num_fp_alu_accesses 0 +system.cpu.num_func_calls 209 +system.cpu.num_conditional_control_insts 899 +system.cpu.num_int_insts 9654 +system.cpu.num_fp_insts 0 +system.cpu.num_int_register_reads 18335 +system.cpu.num_int_register_writes 7527 +system.cpu.num_fp_register_reads 0 +system.cpu.num_fp_register_writes 0 +system.cpu.num_cc_register_reads 6487 +system.cpu.num_cc_register_writes 3536 +system.cpu.num_mem_refs 1988 +system.cpu.num_load_insts 1053 +system.cpu.num_store_insts 935 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 91859 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 1208 +system.cpu.op_class::No_OpClass 1 0.01% 0.01% +system.cpu.op_class::IntAlu 7749 79.49% 79.50% +system.cpu.op_class::IntMult 3 0.03% 79.53% +system.cpu.op_class::IntDiv 7 0.07% 79.61% +system.cpu.op_class::FloatAdd 0 0.00% 79.61% +system.cpu.op_class::FloatCmp 0 0.00% 79.61% +system.cpu.op_class::FloatCvt 0 0.00% 79.61% +system.cpu.op_class::FloatMult 0 0.00% 79.61% +system.cpu.op_class::FloatMultAcc 0 0.00% 79.61% +system.cpu.op_class::FloatDiv 0 0.00% 79.61% +system.cpu.op_class::FloatMisc 0 0.00% 79.61% +system.cpu.op_class::FloatSqrt 0 0.00% 79.61% +system.cpu.op_class::SimdAdd 0 0.00% 79.61% +system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% +system.cpu.op_class::SimdAlu 0 0.00% 79.61% +system.cpu.op_class::SimdCmp 0 0.00% 79.61% +system.cpu.op_class::SimdCvt 0 0.00% 79.61% +system.cpu.op_class::SimdMisc 0 0.00% 79.61% +system.cpu.op_class::SimdMult 0 0.00% 79.61% +system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% +system.cpu.op_class::SimdShift 0 0.00% 79.61% +system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% +system.cpu.op_class::SimdSqrt 0 0.00% 79.61% +system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% +system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% +system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% +system.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% +system.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% +system.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% +system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% +system.cpu.op_class::MemRead 1053 10.80% 90.41% +system.cpu.op_class::MemWrite 935 9.59% 100.00% +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 9748 +system.ruby.clk_domain.clock 1 +system.ruby.pwrStateResidencyTicks::UNDEFINED 91859 +system.ruby.delayHist::bucket_size 1 +system.ruby.delayHist::max_bucket 9 +system.ruby.delayHist::samples 2750 +system.ruby.delayHist | 2750 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.delayHist::total 2750 system.ruby.outstanding_req_hist_seqr::bucket_size 1 system.ruby.outstanding_req_hist_seqr::max_bucket 9 -system.ruby.outstanding_req_hist_seqr::samples 8852 +system.ruby.outstanding_req_hist_seqr::samples 8853 system.ruby.outstanding_req_hist_seqr::mean 1 system.ruby.outstanding_req_hist_seqr::gmean 1 -system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8852 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 8852 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8853 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 8853 system.ruby.latency_hist_seqr::bucket_size 64 system.ruby.latency_hist_seqr::max_bucket 639 system.ruby.latency_hist_seqr::samples 8852 @@ -388,36 +388,36 @@ system.ruby.miss_latency_hist_seqr::stdev 33.880423 system.ruby.miss_latency_hist_seqr | 751 54.54% 54.54% | 589 42.77% 97.31% | 26 1.89% 99.20% | 4 0.29% 99.49% | 3 0.22% 99.71% | 4 0.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 1377 system.ruby.Directory.incomplete_times_seqr 1376 -system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.014947 # Average number of messages in buffer -system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.996691 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.029937 # Average number of messages in buffer -system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.743740 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.014990 # Average number of messages in buffer -system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999249 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.029937 # Average number of messages in buffer -system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999260 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.cacheMemory.demand_hits 7475 # Number of cache demand hits -system.ruby.l1_cntrl0.cacheMemory.demand_misses 1377 # Number of cache demand misses -system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8852 # Number of cache demand accesses -system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.014947 # Average number of messages in buffer -system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.976377 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.096364 # Average number of messages in buffer -system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999989 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.059874 # Average number of messages in buffer -system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999935 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.014990 # Average number of messages in buffer -system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.994285 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.014947 # Average number of messages in buffer -system.ruby.network.routers0.port_buffers03.avg_stall_time 5.979817 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.014990 # Average number of messages in buffer -system.ruby.network.routers0.port_buffers04.avg_stall_time 5.995167 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.089723 # Average number of messages in buffer -system.ruby.network.routers0.port_buffers07.avg_stall_time 6.744611 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states +system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.014947 +system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.996691 +system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.029937 +system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.743740 +system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.014990 +system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999249 +system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.029937 +system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999260 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 91859 +system.ruby.l1_cntrl0.cacheMemory.demand_hits 7475 +system.ruby.l1_cntrl0.cacheMemory.demand_misses 1377 +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8852 +system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.014947 +system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.976377 +system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.096375 +system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999989 +system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.059874 +system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999935 +system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.014990 +system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.994285 +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 91859 +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 91859 +system.ruby.memctrl_clk_domain.clock 3 +system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.014947 +system.ruby.network.routers0.port_buffers03.avg_stall_time 5.979817 +system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.014990 +system.ruby.network.routers0.port_buffers04.avg_stall_time 5.995167 +system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.089723 +system.ruby.network.routers0.port_buffers07.avg_stall_time 6.744611 +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 91859 system.ruby.network.routers0.percent_links_utilized 7.484297 system.ruby.network.routers0.msg_count.Control::2 1377 system.ruby.network.routers0.msg_count.Data::2 1373 @@ -427,13 +427,13 @@ system.ruby.network.routers0.msg_bytes.Control::2 11016 system.ruby.network.routers0.msg_bytes.Data::2 98856 system.ruby.network.routers0.msg_bytes.Response_Data::4 99144 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 10984 -system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.029937 # Average number of messages in buffer -system.ruby.network.routers1.port_buffers02.avg_stall_time 10.743958 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.014947 # Average number of messages in buffer -system.ruby.network.routers1.port_buffers06.avg_stall_time 1.993359 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.014990 # Average number of messages in buffer -system.ruby.network.routers1.port_buffers07.avg_stall_time 1.998476 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.029937 +system.ruby.network.routers1.port_buffers02.avg_stall_time 10.743958 +system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.014947 +system.ruby.network.routers1.port_buffers06.avg_stall_time 1.993359 +system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.014990 +system.ruby.network.routers1.port_buffers07.avg_stall_time 1.998476 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 91859 system.ruby.network.routers1.percent_links_utilized 7.484297 system.ruby.network.routers1.msg_count.Control::2 1377 system.ruby.network.routers1.msg_count.Data::2 1373 @@ -443,25 +443,25 @@ system.ruby.network.routers1.msg_bytes.Control::2 11016 system.ruby.network.routers1.msg_bytes.Data::2 98856 system.ruby.network.routers1.msg_bytes.Response_Data::4 99144 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 10984 -system.ruby.network.int_link_buffers02.avg_buf_msgs 0.029937 # Average number of messages in buffer -system.ruby.network.int_link_buffers02.avg_stall_time 7.744481 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers08.avg_buf_msgs 0.014947 # Average number of messages in buffer -system.ruby.network.int_link_buffers08.avg_stall_time 2.990007 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers09.avg_buf_msgs 0.014990 # Average number of messages in buffer -system.ruby.network.int_link_buffers09.avg_stall_time 2.997681 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers13.avg_buf_msgs 0.014947 # Average number of messages in buffer -system.ruby.network.int_link_buffers13.avg_stall_time 4.983235 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers14.avg_buf_msgs 0.014990 # Average number of messages in buffer -system.ruby.network.int_link_buffers14.avg_stall_time 4.996027 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers17.avg_buf_msgs 0.029937 # Average number of messages in buffer -system.ruby.network.int_link_buffers17.avg_stall_time 9.744154 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.014947 # Average number of messages in buffer -system.ruby.network.routers2.port_buffers03.avg_stall_time 3.986632 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.014990 # Average number of messages in buffer -system.ruby.network.routers2.port_buffers04.avg_stall_time 3.996865 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.029937 # Average number of messages in buffer -system.ruby.network.routers2.port_buffers07.avg_stall_time 8.744328 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states +system.ruby.network.int_link_buffers02.avg_buf_msgs 0.029937 +system.ruby.network.int_link_buffers02.avg_stall_time 7.744481 +system.ruby.network.int_link_buffers08.avg_buf_msgs 0.014947 +system.ruby.network.int_link_buffers08.avg_stall_time 2.990007 +system.ruby.network.int_link_buffers09.avg_buf_msgs 0.014990 +system.ruby.network.int_link_buffers09.avg_stall_time 2.997681 +system.ruby.network.int_link_buffers13.avg_buf_msgs 0.014947 +system.ruby.network.int_link_buffers13.avg_stall_time 4.983235 +system.ruby.network.int_link_buffers14.avg_buf_msgs 0.014990 +system.ruby.network.int_link_buffers14.avg_stall_time 4.996027 +system.ruby.network.int_link_buffers17.avg_buf_msgs 0.029937 +system.ruby.network.int_link_buffers17.avg_stall_time 9.744154 +system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.014947 +system.ruby.network.routers2.port_buffers03.avg_stall_time 3.986632 +system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.014990 +system.ruby.network.routers2.port_buffers04.avg_stall_time 3.996865 +system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.029937 +system.ruby.network.routers2.port_buffers07.avg_stall_time 8.744328 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 91859 system.ruby.network.routers2.percent_links_utilized 7.484297 system.ruby.network.routers2.msg_count.Control::2 1377 system.ruby.network.routers2.msg_count.Data::2 1373 @@ -471,7 +471,7 @@ system.ruby.network.routers2.msg_bytes.Control::2 11016 system.ruby.network.routers2.msg_bytes.Data::2 98856 system.ruby.network.routers2.msg_bytes.Response_Data::4 99144 system.ruby.network.routers2.msg_bytes.Writeback_Control::3 10984 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 91859 system.ruby.network.msg_count.Control 4131 system.ruby.network.msg_count.Data 4119 system.ruby.network.msg_count.Response_Data 4131 @@ -480,7 +480,7 @@ system.ruby.network.msg_byte.Control 33048 system.ruby.network.msg_byte.Data 296568 system.ruby.network.msg_byte.Response_Data 297432 system.ruby.network.msg_byte.Writeback_Control 32952 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 91859 system.ruby.network.routers0.throttle0.link_utilization 7.493006 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1377 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1373 @@ -511,16 +511,16 @@ system.ruby.network.routers2.throttle1.msg_count.Control::2 1377 system.ruby.network.routers2.throttle1.msg_count.Data::2 1373 system.ruby.network.routers2.throttle1.msg_bytes.Control::2 11016 system.ruby.network.routers2.throttle1.msg_bytes.Data::2 98856 -system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 1377 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 1377 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 1377 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 1373 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 1373 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 1373 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_1::bucket_size 1 +system.ruby.delayVCHist.vnet_1::max_bucket 9 +system.ruby.delayVCHist.vnet_1::samples 1377 +system.ruby.delayVCHist.vnet_1 | 1377 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.delayVCHist.vnet_1::total 1377 +system.ruby.delayVCHist.vnet_2::bucket_size 1 +system.ruby.delayVCHist.vnet_2::max_bucket 9 +system.ruby.delayVCHist.vnet_2::samples 1373 +system.ruby.delayVCHist.vnet_2 | 1373 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.delayVCHist.vnet_2::total 1373 system.ruby.LD.latency_hist_seqr::bucket_size 32 system.ruby.LD.latency_hist_seqr::max_bucket 319 system.ruby.LD.latency_hist_seqr::samples 1045 diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini index bc04df7fd..1bbdae21e 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=timing @@ -85,6 +86,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -100,14 +102,14 @@ eventq_index=0 [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -121,6 +123,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -133,15 +136,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dtb] type=X86TLB @@ -166,14 +170,14 @@ port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -187,6 +191,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -199,15 +204,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=X86LocalApic @@ -253,14 +259,14 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -274,6 +280,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -286,15 +293,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -330,7 +338,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -339,14 +347,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/x86/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/x86/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -370,6 +379,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -381,7 +391,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -389,6 +399,13 @@ width=16 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -397,6 +414,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -404,7 +422,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr index aadc3d011..c0b55d123 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout index 17523a325..30d3fbf05 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:35:23 -gem5 started Jul 21 2016 14:36:20 -gem5 executing on e108600-lin, pid 18567 -command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/x86/linux/simple-timing +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:21 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87155 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 30886500 because target called exit() +Exiting @ tick 31247500 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index b6ef5972c..e9a5f137e 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,501 +1,501 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000031 # Number of seconds simulated -sim_ticks 31247500 # Number of ticks simulated -final_tick 31247500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 377585 # Simulator instruction rate (inst/s) -host_op_rate 682900 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2185869298 # Simulator tick rate (ticks/s) -host_mem_usage 268708 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 5381 # Number of instructions simulated -sim_ops 9748 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory -system.physmem.bytes_read::total 23104 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 14528 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 14528 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory -system.physmem.num_reads::total 361 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 464933195 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 274453956 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 739387151 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 464933195 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 464933195 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 464933195 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 274453956 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 739387151 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 31247500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 62495 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5381 # Number of instructions committed -system.cpu.committedOps 9748 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 209 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls -system.cpu.num_int_insts 9654 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 18335 # number of times the integer registers were read -system.cpu.num_int_register_writes 7527 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 6487 # number of times the CC registers were read -system.cpu.num_cc_register_writes 3536 # number of times the CC registers were written -system.cpu.num_mem_refs 1988 # number of memory refs -system.cpu.num_load_insts 1053 # Number of load instructions -system.cpu.num_store_insts 935 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 62494.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1208 # Number of branches fetched -system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction -system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction -system.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction -system.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction -system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 9748 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 80.527852 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 80.527852 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.019660 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.019660 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.032715 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4110 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4110 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 856 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1854 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1854 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1854 # number of overall hits -system.cpu.dcache.overall_hits::total 1854 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 134 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses -system.cpu.dcache.overall_misses::total 134 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3465000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3465000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4977000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4977000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 8442000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8442000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 8442000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8442000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1053 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1053 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1988 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1988 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1988 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1988 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052232 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.052232 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084492 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.084492 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.067404 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.067404 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.067404 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.067404 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3410000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3410000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4898000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4898000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8308000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8308000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8308000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8308000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052232 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084492 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.067404 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.067404 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative 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-system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.111328 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 13956 # Number of tag accesses -system.cpu.icache.tags.data_accesses 13956 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 6636 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 6636 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 6636 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 6636 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 6636 # number of overall hits -system.cpu.icache.overall_hits::total 6636 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 228 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 228 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 228 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses -system.cpu.icache.overall_misses::total 228 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14315500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14315500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14315500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14315500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14315500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14315500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 6864 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 6864 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 6864 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 6864 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 6864 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 6864 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.033217 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.033217 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.033217 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.033217 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.033217 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.033217 # miss rate for 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-system.cpu.icache.demand_mshr_miss_latency::total 14087500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14087500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14087500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033217 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.033217 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.033217 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61787.280702 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61787.280702 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61787.280702 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 61787.280702 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61787.280702 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 61787.280702 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 185.792229 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 361 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.002770 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.219349 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 80.572880 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003211 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002459 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005670 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 361 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 247 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011017 # Percentage of cache occupancy per task id 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number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 55 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 55 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 227 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 361 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 227 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses -system.cpu.l2cache.overall_misses::total 361 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4779500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4779500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13734000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 13734000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3327500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 3327500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 13734000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8107000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21841000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 13734000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8107000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21841000 # number of overall miss cycles -system.cpu.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 228 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 228 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 55 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 55 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 228 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 134 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 362 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 228 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 134 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 362 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.995614 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.995614 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995614 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.997238 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995614 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.997238 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60502.202643 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60502.202643 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60502.202643 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60501.385042 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60502.202643 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60501.385042 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 227 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 227 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 55 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 55 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 227 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 227 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 361 # number of overall MSHR misses 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-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11464000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6767000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18231000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.995614 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997238 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997238 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50502.202643 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50502.202643 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50502.202643 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.385042 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50502.202643 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.385042 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 362 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 79 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 228 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 55 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 456 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 268 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 724 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8576 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 23168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 362 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.002762 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.052559 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 361 99.72% 99.72% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1 0.28% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 362 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 342000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 201000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 361 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 282 # Transaction distribution -system.membus.trans_dist::ReadExReq 79 # Transaction distribution -system.membus.trans_dist::ReadExResp 79 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 282 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 722 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 23104 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 23104 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 361 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 361 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 361 # Request fanout histogram -system.membus.reqLayer0.occupancy 361500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1805000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 5.8 # Layer utilization (%) +sim_seconds 0.000031 +sim_ticks 31247500 +final_tick 31247500 +sim_freq 1000000000000 +host_inst_rate 194718 +host_op_rate 352470 +host_tick_rate 1129073998 +host_mem_usage 278812 +host_seconds 0.03 +sim_insts 5381 +sim_ops 9748 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 31247500 +system.physmem.bytes_read::cpu.inst 14528 +system.physmem.bytes_read::cpu.data 8576 +system.physmem.bytes_read::total 23104 +system.physmem.bytes_inst_read::cpu.inst 14528 +system.physmem.bytes_inst_read::total 14528 +system.physmem.num_reads::cpu.inst 227 +system.physmem.num_reads::cpu.data 134 +system.physmem.num_reads::total 361 +system.physmem.bw_read::cpu.inst 464933195 +system.physmem.bw_read::cpu.data 274453956 +system.physmem.bw_read::total 739387151 +system.physmem.bw_inst_read::cpu.inst 464933195 +system.physmem.bw_inst_read::total 464933195 +system.physmem.bw_total::cpu.inst 464933195 +system.physmem.bw_total::cpu.data 274453956 +system.physmem.bw_total::total 739387151 +system.pwrStateResidencyTicks::UNDEFINED 31247500 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 31247500 +system.cpu.apic_clk_domain.clock 8000 +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 31247500 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 31247500 +system.cpu.workload.numSyscalls 11 +system.cpu.pwrStateResidencyTicks::ON 31247500 +system.cpu.numCycles 62495 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 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+system.cpu.op_class::FloatCmp 0 0.00% 79.61% +system.cpu.op_class::FloatCvt 0 0.00% 79.61% +system.cpu.op_class::FloatMult 0 0.00% 79.61% +system.cpu.op_class::FloatMultAcc 0 0.00% 79.61% +system.cpu.op_class::FloatDiv 0 0.00% 79.61% +system.cpu.op_class::FloatMisc 0 0.00% 79.61% +system.cpu.op_class::FloatSqrt 0 0.00% 79.61% +system.cpu.op_class::SimdAdd 0 0.00% 79.61% +system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% +system.cpu.op_class::SimdAlu 0 0.00% 79.61% +system.cpu.op_class::SimdCmp 0 0.00% 79.61% +system.cpu.op_class::SimdCvt 0 0.00% 79.61% +system.cpu.op_class::SimdMisc 0 0.00% 79.61% +system.cpu.op_class::SimdMult 0 0.00% 79.61% +system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% +system.cpu.op_class::SimdShift 0 0.00% 79.61% +system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% +system.cpu.op_class::SimdSqrt 0 0.00% 79.61% +system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% +system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% +system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% 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80.527852 +system.cpu.dcache.tags.occ_percent::cpu.data 0.019660 +system.cpu.dcache.tags.occ_percent::total 0.019660 +system.cpu.dcache.tags.occ_task_id_blocks::1024 134 +system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 +system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 +system.cpu.dcache.tags.occ_task_id_percent::1024 0.032715 +system.cpu.dcache.tags.tag_accesses 4110 +system.cpu.dcache.tags.data_accesses 4110 +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 31247500 +system.cpu.dcache.ReadReq_hits::cpu.data 998 +system.cpu.dcache.ReadReq_hits::total 998 +system.cpu.dcache.WriteReq_hits::cpu.data 856 +system.cpu.dcache.WriteReq_hits::total 856 +system.cpu.dcache.demand_hits::cpu.data 1854 +system.cpu.dcache.demand_hits::total 1854 +system.cpu.dcache.overall_hits::cpu.data 1854 +system.cpu.dcache.overall_hits::total 1854 +system.cpu.dcache.ReadReq_misses::cpu.data 55 +system.cpu.dcache.ReadReq_misses::total 55 +system.cpu.dcache.WriteReq_misses::cpu.data 79 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+system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 31247500 +system.membus.trans_dist::ReadResp 282 +system.membus.trans_dist::ReadExReq 79 +system.membus.trans_dist::ReadExResp 79 +system.membus.trans_dist::ReadSharedReq 282 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 +system.membus.pkt_count::total 722 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 23104 +system.membus.pkt_size::total 23104 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 361 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 361 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 361 +system.membus.reqLayer0.occupancy 361500 +system.membus.reqLayer0.utilization 1.2 +system.membus.respLayer1.occupancy 1805000 +system.membus.respLayer1.utilization 5.8 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini index 5c4d73bb2..d465f3325 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini @@ -739,7 +739,7 @@ executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/h gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout pgid=100 pid=100 @@ -763,7 +763,7 @@ executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/h gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout pgid=100 pid=101 diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout index 98b12d0fa..45d42fd47 100755 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 29 2017 21:35:16 -gem5 started Mar 29 2017 21:35:26 -gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87431 +gem5 compiled Mar 29 2017 21:52:42 +gem5 started Mar 29 2017 21:52:53 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 118268 command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt Global frequency set at 1000000000000 ticks per second Hello world! Hello world! -Exiting @ tick 27117500 because target called exit() +Exiting @ tick 27117500 because exiting with last active thread context diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt index ed0c77d41..1efa6d783 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000027 sim_ticks 27117500 final_tick 27117500 sim_freq 1000000000000 -host_inst_rate 132500 -host_op_rate 132484 -host_tick_rate 281303428 -host_mem_usage 265748 -host_seconds 0.10 +host_inst_rate 121145 +host_op_rate 121128 +host_tick_rate 257188425 +host_mem_usage 265776 +host_seconds 0.11 sim_insts 12770 sim_ops 12770 system.voltage_domain.voltage 1 @@ -755,7 +755,7 @@ system.cpu.cpi_total 4.247142 system.cpu.ipc::0 0.117726 system.cpu.ipc::1 0.117726 system.cpu.ipc_total 0.235452 -system.cpu.int_regfile_reads 23898 +system.cpu.int_regfile_reads 23899 system.cpu.int_regfile_writes 13306 system.cpu.fp_regfile_reads 16 system.cpu.fp_regfile_writes 4 diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini index 7685aa1bd..4fcd776f1 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -65,7 +65,7 @@ SSITSize=1024 activity=0 backComSize=5 branchPred=system.cpu.branchPred -cachePorts=200 +cacheStorePorts=200 checker=Null clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 @@ -139,6 +139,7 @@ socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -715,7 +716,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=insttest cwd= drivers= @@ -724,14 +725,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr index bbcd9d751..707fed98b 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr @@ -1,3 +1,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout index 7b48b6ce0..d5dd8e395 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3- gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 29 2016 18:44:12 -gem5 started Nov 29 2016 18:44:33 -gem5 executing on zizzer, pid 58827 -command line: /z/powerjg/gem5-upstream/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/sparc/linux/o3-timing +gem5 compiled Apr 3 2017 18:41:19 +gem5 started Apr 3 2017 18:41:39 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 64867 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Begining test of difficult SPARC instructions... LDSTUB: Passed SWAP: Passed @@ -21,4 +20,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 29908500 because target called exit() +Exiting @ tick 29673500 because exiting with last active thread context diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index d8bf75e3e..c16641d08 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,990 +1,990 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000030 # Number of seconds simulated -sim_ticks 29673500 # Number of ticks simulated -final_tick 29673500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 97740 # Simulator instruction rate (inst/s) -host_op_rate 97731 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 200871294 # Simulator tick rate (ticks/s) -host_mem_usage 251556 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host -sim_insts 14436 # Number of instructions simulated -sim_ops 14436 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory -system.physmem.bytes_read::total 32640 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 23232 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 23232 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 363 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory -system.physmem.num_reads::total 510 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 782920788 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 317050567 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1099971355 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 782920788 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 782920788 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 782920788 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 317050567 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1099971355 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 511 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 511 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 32704 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 32704 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 104 # Per bank write bursts -system.physmem.perBankRdBursts::1 28 # Per bank write bursts -system.physmem.perBankRdBursts::2 54 # Per bank write bursts -system.physmem.perBankRdBursts::3 28 # Per bank write bursts -system.physmem.perBankRdBursts::4 22 # Per bank write bursts -system.physmem.perBankRdBursts::5 0 # Per bank write bursts -system.physmem.perBankRdBursts::6 32 # Per bank write bursts -system.physmem.perBankRdBursts::7 38 # Per bank write bursts -system.physmem.perBankRdBursts::8 7 # Per bank write bursts -system.physmem.perBankRdBursts::9 4 # Per bank write bursts -system.physmem.perBankRdBursts::10 2 # Per bank write bursts -system.physmem.perBankRdBursts::11 0 # Per bank write bursts -system.physmem.perBankRdBursts::12 57 # Per bank write bursts -system.physmem.perBankRdBursts::13 31 # Per bank write bursts -system.physmem.perBankRdBursts::14 63 # Per bank write bursts -system.physmem.perBankRdBursts::15 41 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 29642000 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 511 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 153 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 58 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 78 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 393.025641 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 252.718123 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 347.605052 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 17 21.79% 21.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18 23.08% 44.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 14 17.95% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4 5.13% 67.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5 6.41% 74.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1 1.28% 75.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7 8.97% 84.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 12 15.38% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 78 # Bytes accessed per row activation -system.physmem.totQLat 6610250 # Total ticks spent queuing -system.physmem.totMemAccLat 16191500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2555000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12935.91 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31685.91 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1102.13 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1102.13 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 8.61 # Data bus utilization in percentage -system.physmem.busUtilRead 8.61 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 422 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.58 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 58007.83 # Average gap between requests -system.physmem.pageHitRate 82.58 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 364140 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 174570 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2184840 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3606960 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 63360 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 9847320 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 1440 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 18086550 # Total energy per rank (pJ) -system.physmem_0.averagePower 609.513459 # Core power per rank (mW) -system.physmem_0.totalIdleTime 21469250 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 40500 # Time in different power states -system.physmem_0.memoryStateTime::REF 780000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 3750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 7251250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 21598000 # Time in different power states -system.physmem_1.actEnergy 271320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 121440 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1463700 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2504580 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 86400 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 10184760 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 622560 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 17098680 # Total energy per rank (pJ) -system.physmem_1.averagePower 576.222419 # Core power per rank (mW) -system.physmem_1.totalIdleTime 23952750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 143000 # Time in different power states -system.physmem_1.memoryStateTime::REF 780000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 1619750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 4797750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 22333000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 11901 # Number of BP lookups -system.cpu.branchPred.condPredicted 7287 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1354 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9352 # Number of BTB lookups -system.cpu.branchPred.BTBHits 0 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 685 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 9352 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 1949 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 7403 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 793 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.numSyscalls 18 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 29673500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 59348 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15163 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 55604 # Number of instructions fetch has processed -system.cpu.fetch.Branches 11901 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 2634 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 17364 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2905 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 12 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 9 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1168 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 12 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 7191 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 701 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 35180 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.580557 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.839184 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 22867 65.00% 65.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4490 12.76% 77.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 508 1.44% 79.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 450 1.28% 80.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 761 2.16% 82.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 731 2.08% 84.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 296 0.84% 85.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 343 0.97% 86.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4734 13.46% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 35180 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.200529 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.936914 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12094 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 13233 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 7639 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 762 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1452 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 39805 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1452 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 12828 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1813 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9904 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 7640 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1543 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 35279 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full -system.cpu.rename.SQFullEvents 1128 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 30611 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 63420 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 52396 # Number of integer rename lookups -system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16792 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 761 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 767 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4154 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 4391 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 2803 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 27854 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 724 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 24627 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 122 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 14142 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 10452 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 249 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 35180 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.700028 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.493682 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 26218 74.53% 74.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3125 8.88% 83.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1567 4.45% 87.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1507 4.28% 92.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1190 3.38% 95.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 757 2.15% 97.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 486 1.38% 99.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 254 0.72% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 76 0.22% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 35180 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 151 52.07% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.07% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 51 17.59% 69.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 88 30.34% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 18085 73.44% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 4096 16.63% 90.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 2446 9.93% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 24627 # Type of FU issued -system.cpu.iq.rate 0.414959 # Inst issue rate -system.cpu.iq.fu_busy_cnt 290 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011776 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 84846 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 42748 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 22066 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 24917 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2166 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1355 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 22 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1452 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1841 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 30085 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 231 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 4391 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2803 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 724 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 209 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1460 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1669 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 23080 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 3816 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1547 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1507 # number of nop insts executed -system.cpu.iew.exec_refs 6070 # number of memory reference insts executed -system.cpu.iew.exec_branches 4884 # Number of branches executed -system.cpu.iew.exec_stores 2254 # Number of stores executed -system.cpu.iew.exec_rate 0.388893 # Inst execution rate -system.cpu.iew.wb_sent 22529 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 22066 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10367 # num instructions producing a value -system.cpu.iew.wb_consumers 13651 # num instructions consuming a value -system.cpu.iew.wb_rate 0.371807 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.759432 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 14855 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1354 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 32262 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.469965 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.260994 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 25609 79.38% 79.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 3577 11.09% 90.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1157 3.59% 94.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 603 1.87% 95.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 332 1.03% 96.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 298 0.92% 97.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 393 1.22% 99.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 58 0.18% 99.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 235 0.73% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 32262 # Number of insts commited each cycle -system.cpu.commit.committedInsts 15162 # Number of instructions committed -system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 3673 # Number of memory references committed -system.cpu.commit.loads 2225 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 3358 # Number of branches committed -system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 12174 # Number of committed integer instructions. -system.cpu.commit.function_calls 187 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 726 4.79% 4.79% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 10763 70.99% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 2225 14.67% 90.45% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 1448 9.55% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 15162 # Class of committed instruction -system.cpu.commit.bw_lim_events 235 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 61221 # The number of ROB reads -system.cpu.rob.rob_writes 63021 # The number of ROB writes -system.cpu.timesIdled 194 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 24168 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 14436 # Number of Instructions Simulated -system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 4.111111 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.111111 # CPI: Total CPI of All Threads -system.cpu.ipc 0.243243 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.243243 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 36173 # number of integer regfile reads -system.cpu.int_regfile_writes 20126 # number of integer regfile writes -system.cpu.misc_regfile_reads 7956 # number of misc regfile reads -system.cpu.misc_regfile_writes 569 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 98.931439 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 4528 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 31.013699 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 98.931439 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.024153 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.024153 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 10292 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 10292 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 3489 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3489 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits -system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 4522 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4522 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4522 # number of overall hits -system.cpu.dcache.overall_hits::total 4522 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 136 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 136 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 545 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 545 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 545 # number of overall misses -system.cpu.dcache.overall_misses::total 545 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10734500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10734500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 29028485 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 29028485 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39762985 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39762985 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39762985 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39762985 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3625 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3625 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 5067 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 5067 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 5067 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 5067 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037517 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.037517 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.107559 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.107559 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.107559 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.107559 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78930.147059 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 78930.147059 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70974.290954 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70974.290954 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72959.605505 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72959.605505 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72959.605505 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72959.605505 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1437 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 75.631579 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 71 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 397 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 397 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 397 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 397 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6080000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6080000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6906500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6906500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12986500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12986500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12986500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12986500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017931 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017931 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029209 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.029209 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029209 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.029209 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 93538.461538 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 93538.461538 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83210.843373 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83210.843373 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87746.621622 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 87746.621622 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87746.621622 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 87746.621622 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 202.053622 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 6606 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18.098630 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 202.053622 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.098659 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.098659 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 270 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 14747 # Number of tag accesses -system.cpu.icache.tags.data_accesses 14747 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 6606 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 6606 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 6606 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 6606 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 6606 # number of overall hits -system.cpu.icache.overall_hits::total 6606 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 585 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 585 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 585 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 585 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 585 # number of overall misses -system.cpu.icache.overall_misses::total 585 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 45161000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 45161000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 45161000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 45161000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 45161000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 45161000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 7191 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 7191 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 7191 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 7191 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 7191 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 7191 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081352 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.081352 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.081352 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.081352 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.081352 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.081352 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77198.290598 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 77198.290598 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 77198.290598 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 77198.290598 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 77198.290598 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 77198.290598 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 63.500000 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 220 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 220 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 220 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 220 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 220 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 220 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 365 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 365 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 365 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29981500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 29981500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29981500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 29981500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29981500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 29981500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050758 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050758 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050758 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.050758 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050758 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.050758 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82141.095890 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82141.095890 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82141.095890 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 82141.095890 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82141.095890 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 82141.095890 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 300.398022 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 509 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.003929 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 201.414921 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 98.983101 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006147 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.003021 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.009167 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 394 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.015533 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4613 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4613 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits -system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 363 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 363 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 65 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 65 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 363 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 148 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 511 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 363 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 148 # number of overall misses -system.cpu.l2cache.overall_misses::total 511 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6781000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6781000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 29411000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 29411000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5985000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 5985000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 29411000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12766000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 42177000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 29411000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12766000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 42177000 # number of overall miss cycles -system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 365 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 365 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 65 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 65 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 365 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 513 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 365 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 148 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 513 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.994521 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.994521 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994521 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.996101 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994521 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.996101 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81698.795181 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81698.795181 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81022.038567 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81022.038567 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92076.923077 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92076.923077 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81022.038567 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86256.756757 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 82538.160470 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81022.038567 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86256.756757 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82538.160470 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 363 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 363 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 65 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 65 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 363 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 511 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 363 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 511 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5951000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5951000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 25781000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 25781000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5355000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5355000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25781000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11306000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 37087000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25781000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11306000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 37087000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.994521 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.996101 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.996101 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71698.795181 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71698.795181 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71022.038567 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71022.038567 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82384.615385 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 82384.615385 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71022.038567 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76391.891892 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72577.299413 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71022.038567 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76391.891892 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72577.299413 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 513 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 428 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 365 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 65 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1024 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 32704 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 513 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.003899 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.062378 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 511 99.61% 99.61% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2 0.39% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 513 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 256500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 547500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 219000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 426 # Transaction distribution -system.membus.trans_dist::ReadExReq 83 # Transaction distribution -system.membus.trans_dist::ReadExResp 83 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 428 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1020 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1020 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 32576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 32576 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 511 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 511 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 511 # Request fanout histogram -system.membus.reqLayer0.occupancy 623500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2697250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 9.1 # Layer utilization (%) +sim_seconds 0.000030 +sim_ticks 29673500 +final_tick 29673500 +sim_freq 1000000000000 +host_inst_rate 61209 +host_op_rate 61203 +host_tick_rate 125793033 +host_mem_usage 263540 +host_seconds 0.24 +sim_insts 14436 +sim_ops 14436 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 29673500 +system.physmem.bytes_read::cpu.inst 23232 +system.physmem.bytes_read::cpu.data 9408 +system.physmem.bytes_read::total 32640 +system.physmem.bytes_inst_read::cpu.inst 23232 +system.physmem.bytes_inst_read::total 23232 +system.physmem.num_reads::cpu.inst 363 +system.physmem.num_reads::cpu.data 147 +system.physmem.num_reads::total 510 +system.physmem.bw_read::cpu.inst 782920788 +system.physmem.bw_read::cpu.data 317050567 +system.physmem.bw_read::total 1099971355 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+system.physmem_0.preEnergy 174570 +system.physmem_0.readEnergy 2184840 +system.physmem_0.writeEnergy 0 +system.physmem_0.refreshEnergy 1843920.000000 +system.physmem_0.actBackEnergy 3606960 +system.physmem_0.preBackEnergy 63360 +system.physmem_0.actPowerDownEnergy 9847320 +system.physmem_0.prePowerDownEnergy 1440 +system.physmem_0.selfRefreshEnergy 0 +system.physmem_0.totalEnergy 18086550 +system.physmem_0.averagePower 609.513459 +system.physmem_0.totalIdleTime 21469250 +system.physmem_0.memoryStateTime::IDLE 40500 +system.physmem_0.memoryStateTime::REF 780000 +system.physmem_0.memoryStateTime::SREF 0 +system.physmem_0.memoryStateTime::PRE_PDN 3750 +system.physmem_0.memoryStateTime::ACT 7251250 +system.physmem_0.memoryStateTime::ACT_PDN 21598000 +system.physmem_1.actEnergy 271320 +system.physmem_1.preEnergy 121440 +system.physmem_1.readEnergy 1463700 +system.physmem_1.writeEnergy 0 +system.physmem_1.refreshEnergy 1843920.000000 +system.physmem_1.actBackEnergy 2504580 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0.00% 0.00% +system.cpu.iq.fu_full::IntAlu 151 52.07% 52.07% +system.cpu.iq.fu_full::IntMult 0 0.00% 52.07% +system.cpu.iq.fu_full::IntDiv 0 0.00% 52.07% +system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.07% +system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.07% +system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.07% +system.cpu.iq.fu_full::FloatMult 0 0.00% 52.07% +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 52.07% +system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.07% +system.cpu.iq.fu_full::FloatMisc 0 0.00% 52.07% +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.07% +system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.07% +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.07% +system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.07% +system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.07% +system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.07% +system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.07% +system.cpu.iq.fu_full::SimdMult 0 0.00% 52.07% +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.07% +system.cpu.iq.fu_full::SimdShift 0 0.00% 52.07% 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+system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 1 +system.cpu.toL2Bus.snoop_fanout::total 513 +system.cpu.toL2Bus.reqLayer0.occupancy 256500 +system.cpu.toL2Bus.reqLayer0.utilization 0.9 +system.cpu.toL2Bus.respLayer0.occupancy 547500 +system.cpu.toL2Bus.respLayer0.utilization 1.8 +system.cpu.toL2Bus.respLayer1.occupancy 219000 +system.cpu.toL2Bus.respLayer1.utilization 0.7 +system.membus.snoop_filter.tot_requests 511 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 29673500 +system.membus.trans_dist::ReadResp 426 +system.membus.trans_dist::ReadExReq 83 +system.membus.trans_dist::ReadExResp 83 +system.membus.trans_dist::ReadSharedReq 428 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1020 +system.membus.pkt_count::total 1020 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 32576 +system.membus.pkt_size::total 32576 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 511 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 511 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 511 +system.membus.reqLayer0.occupancy 623500 +system.membus.reqLayer0.utilization 2.1 +system.membus.respLayer1.occupancy 2697250 +system.membus.respLayer1.utilization 9.1 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini index 28ad26872..297f86454 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini @@ -88,6 +88,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -118,7 +119,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=insttest cwd= drivers= @@ -127,14 +128,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/insttest/bin/sparc/linux/insttest +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -158,6 +160,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -169,7 +172,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -177,6 +180,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -185,6 +195,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -192,7 +203,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr index aadc3d011..c0b55d123 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout index da1b76716..bf2b3f4bd 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/sim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:30:06 -gem5 started Jul 21 2016 14:30:36 -gem5 executing on e108600-lin, pid 38677 -command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/02.insttest/sparc/linux/simple-atomic +gem5 compiled Apr 3 2017 18:41:19 +gem5 started Apr 3 2017 18:41:41 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 64897 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/02.insttest/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Begining test of difficult SPARC instructions... LDSTUB: Passed SWAP: Passed @@ -21,4 +20,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 7612000 because target called exit() +Exiting @ tick 7612000 because exiting with last active thread context diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt index 008914f75..322c3c70b 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt @@ -1,139 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000008 # Number of seconds simulated -sim_ticks 7612000 # Number of ticks simulated -final_tick 7612000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 446852 # Simulator instruction rate (inst/s) -host_op_rate 446721 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 224213840 # Simulator tick rate (ticks/s) -host_mem_usage 239476 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -sim_insts 15162 # Number of instructions simulated -sim_ops 15162 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 7612000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 60828 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 11342 # Number of bytes read from this memory -system.physmem.bytes_read::total 72170 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 60828 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 60828 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 9042 # Number of bytes written to this memory -system.physmem.bytes_written::total 9042 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15207 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2225 # Number of read requests responded to by this memory -system.physmem.num_reads::total 17432 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 1442 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1442 # Number of write requests responded to by this memory -system.physmem.num_other::cpu.data 6 # Number of other requests responded to by this memory -system.physmem.num_other::total 6 # Number of other requests responded to by this memory -system.physmem.bw_read::cpu.inst 7991066737 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1490015765 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9481082501 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7991066737 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7991066737 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1187861272 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1187861272 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7991066737 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2677877036 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10668943773 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 7612000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.numSyscalls 18 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 7612000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 15225 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 15162 # Number of instructions committed -system.cpu.committedOps 15162 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 12219 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 385 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 2434 # number of instructions that are conditional controls -system.cpu.num_int_insts 12219 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 29037 # number of times the integer registers were read -system.cpu.num_int_register_writes 13819 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 3683 # number of memory refs -system.cpu.num_load_insts 2231 # Number of load instructions -system.cpu.num_store_insts 1452 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 15224.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 3363 # Number of branches fetched -system.cpu.op_class::No_OpClass 726 4.77% 4.77% # Class of executed instruction -system.cpu.op_class::IntAlu 10798 71.01% 75.78% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::MemRead 2231 14.67% 90.45% # Class of executed instruction -system.cpu.op_class::MemWrite 1452 9.55% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 15207 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 7612000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 17432 # Transaction distribution -system.membus.trans_dist::ReadResp 17432 # Transaction distribution -system.membus.trans_dist::WriteReq 1442 # Transaction distribution -system.membus.trans_dist::WriteResp 1442 # Transaction distribution -system.membus.trans_dist::SwapReq 6 # Transaction distribution -system.membus.trans_dist::SwapResp 6 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 30414 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 7346 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 37760 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 60828 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 20442 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 81270 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 18880 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 18880 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 18880 # Request fanout histogram +sim_seconds 0.000008 +sim_ticks 7612000 +final_tick 7612000 +sim_freq 1000000000000 +host_inst_rate 370319 +host_op_rate 370098 +host_tick_rate 185717309 +host_mem_usage 251756 +host_seconds 0.04 +sim_insts 15162 +sim_ops 15162 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 7612000 +system.physmem.bytes_read::cpu.inst 60828 +system.physmem.bytes_read::cpu.data 11342 +system.physmem.bytes_read::total 72170 +system.physmem.bytes_inst_read::cpu.inst 60828 +system.physmem.bytes_inst_read::total 60828 +system.physmem.bytes_written::cpu.data 9042 +system.physmem.bytes_written::total 9042 +system.physmem.num_reads::cpu.inst 15207 +system.physmem.num_reads::cpu.data 2225 +system.physmem.num_reads::total 17432 +system.physmem.num_writes::cpu.data 1442 +system.physmem.num_writes::total 1442 +system.physmem.num_other::cpu.data 6 +system.physmem.num_other::total 6 +system.physmem.bw_read::cpu.inst 7991066737 +system.physmem.bw_read::cpu.data 1490015765 +system.physmem.bw_read::total 9481082501 +system.physmem.bw_inst_read::cpu.inst 7991066737 +system.physmem.bw_inst_read::total 7991066737 +system.physmem.bw_write::cpu.data 1187861272 +system.physmem.bw_write::total 1187861272 +system.physmem.bw_total::cpu.inst 7991066737 +system.physmem.bw_total::cpu.data 2677877036 +system.physmem.bw_total::total 10668943773 +system.pwrStateResidencyTicks::UNDEFINED 7612000 +system.cpu_clk_domain.clock 500 +system.cpu.workload.numSyscalls 18 +system.cpu.pwrStateResidencyTicks::ON 7612000 +system.cpu.numCycles 15225 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 15162 +system.cpu.committedOps 15162 +system.cpu.num_int_alu_accesses 12219 +system.cpu.num_fp_alu_accesses 0 +system.cpu.num_func_calls 385 +system.cpu.num_conditional_control_insts 2434 +system.cpu.num_int_insts 12219 +system.cpu.num_fp_insts 0 +system.cpu.num_int_register_reads 29037 +system.cpu.num_int_register_writes 13819 +system.cpu.num_fp_register_reads 0 +system.cpu.num_fp_register_writes 0 +system.cpu.num_mem_refs 3683 +system.cpu.num_load_insts 2231 +system.cpu.num_store_insts 1452 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 15225 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 3363 +system.cpu.op_class::No_OpClass 726 4.77% 4.77% +system.cpu.op_class::IntAlu 10798 71.01% 75.78% +system.cpu.op_class::IntMult 0 0.00% 75.78% +system.cpu.op_class::IntDiv 0 0.00% 75.78% +system.cpu.op_class::FloatAdd 0 0.00% 75.78% +system.cpu.op_class::FloatCmp 0 0.00% 75.78% +system.cpu.op_class::FloatCvt 0 0.00% 75.78% +system.cpu.op_class::FloatMult 0 0.00% 75.78% +system.cpu.op_class::FloatMultAcc 0 0.00% 75.78% +system.cpu.op_class::FloatDiv 0 0.00% 75.78% +system.cpu.op_class::FloatMisc 0 0.00% 75.78% +system.cpu.op_class::FloatSqrt 0 0.00% 75.78% +system.cpu.op_class::SimdAdd 0 0.00% 75.78% +system.cpu.op_class::SimdAddAcc 0 0.00% 75.78% +system.cpu.op_class::SimdAlu 0 0.00% 75.78% +system.cpu.op_class::SimdCmp 0 0.00% 75.78% +system.cpu.op_class::SimdCvt 0 0.00% 75.78% +system.cpu.op_class::SimdMisc 0 0.00% 75.78% +system.cpu.op_class::SimdMult 0 0.00% 75.78% +system.cpu.op_class::SimdMultAcc 0 0.00% 75.78% +system.cpu.op_class::SimdShift 0 0.00% 75.78% +system.cpu.op_class::SimdShiftAcc 0 0.00% 75.78% +system.cpu.op_class::SimdSqrt 0 0.00% 75.78% +system.cpu.op_class::SimdFloatAdd 0 0.00% 75.78% +system.cpu.op_class::SimdFloatAlu 0 0.00% 75.78% +system.cpu.op_class::SimdFloatCmp 0 0.00% 75.78% +system.cpu.op_class::SimdFloatCvt 0 0.00% 75.78% +system.cpu.op_class::SimdFloatDiv 0 0.00% 75.78% +system.cpu.op_class::SimdFloatMisc 0 0.00% 75.78% +system.cpu.op_class::SimdFloatMult 0 0.00% 75.78% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 75.78% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 75.78% +system.cpu.op_class::MemRead 2231 14.67% 90.45% +system.cpu.op_class::MemWrite 1452 9.55% 100.00% +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 15207 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 7612000 +system.membus.trans_dist::ReadReq 17432 +system.membus.trans_dist::ReadResp 17432 +system.membus.trans_dist::WriteReq 1442 +system.membus.trans_dist::WriteResp 1442 +system.membus.trans_dist::SwapReq 6 +system.membus.trans_dist::SwapResp 6 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 30414 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 7346 +system.membus.pkt_count::total 37760 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 60828 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 20442 +system.membus.pkt_size::total 81270 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 18880 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 18880 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 18880 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini index 76eaa1c9f..d56f74081 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini @@ -85,6 +85,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -94,14 +95,14 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -115,6 +116,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -127,15 +129,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dtb] type=SparcTLB @@ -145,14 +148,14 @@ size=64 [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -166,6 +169,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -178,15 +182,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=SparcInterrupts @@ -204,14 +209,14 @@ size=64 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -225,6 +230,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -237,15 +243,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -281,7 +288,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=insttest cwd= drivers= @@ -290,14 +297,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/insttest/bin/sparc/linux/insttest +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -321,6 +329,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -332,7 +341,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -340,6 +349,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -348,6 +364,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -355,7 +372,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr index aadc3d011..c0b55d123 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout index aa11b3776..65544f70a 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/sim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:30:06 -gem5 started Jul 21 2016 14:30:38 -gem5 executing on e108600-lin, pid 38722 -command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/02.insttest/sparc/linux/simple-timing +gem5 compiled Apr 3 2017 18:41:19 +gem5 started Apr 3 2017 18:41:42 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 64930 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/02.insttest/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Begining test of difficult SPARC instructions... LDSTUB: Passed SWAP: Passed @@ -21,4 +20,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 44282500 because target called exit() +Exiting @ tick 44698500 because exiting with last active thread context diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt index 08009f0ca..98ef53418 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -1,497 +1,497 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000045 # Number of seconds simulated -sim_ticks 44698500 # Number of ticks simulated -final_tick 44698500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 357665 # Simulator instruction rate (inst/s) -host_op_rate 357507 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1053539740 # Simulator tick rate (ticks/s) -host_mem_usage 250236 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -sim_insts 15162 # Number of instructions simulated -sim_ops 15162 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory -system.physmem.bytes_read::total 26624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory -system.physmem.num_reads::total 416 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 398044677 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 197590523 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 595635200 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 398044677 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 398044677 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 398044677 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 197590523 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 595635200 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.numSyscalls 18 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 44698500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 89397 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 15162 # Number of instructions committed -system.cpu.committedOps 15162 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 12219 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 385 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 2434 # number of instructions that are conditional controls -system.cpu.num_int_insts 12219 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 29037 # number of times the integer registers were read -system.cpu.num_int_register_writes 13818 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 3683 # number of memory refs -system.cpu.num_load_insts 2231 # Number of load instructions -system.cpu.num_store_insts 1452 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 89396.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 3363 # Number of branches fetched -system.cpu.op_class::No_OpClass 726 4.77% 4.77% # Class of executed instruction -system.cpu.op_class::IntAlu 10798 71.01% 75.78% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::MemRead 2231 14.67% 90.45% # Class of executed instruction -system.cpu.op_class::MemWrite 1452 9.55% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 15207 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 97.037351 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 97.037351 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.023691 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.023691 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 7484 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 7484 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1357 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits -system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 3529 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 3529 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 3529 # number of overall hits -system.cpu.dcache.overall_hits::total 3529 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 53 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 53 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses -system.cpu.dcache.overall_misses::total 138 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3339000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3339000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5355000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5355000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 8694000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8694000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 8694000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8694000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 3667 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 3667 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 3667 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023820 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.023820 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.058946 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.058946 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3286000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3286000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5270000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5270000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8556000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8556000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8556000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8556000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 151.480746 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 151.480746 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.073965 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.073965 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 280 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 235 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.136719 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 30696 # Number of tag accesses -system.cpu.icache.tags.data_accesses 30696 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 14928 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14928 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14928 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14928 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14928 # number of overall hits -system.cpu.icache.overall_hits::total 14928 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 280 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 280 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 280 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 280 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 280 # number of overall misses -system.cpu.icache.overall_misses::total 280 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17542500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17542500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17542500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17542500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17542500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17542500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 15208 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 15208 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 15208 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 15208 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 15208 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 15208 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.018411 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.018411 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.018411 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.018411 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.018411 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.018411 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62651.785714 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 62651.785714 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 62651.785714 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 62651.785714 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 62651.785714 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 62651.785714 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 280 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 280 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 280 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17262500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17262500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17262500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17262500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17262500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17262500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.018411 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.018411 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.018411 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61651.785714 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61651.785714 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61651.785714 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 61651.785714 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61651.785714 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 61651.785714 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 247.870917 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 416 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.004808 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 150.801148 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 97.069768 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004602 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002962 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.007564 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 416 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012695 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3760 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3760 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits -system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 85 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 85 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 278 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 278 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 53 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 53 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 416 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses -system.cpu.l2cache.overall_misses::total 416 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5142500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5142500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16819500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 16819500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3206500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 3206500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16819500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8349000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 25168500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16819500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8349000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 25168500 # number of overall miss cycles -system.cpu.l2cache.ReadExReq_accesses::cpu.data 85 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 85 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 280 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 280 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 53 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 280 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 418 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 280 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 418 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.992857 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.992857 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992857 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.995215 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992857 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.995215 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60501.798561 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60501.798561 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60501.798561 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60501.201923 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60501.798561 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60501.201923 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 85 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 85 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 278 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 278 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 53 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 53 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 416 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 416 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4292500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4292500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14039500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14039500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2676500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2676500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14039500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6969000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 21008500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14039500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6969000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 21008500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.992857 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.995215 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.995215 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.798561 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.798561 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.798561 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.201923 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.798561 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.201923 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 280 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 53 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 560 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.004785 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.069088 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 416 99.52% 99.52% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2 0.48% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 420000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 416 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 331 # Transaction distribution -system.membus.trans_dist::ReadExReq 85 # Transaction distribution -system.membus.trans_dist::ReadExResp 85 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 331 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 416 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 416 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 416 # Request fanout histogram -system.membus.reqLayer0.occupancy 416500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2080000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 4.7 # Layer utilization (%) +sim_seconds 0.000045 +sim_ticks 44698500 +final_tick 44698500 +sim_freq 1000000000000 +host_inst_rate 251543 +host_op_rate 251424 +host_tick_rate 740962061 +host_mem_usage 261496 +host_seconds 0.06 +sim_insts 15162 +sim_ops 15162 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 44698500 +system.physmem.bytes_read::cpu.inst 17792 +system.physmem.bytes_read::cpu.data 8832 +system.physmem.bytes_read::total 26624 +system.physmem.bytes_inst_read::cpu.inst 17792 +system.physmem.bytes_inst_read::total 17792 +system.physmem.num_reads::cpu.inst 278 +system.physmem.num_reads::cpu.data 138 +system.physmem.num_reads::total 416 +system.physmem.bw_read::cpu.inst 398044677 +system.physmem.bw_read::cpu.data 197590523 +system.physmem.bw_read::total 595635200 +system.physmem.bw_inst_read::cpu.inst 398044677 +system.physmem.bw_inst_read::total 398044677 +system.physmem.bw_total::cpu.inst 398044677 +system.physmem.bw_total::cpu.data 197590523 +system.physmem.bw_total::total 595635200 +system.pwrStateResidencyTicks::UNDEFINED 44698500 +system.cpu_clk_domain.clock 500 +system.cpu.workload.numSyscalls 18 +system.cpu.pwrStateResidencyTicks::ON 44698500 +system.cpu.numCycles 89397 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 15162 +system.cpu.committedOps 15162 +system.cpu.num_int_alu_accesses 12219 +system.cpu.num_fp_alu_accesses 0 +system.cpu.num_func_calls 385 +system.cpu.num_conditional_control_insts 2434 +system.cpu.num_int_insts 12219 +system.cpu.num_fp_insts 0 +system.cpu.num_int_register_reads 29037 +system.cpu.num_int_register_writes 13818 +system.cpu.num_fp_register_reads 0 +system.cpu.num_fp_register_writes 0 +system.cpu.num_mem_refs 3683 +system.cpu.num_load_insts 2231 +system.cpu.num_store_insts 1452 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 89397 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 3363 +system.cpu.op_class::No_OpClass 726 4.77% 4.77% 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+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 +system.cpu.toL2Bus.pkt_count::total 836 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17920 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 +system.cpu.toL2Bus.pkt_size::total 26752 +system.cpu.toL2Bus.snoops 0 +system.cpu.toL2Bus.snoopTraffic 0 +system.cpu.toL2Bus.snoop_fanout::samples 418 +system.cpu.toL2Bus.snoop_fanout::mean 0.004785 +system.cpu.toL2Bus.snoop_fanout::stdev 0.069088 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 416 99.52% 99.52% +system.cpu.toL2Bus.snoop_fanout::1 2 0.48% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 1 +system.cpu.toL2Bus.snoop_fanout::total 418 +system.cpu.toL2Bus.reqLayer0.occupancy 209000 +system.cpu.toL2Bus.reqLayer0.utilization 0.5 +system.cpu.toL2Bus.respLayer0.occupancy 420000 +system.cpu.toL2Bus.respLayer0.utilization 0.9 +system.cpu.toL2Bus.respLayer1.occupancy 207000 +system.cpu.toL2Bus.respLayer1.utilization 0.5 +system.membus.snoop_filter.tot_requests 416 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 44698500 +system.membus.trans_dist::ReadResp 331 +system.membus.trans_dist::ReadExReq 85 +system.membus.trans_dist::ReadExResp 85 +system.membus.trans_dist::ReadSharedReq 331 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 +system.membus.pkt_count::total 832 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 +system.membus.pkt_size::total 26624 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 416 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 416 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 416 +system.membus.reqLayer0.occupancy 416500 +system.membus.reqLayer0.utilization 0.9 +system.membus.respLayer1.occupancy 2080000 +system.membus.respLayer1.utilization 4.7 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini index 2d26791e9..34c898798 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini @@ -93,6 +93,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -166,8 +167,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -178,8 +177,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -239,7 +236,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=tests/test-progs/hello/bin/arm/linux/hello cwd= drivers= @@ -252,10 +249,11 @@ executable= gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simerr b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simerr index 2f9507495..1cfcb3e18 100755 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simerr +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simerr @@ -1,3 +1,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simout index 40266a5d8..01bb29eda 100755 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simout +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/le gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 21:05:23 -gem5 executing on e108600-lin, pid 17594 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 18:05:51 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 55329 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple Global frequency set at 1000000000000 ticks per second Beginning simulation! -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 372284000 because target called exit() +Exiting @ tick 372284000 because exiting with last active thread context diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt index d96e2fe55..bf625223f 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt @@ -1,510 +1,510 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000372 # Number of seconds simulated -sim_ticks 372284000 # Number of ticks simulated -final_tick 372284000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 264702 # Simulator instruction rate (inst/s) -host_op_rate 305997 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 19731375693 # Simulator tick rate (ticks/s) -host_mem_usage 650740 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -sim_insts 4988 # Number of instructions simulated -sim_ops 5770 # Number of ops (including micro ops) simulated -system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 372284000 # Cumulative time (in ticks) in various power states -system.mem_ctrl.bytes_read::cpu.inst 20108 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::cpu.data 4672 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::total 24780 # Number of bytes read from this memory -system.mem_ctrl.bytes_inst_read::cpu.inst 20108 # Number of instructions bytes read from this memory -system.mem_ctrl.bytes_inst_read::total 20108 # Number of instructions bytes read from this memory -system.mem_ctrl.bytes_written::cpu.data 3696 # Number of bytes written to this memory -system.mem_ctrl.bytes_written::total 3696 # Number of bytes written to this memory -system.mem_ctrl.num_reads::cpu.inst 5027 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::cpu.data 1061 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::total 6088 # Number of read requests responded to by this memory -system.mem_ctrl.num_writes::cpu.data 936 # Number of write requests responded to by this memory -system.mem_ctrl.num_writes::total 936 # Number of write requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 54012528 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 12549559 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 66562087 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 54012528 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 54012528 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::cpu.data 9927905 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::total 9927905 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 54012528 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 22477463 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 76489992 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.readReqs 6089 # Number of read requests accepted -system.mem_ctrl.writeReqs 936 # Number of write requests accepted -system.mem_ctrl.readBursts 6089 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrl.writeBursts 936 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 383296 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 6400 # Total number of bytes read from write queue -system.mem_ctrl.bytesWritten 4096 # Total number of bytes written to DRAM -system.mem_ctrl.bytesReadSys 24784 # Total read bytes from the system interface side -system.mem_ctrl.bytesWrittenSys 3696 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 100 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 855 # Number of DRAM write bursts merged with an existing one -system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrl.perBankRdBursts::0 911 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::1 1454 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::2 724 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::3 364 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::4 505 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::5 303 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::6 487 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::7 206 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::8 42 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::9 155 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::10 192 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::11 422 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::12 108 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::13 36 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::14 0 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::15 80 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::10 13 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::11 46 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::12 5 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts -system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 372207000 # Total gap between requests -system.mem_ctrl.readPktSize::0 70 # Read request sizes (log2) -system.mem_ctrl.readPktSize::1 1 # Read request sizes (log2) -system.mem_ctrl.readPktSize::2 5858 # Read request sizes (log2) -system.mem_ctrl.readPktSize::3 160 # Read request sizes (log2) -system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::6 0 # Read request sizes (log2) -system.mem_ctrl.writePktSize::0 16 # Write request sizes (log2) -system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::2 920 # Write request sizes (log2) -system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 5980 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::1 9 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see 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see -system.mem_ctrl.wrQLenPdf::18 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::19 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::20 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::21 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::22 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::23 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::24 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::25 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::26 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::27 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::28 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::29 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::30 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::31 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::32 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 514 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 749.322957 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 608.037375 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 344.826867 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 25 4.86% 4.86% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 42 8.17% 13.04% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 44 8.56% 21.60% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 26 5.06% 26.65% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 25 4.86% 31.52% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 34 6.61% 38.13% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 27 5.25% 43.39% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 27 5.25% 48.64% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 264 51.36% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 514 # Bytes accessed per row activation -system.mem_ctrl.rdPerTurnAround::samples 4 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::mean 1490.500000 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::gmean 1373.591360 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::stdev 606.712727 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::640-767 1 25.00% 25.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1408-1535 1 25.00% 50.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1792-1919 1 25.00% 75.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::2048-2175 1 25.00% 100.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::total 4 # Reads before turning the bus around for writes -system.mem_ctrl.wrPerTurnAround::samples 4 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::16 4 100.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::total 4 # Writes before turning the bus around for reads -system.mem_ctrl.totQLat 57609500 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 169903250 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 29945000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 9619.22 # Average queueing delay per DRAM burst -system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 28369.22 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 1029.58 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 11.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 66.57 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 9.93 # Average system write bandwidth in MiByte/s -system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 8.13 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 8.04 # Data bus utilization in percentage for reads -system.mem_ctrl.busUtilWrite 0.09 # Data bus utilization in percentage for writes -system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 24.94 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 5473 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 62 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 91.38 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate 76.54 # Row buffer hit rate for writes -system.mem_ctrl.avgGap 52983.20 # Average gap between requests -system.mem_ctrl.pageHitRate 91.19 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 2727480 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 1438305 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 35364420 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 28888080.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 64999380 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 1619520 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.actPowerDownEnergy 98643060 # Energy for active power-down per rank (pJ) -system.mem_ctrl_0.prePowerDownEnergy 3533760 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrl_0.totalEnergy 237214005 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 637.183891 # Core power per rank (mW) -system.mem_ctrl_0.totalIdleTime 225396250 # Total Idle time Per DRAM Rank -system.mem_ctrl_0.memoryStateTime::IDLE 954000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 12220000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 9196500 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 133713750 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 216199750 # Time in different power states -system.mem_ctrl_1.actEnergy 971040 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 512325 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 7389900 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 334080 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 27658800.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 18607080 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 791520 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.actPowerDownEnergy 128152530 # Energy for active power-down per rank (pJ) -system.mem_ctrl_1.prePowerDownEnergy 7837920 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_1.selfRefreshEnergy 7265340 # Energy for self refresh per rank (pJ) -system.mem_ctrl_1.totalEnergy 199520535 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 535.934929 # Core power per rank (mW) -system.mem_ctrl_1.totalIdleTime 328663750 # Total Idle time Per DRAM Rank -system.mem_ctrl_1.memoryStateTime::IDLE 770000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 11706000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::SREF 27971000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 20415250 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 30385000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 281036750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 372284000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 372284000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 372284000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 372284000 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 372284000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 372284000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 372284 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 4988 # Number of instructions committed -system.cpu.committedOps 5770 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4977 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses -system.cpu.num_func_calls 215 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 800 # number of instructions that are conditional controls -system.cpu.num_int_insts 4977 # number of integer instructions -system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 8049 # number of times the integer registers were read -system.cpu.num_int_register_writes 2992 # number of times the integer registers were written -system.cpu.num_fp_register_reads 16 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 20681 # number of times the CC registers were read -system.cpu.num_cc_register_writes 2647 # number of times the CC registers were written -system.cpu.num_mem_refs 2035 # number of memory refs -system.cpu.num_load_insts 1085 # Number of load instructions -system.cpu.num_store_insts 950 # Number of store instructions -system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 372283.999000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1107 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 3789 64.98% 64.98% # Class of executed instruction -system.cpu.op_class::IntMult 4 0.07% 65.05% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.05% 65.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 65.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.10% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.10% # Class of executed instruction -system.cpu.op_class::MemRead 1085 18.61% 83.71% # Class of executed instruction -system.cpu.op_class::MemWrite 934 16.02% 99.73% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 99.73% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 16 0.27% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5831 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 372284000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 6078 # Transaction distribution -system.membus.trans_dist::ReadResp 6088 # Transaction distribution -system.membus.trans_dist::WriteReq 925 # Transaction distribution -system.membus.trans_dist::WriteResp 925 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution -system.membus.trans_dist::StoreCondReq 11 # Transaction distribution -system.membus.trans_dist::StoreCondResp 11 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 10055 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 3994 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14049 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 20108 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 8368 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 28476 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 7025 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7025 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7025 # Request fanout histogram -system.membus.reqLayer0.occupancy 7961000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.membus.respLayer0.occupancy 11413250 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3327250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.9 # Layer utilization (%) +sim_seconds 0.000372 +sim_ticks 372284000 +final_tick 372284000 +sim_freq 1000000000000 +host_inst_rate 111411 +host_op_rate 128815 +host_tick_rate 8307715104 +host_mem_usage 662496 +host_seconds 0.05 +sim_insts 4988 +sim_ops 5770 +system.clk_domain.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 372284000 +system.mem_ctrl.bytes_read::cpu.inst 20108 +system.mem_ctrl.bytes_read::cpu.data 4672 +system.mem_ctrl.bytes_read::total 24780 +system.mem_ctrl.bytes_inst_read::cpu.inst 20108 +system.mem_ctrl.bytes_inst_read::total 20108 +system.mem_ctrl.bytes_written::cpu.data 3696 +system.mem_ctrl.bytes_written::total 3696 +system.mem_ctrl.num_reads::cpu.inst 5027 +system.mem_ctrl.num_reads::cpu.data 1061 +system.mem_ctrl.num_reads::total 6088 +system.mem_ctrl.num_writes::cpu.data 936 +system.mem_ctrl.num_writes::total 936 +system.mem_ctrl.bw_read::cpu.inst 54012528 +system.mem_ctrl.bw_read::cpu.data 12549559 +system.mem_ctrl.bw_read::total 66562087 +system.mem_ctrl.bw_inst_read::cpu.inst 54012528 +system.mem_ctrl.bw_inst_read::total 54012528 +system.mem_ctrl.bw_write::cpu.data 9927905 +system.mem_ctrl.bw_write::total 9927905 +system.mem_ctrl.bw_total::cpu.inst 54012528 +system.mem_ctrl.bw_total::cpu.data 22477463 +system.mem_ctrl.bw_total::total 76489992 +system.mem_ctrl.readReqs 6089 +system.mem_ctrl.writeReqs 936 +system.mem_ctrl.readBursts 6089 +system.mem_ctrl.writeBursts 936 +system.mem_ctrl.bytesReadDRAM 383296 +system.mem_ctrl.bytesReadWrQ 6400 +system.mem_ctrl.bytesWritten 4096 +system.mem_ctrl.bytesReadSys 24784 +system.mem_ctrl.bytesWrittenSys 3696 +system.mem_ctrl.servicedByWrQ 100 +system.mem_ctrl.mergedWrBursts 855 +system.mem_ctrl.neitherReadNorWriteReqs 0 +system.mem_ctrl.perBankRdBursts::0 911 +system.mem_ctrl.perBankRdBursts::1 1454 +system.mem_ctrl.perBankRdBursts::2 724 +system.mem_ctrl.perBankRdBursts::3 364 +system.mem_ctrl.perBankRdBursts::4 505 +system.mem_ctrl.perBankRdBursts::5 303 +system.mem_ctrl.perBankRdBursts::6 487 +system.mem_ctrl.perBankRdBursts::7 206 +system.mem_ctrl.perBankRdBursts::8 42 +system.mem_ctrl.perBankRdBursts::9 155 +system.mem_ctrl.perBankRdBursts::10 192 +system.mem_ctrl.perBankRdBursts::11 422 +system.mem_ctrl.perBankRdBursts::12 108 +system.mem_ctrl.perBankRdBursts::13 36 +system.mem_ctrl.perBankRdBursts::14 0 +system.mem_ctrl.perBankRdBursts::15 80 +system.mem_ctrl.perBankWrBursts::0 0 +system.mem_ctrl.perBankWrBursts::1 0 +system.mem_ctrl.perBankWrBursts::2 0 +system.mem_ctrl.perBankWrBursts::3 0 +system.mem_ctrl.perBankWrBursts::4 0 +system.mem_ctrl.perBankWrBursts::5 0 +system.mem_ctrl.perBankWrBursts::6 0 +system.mem_ctrl.perBankWrBursts::7 0 +system.mem_ctrl.perBankWrBursts::8 0 +system.mem_ctrl.perBankWrBursts::9 0 +system.mem_ctrl.perBankWrBursts::10 13 +system.mem_ctrl.perBankWrBursts::11 46 +system.mem_ctrl.perBankWrBursts::12 5 +system.mem_ctrl.perBankWrBursts::13 0 +system.mem_ctrl.perBankWrBursts::14 0 +system.mem_ctrl.perBankWrBursts::15 0 +system.mem_ctrl.numRdRetry 0 +system.mem_ctrl.numWrRetry 0 +system.mem_ctrl.totGap 372207000 +system.mem_ctrl.readPktSize::0 70 +system.mem_ctrl.readPktSize::1 1 +system.mem_ctrl.readPktSize::2 5858 +system.mem_ctrl.readPktSize::3 160 +system.mem_ctrl.readPktSize::4 0 +system.mem_ctrl.readPktSize::5 0 +system.mem_ctrl.readPktSize::6 0 +system.mem_ctrl.writePktSize::0 16 +system.mem_ctrl.writePktSize::1 0 +system.mem_ctrl.writePktSize::2 920 +system.mem_ctrl.writePktSize::3 0 +system.mem_ctrl.writePktSize::4 0 +system.mem_ctrl.writePktSize::5 0 +system.mem_ctrl.writePktSize::6 0 +system.mem_ctrl.rdQLenPdf::0 5980 +system.mem_ctrl.rdQLenPdf::1 9 +system.mem_ctrl.rdQLenPdf::2 0 +system.mem_ctrl.rdQLenPdf::3 0 +system.mem_ctrl.rdQLenPdf::4 0 +system.mem_ctrl.rdQLenPdf::5 0 +system.mem_ctrl.rdQLenPdf::6 0 +system.mem_ctrl.rdQLenPdf::7 0 +system.mem_ctrl.rdQLenPdf::8 0 +system.mem_ctrl.rdQLenPdf::9 0 +system.mem_ctrl.rdQLenPdf::10 0 +system.mem_ctrl.rdQLenPdf::11 0 +system.mem_ctrl.rdQLenPdf::12 0 +system.mem_ctrl.rdQLenPdf::13 0 +system.mem_ctrl.rdQLenPdf::14 0 +system.mem_ctrl.rdQLenPdf::15 0 +system.mem_ctrl.rdQLenPdf::16 0 +system.mem_ctrl.rdQLenPdf::17 0 +system.mem_ctrl.rdQLenPdf::18 0 +system.mem_ctrl.rdQLenPdf::19 0 +system.mem_ctrl.rdQLenPdf::20 0 +system.mem_ctrl.rdQLenPdf::21 0 +system.mem_ctrl.rdQLenPdf::22 0 +system.mem_ctrl.rdQLenPdf::23 0 +system.mem_ctrl.rdQLenPdf::24 0 +system.mem_ctrl.rdQLenPdf::25 0 +system.mem_ctrl.rdQLenPdf::26 0 +system.mem_ctrl.rdQLenPdf::27 0 +system.mem_ctrl.rdQLenPdf::28 0 +system.mem_ctrl.rdQLenPdf::29 0 +system.mem_ctrl.rdQLenPdf::30 0 +system.mem_ctrl.rdQLenPdf::31 0 +system.mem_ctrl.wrQLenPdf::0 1 +system.mem_ctrl.wrQLenPdf::1 1 +system.mem_ctrl.wrQLenPdf::2 1 +system.mem_ctrl.wrQLenPdf::3 1 +system.mem_ctrl.wrQLenPdf::4 1 +system.mem_ctrl.wrQLenPdf::5 1 +system.mem_ctrl.wrQLenPdf::6 1 +system.mem_ctrl.wrQLenPdf::7 1 +system.mem_ctrl.wrQLenPdf::8 1 +system.mem_ctrl.wrQLenPdf::9 1 +system.mem_ctrl.wrQLenPdf::10 1 +system.mem_ctrl.wrQLenPdf::11 1 +system.mem_ctrl.wrQLenPdf::12 1 +system.mem_ctrl.wrQLenPdf::13 1 +system.mem_ctrl.wrQLenPdf::14 1 +system.mem_ctrl.wrQLenPdf::15 1 +system.mem_ctrl.wrQLenPdf::16 1 +system.mem_ctrl.wrQLenPdf::17 4 +system.mem_ctrl.wrQLenPdf::18 4 +system.mem_ctrl.wrQLenPdf::19 4 +system.mem_ctrl.wrQLenPdf::20 4 +system.mem_ctrl.wrQLenPdf::21 4 +system.mem_ctrl.wrQLenPdf::22 4 +system.mem_ctrl.wrQLenPdf::23 4 +system.mem_ctrl.wrQLenPdf::24 4 +system.mem_ctrl.wrQLenPdf::25 4 +system.mem_ctrl.wrQLenPdf::26 4 +system.mem_ctrl.wrQLenPdf::27 4 +system.mem_ctrl.wrQLenPdf::28 4 +system.mem_ctrl.wrQLenPdf::29 4 +system.mem_ctrl.wrQLenPdf::30 4 +system.mem_ctrl.wrQLenPdf::31 4 +system.mem_ctrl.wrQLenPdf::32 4 +system.mem_ctrl.wrQLenPdf::33 0 +system.mem_ctrl.wrQLenPdf::34 0 +system.mem_ctrl.wrQLenPdf::35 0 +system.mem_ctrl.wrQLenPdf::36 0 +system.mem_ctrl.wrQLenPdf::37 0 +system.mem_ctrl.wrQLenPdf::38 0 +system.mem_ctrl.wrQLenPdf::39 0 +system.mem_ctrl.wrQLenPdf::40 0 +system.mem_ctrl.wrQLenPdf::41 0 +system.mem_ctrl.wrQLenPdf::42 0 +system.mem_ctrl.wrQLenPdf::43 0 +system.mem_ctrl.wrQLenPdf::44 0 +system.mem_ctrl.wrQLenPdf::45 0 +system.mem_ctrl.wrQLenPdf::46 0 +system.mem_ctrl.wrQLenPdf::47 0 +system.mem_ctrl.wrQLenPdf::48 0 +system.mem_ctrl.wrQLenPdf::49 0 +system.mem_ctrl.wrQLenPdf::50 0 +system.mem_ctrl.wrQLenPdf::51 0 +system.mem_ctrl.wrQLenPdf::52 0 +system.mem_ctrl.wrQLenPdf::53 0 +system.mem_ctrl.wrQLenPdf::54 0 +system.mem_ctrl.wrQLenPdf::55 0 +system.mem_ctrl.wrQLenPdf::56 0 +system.mem_ctrl.wrQLenPdf::57 0 +system.mem_ctrl.wrQLenPdf::58 0 +system.mem_ctrl.wrQLenPdf::59 0 +system.mem_ctrl.wrQLenPdf::60 0 +system.mem_ctrl.wrQLenPdf::61 0 +system.mem_ctrl.wrQLenPdf::62 0 +system.mem_ctrl.wrQLenPdf::63 0 +system.mem_ctrl.bytesPerActivate::samples 514 +system.mem_ctrl.bytesPerActivate::mean 749.322957 +system.mem_ctrl.bytesPerActivate::gmean 608.037375 +system.mem_ctrl.bytesPerActivate::stdev 344.826867 +system.mem_ctrl.bytesPerActivate::0-127 25 4.86% 4.86% +system.mem_ctrl.bytesPerActivate::128-255 42 8.17% 13.04% +system.mem_ctrl.bytesPerActivate::256-383 44 8.56% 21.60% +system.mem_ctrl.bytesPerActivate::384-511 26 5.06% 26.65% +system.mem_ctrl.bytesPerActivate::512-639 25 4.86% 31.52% +system.mem_ctrl.bytesPerActivate::640-767 34 6.61% 38.13% +system.mem_ctrl.bytesPerActivate::768-895 27 5.25% 43.39% +system.mem_ctrl.bytesPerActivate::896-1023 27 5.25% 48.64% +system.mem_ctrl.bytesPerActivate::1024-1151 264 51.36% 100.00% +system.mem_ctrl.bytesPerActivate::total 514 +system.mem_ctrl.rdPerTurnAround::samples 4 +system.mem_ctrl.rdPerTurnAround::mean 1490.500000 +system.mem_ctrl.rdPerTurnAround::gmean 1373.591360 +system.mem_ctrl.rdPerTurnAround::stdev 606.712727 +system.mem_ctrl.rdPerTurnAround::640-767 1 25.00% 25.00% +system.mem_ctrl.rdPerTurnAround::1408-1535 1 25.00% 50.00% +system.mem_ctrl.rdPerTurnAround::1792-1919 1 25.00% 75.00% +system.mem_ctrl.rdPerTurnAround::2048-2175 1 25.00% 100.00% +system.mem_ctrl.rdPerTurnAround::total 4 +system.mem_ctrl.wrPerTurnAround::samples 4 +system.mem_ctrl.wrPerTurnAround::mean 16 +system.mem_ctrl.wrPerTurnAround::gmean 16.000000 +system.mem_ctrl.wrPerTurnAround::16 4 100.00% 100.00% +system.mem_ctrl.wrPerTurnAround::total 4 +system.mem_ctrl.totQLat 57609500 +system.mem_ctrl.totMemAccLat 169903250 +system.mem_ctrl.totBusLat 29945000 +system.mem_ctrl.avgQLat 9619.22 +system.mem_ctrl.avgBusLat 5000.00 +system.mem_ctrl.avgMemAccLat 28369.22 +system.mem_ctrl.avgRdBW 1029.58 +system.mem_ctrl.avgWrBW 11.00 +system.mem_ctrl.avgRdBWSys 66.57 +system.mem_ctrl.avgWrBWSys 9.93 +system.mem_ctrl.peakBW 12800.00 +system.mem_ctrl.busUtil 8.13 +system.mem_ctrl.busUtilRead 8.04 +system.mem_ctrl.busUtilWrite 0.09 +system.mem_ctrl.avgRdQLen 1.00 +system.mem_ctrl.avgWrQLen 24.94 +system.mem_ctrl.readRowHits 5473 +system.mem_ctrl.writeRowHits 62 +system.mem_ctrl.readRowHitRate 91.38 +system.mem_ctrl.writeRowHitRate 76.54 +system.mem_ctrl.avgGap 52983.20 +system.mem_ctrl.pageHitRate 91.19 +system.mem_ctrl_0.actEnergy 2727480 +system.mem_ctrl_0.preEnergy 1438305 +system.mem_ctrl_0.readEnergy 35364420 +system.mem_ctrl_0.writeEnergy 0 +system.mem_ctrl_0.refreshEnergy 28888080.000000 +system.mem_ctrl_0.actBackEnergy 64999380 +system.mem_ctrl_0.preBackEnergy 1619520 +system.mem_ctrl_0.actPowerDownEnergy 98643060 +system.mem_ctrl_0.prePowerDownEnergy 3533760 +system.mem_ctrl_0.selfRefreshEnergy 0 +system.mem_ctrl_0.totalEnergy 237214005 +system.mem_ctrl_0.averagePower 637.183891 +system.mem_ctrl_0.totalIdleTime 225396250 +system.mem_ctrl_0.memoryStateTime::IDLE 954000 +system.mem_ctrl_0.memoryStateTime::REF 12220000 +system.mem_ctrl_0.memoryStateTime::SREF 0 +system.mem_ctrl_0.memoryStateTime::PRE_PDN 9196500 +system.mem_ctrl_0.memoryStateTime::ACT 133713750 +system.mem_ctrl_0.memoryStateTime::ACT_PDN 216199750 +system.mem_ctrl_1.actEnergy 971040 +system.mem_ctrl_1.preEnergy 512325 +system.mem_ctrl_1.readEnergy 7389900 +system.mem_ctrl_1.writeEnergy 334080 +system.mem_ctrl_1.refreshEnergy 27658800.000000 +system.mem_ctrl_1.actBackEnergy 18607080 +system.mem_ctrl_1.preBackEnergy 791520 +system.mem_ctrl_1.actPowerDownEnergy 128152530 +system.mem_ctrl_1.prePowerDownEnergy 7837920 +system.mem_ctrl_1.selfRefreshEnergy 7265340 +system.mem_ctrl_1.totalEnergy 199520535 +system.mem_ctrl_1.averagePower 535.934929 +system.mem_ctrl_1.totalIdleTime 328663750 +system.mem_ctrl_1.memoryStateTime::IDLE 770000 +system.mem_ctrl_1.memoryStateTime::REF 11706000 +system.mem_ctrl_1.memoryStateTime::SREF 27971000 +system.mem_ctrl_1.memoryStateTime::PRE_PDN 20415250 +system.mem_ctrl_1.memoryStateTime::ACT 30385000 +system.mem_ctrl_1.memoryStateTime::ACT_PDN 281036750 +system.pwrStateResidencyTicks::UNDEFINED 372284000 +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 372284000 +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.hits 0 +system.cpu.dstage2_mmu.stage2_tlb.misses 0 +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 372284000 +system.cpu.dtb.walker.walks 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dtb.walker.walkRequestOrigin::total 0 +system.cpu.dtb.inst_hits 0 +system.cpu.dtb.inst_misses 0 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.flush_tlb 0 +system.cpu.dtb.flush_tlb_mva 0 +system.cpu.dtb.flush_tlb_mva_asid 0 +system.cpu.dtb.flush_tlb_asid 0 +system.cpu.dtb.flush_entries 0 +system.cpu.dtb.align_faults 0 +system.cpu.dtb.prefetch_faults 0 +system.cpu.dtb.domain_faults 0 +system.cpu.dtb.perms_faults 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.inst_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 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+system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.hits 0 +system.cpu.istage2_mmu.stage2_tlb.misses 0 +system.cpu.istage2_mmu.stage2_tlb.accesses 0 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 372284000 +system.cpu.itb.walker.walks 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.itb.walker.walkRequestOrigin::total 0 +system.cpu.itb.inst_hits 0 +system.cpu.itb.inst_misses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.flush_tlb 0 +system.cpu.itb.flush_tlb_mva 0 +system.cpu.itb.flush_tlb_mva_asid 0 +system.cpu.itb.flush_tlb_asid 0 +system.cpu.itb.flush_entries 0 +system.cpu.itb.align_faults 0 +system.cpu.itb.prefetch_faults 0 +system.cpu.itb.domain_faults 0 +system.cpu.itb.perms_faults 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.inst_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 13 +system.cpu.pwrStateResidencyTicks::ON 372284000 +system.cpu.numCycles 372284 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 4988 +system.cpu.committedOps 5770 +system.cpu.num_int_alu_accesses 4977 +system.cpu.num_fp_alu_accesses 16 +system.cpu.num_func_calls 215 +system.cpu.num_conditional_control_insts 800 +system.cpu.num_int_insts 4977 +system.cpu.num_fp_insts 16 +system.cpu.num_int_register_reads 8049 +system.cpu.num_int_register_writes 2992 +system.cpu.num_fp_register_reads 16 +system.cpu.num_fp_register_writes 0 +system.cpu.num_cc_register_reads 20681 +system.cpu.num_cc_register_writes 2647 +system.cpu.num_mem_refs 2035 +system.cpu.num_load_insts 1085 +system.cpu.num_store_insts 950 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 372284 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 1107 +system.cpu.op_class::No_OpClass 0 0.00% 0.00% +system.cpu.op_class::IntAlu 3789 64.98% 64.98% +system.cpu.op_class::IntMult 4 0.07% 65.05% +system.cpu.op_class::IntDiv 0 0.00% 65.05% +system.cpu.op_class::FloatAdd 0 0.00% 65.05% +system.cpu.op_class::FloatCmp 0 0.00% 65.05% +system.cpu.op_class::FloatCvt 0 0.00% 65.05% +system.cpu.op_class::FloatMult 0 0.00% 65.05% +system.cpu.op_class::FloatMultAcc 0 0.00% 65.05% +system.cpu.op_class::FloatDiv 0 0.00% 65.05% +system.cpu.op_class::FloatMisc 0 0.00% 65.05% +system.cpu.op_class::FloatSqrt 0 0.00% 65.05% +system.cpu.op_class::SimdAdd 0 0.00% 65.05% +system.cpu.op_class::SimdAddAcc 0 0.00% 65.05% +system.cpu.op_class::SimdAlu 0 0.00% 65.05% +system.cpu.op_class::SimdCmp 0 0.00% 65.05% +system.cpu.op_class::SimdCvt 0 0.00% 65.05% +system.cpu.op_class::SimdMisc 0 0.00% 65.05% +system.cpu.op_class::SimdMult 0 0.00% 65.05% +system.cpu.op_class::SimdMultAcc 0 0.00% 65.05% +system.cpu.op_class::SimdShift 0 0.00% 65.05% +system.cpu.op_class::SimdShiftAcc 0 0.00% 65.05% +system.cpu.op_class::SimdSqrt 0 0.00% 65.05% +system.cpu.op_class::SimdFloatAdd 0 0.00% 65.05% +system.cpu.op_class::SimdFloatAlu 0 0.00% 65.05% +system.cpu.op_class::SimdFloatCmp 0 0.00% 65.05% +system.cpu.op_class::SimdFloatCvt 0 0.00% 65.05% +system.cpu.op_class::SimdFloatDiv 0 0.00% 65.05% +system.cpu.op_class::SimdFloatMisc 3 0.05% 65.10% +system.cpu.op_class::SimdFloatMult 0 0.00% 65.10% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.10% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.10% +system.cpu.op_class::MemRead 1085 18.61% 83.71% +system.cpu.op_class::MemWrite 934 16.02% 99.73% +system.cpu.op_class::FloatMemRead 0 0.00% 99.73% +system.cpu.op_class::FloatMemWrite 16 0.27% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 5831 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 372284000 +system.membus.trans_dist::ReadReq 6078 +system.membus.trans_dist::ReadResp 6088 +system.membus.trans_dist::WriteReq 925 +system.membus.trans_dist::WriteResp 925 +system.membus.trans_dist::LoadLockedReq 11 +system.membus.trans_dist::StoreCondReq 11 +system.membus.trans_dist::StoreCondResp 11 +system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 10055 +system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 3994 +system.membus.pkt_count::total 14049 +system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 20108 +system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 8368 +system.membus.pkt_size::total 28476 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 7025 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 7025 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 7025 +system.membus.reqLayer0.occupancy 7961000 +system.membus.reqLayer0.utilization 2.1 +system.membus.respLayer0.occupancy 11413250 +system.membus.respLayer0.utilization 3.1 +system.membus.respLayer1.occupancy 3327250 +system.membus.respLayer1.utilization 0.9 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini index 733323a88..df4988eaf 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini @@ -93,6 +93,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -106,10 +107,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -123,6 +124,7 @@ response_latency=2 sequential_access=false size=65536 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -135,15 +137,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=65536 +tag_latency=2 [system.cpu.dstage2_mmu] type=ArmStage2MMU @@ -202,10 +205,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -219,6 +222,7 @@ response_latency=2 sequential_access=false size=16384 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -231,15 +235,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=16384 +tag_latency=2 [system.cpu.interrupts] type=ArmInterrupts @@ -258,8 +263,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -270,8 +273,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -331,7 +332,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=tests/test-progs/hello/bin/arm/linux/hello cwd= drivers= @@ -344,10 +345,11 @@ executable= gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -397,10 +399,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -414,6 +416,7 @@ response_latency=20 sequential_access=false size=262144 system=system +tag_latency=20 tags=system.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -426,15 +429,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=20 [system.mem_ctrl] type=DRAMCtrl diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simerr b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simerr index 2f9507495..1cfcb3e18 100755 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simerr +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simerr @@ -1,3 +1,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout index 7a7d67b77..00615c5ed 100755 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/le gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 21:05:17 -gem5 executing on e108600-lin, pid 17589 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 18:08:19 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 55755 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level Global frequency set at 1000000000000 ticks per second Beginning simulation! -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 52453000 because target called exit() +Exiting @ tick 52453000 because exiting with last active thread context diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt index 0bf6798da..67ec14819 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt @@ -1,846 +1,846 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000052 # Number of seconds simulated -sim_ticks 52453000 # Number of ticks simulated -final_tick 52453000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 494492 # Simulator instruction rate (inst/s) -host_op_rate 571324 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5188174566 # Simulator tick rate (ticks/s) -host_mem_usage 654324 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 4988 # Number of instructions simulated -sim_ops 5770 # Number of ops (including micro ops) simulated -system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.mem_ctrl.bytes_read::cpu.inst 14400 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::cpu.data 8064 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::total 22464 # Number of bytes read from this memory -system.mem_ctrl.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory -system.mem_ctrl.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory -system.mem_ctrl.num_reads::cpu.inst 225 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::cpu.data 126 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::total 351 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 274531485 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 153737632 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 428269117 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 274531485 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 274531485 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 274531485 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 153737632 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 428269117 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.readReqs 351 # Number of read requests accepted -system.mem_ctrl.writeReqs 0 # Number of write requests accepted -system.mem_ctrl.readBursts 351 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 22464 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue -system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM -system.mem_ctrl.bytesReadSys 22464 # Total read bytes from the system interface side -system.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrl.perBankRdBursts::0 78 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::1 42 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::2 13 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::3 33 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::4 14 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::5 31 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::6 34 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::7 9 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::8 4 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::9 6 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::10 25 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::11 43 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::12 8 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::13 5 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::14 0 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::15 6 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts -system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 52348000 # Total gap between requests -system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::6 351 # Read request sizes (log2) -system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 351 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 75 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 285.866667 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 188.503913 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 282.583704 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 22 29.33% 29.33% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 20 26.67% 56.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 15 20.00% 76.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 4 5.33% 81.33% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 4 5.33% 86.67% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 2 2.67% 89.33% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 2 2.67% 92.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 6 8.00% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 75 # Bytes accessed per row activation -system.mem_ctrl.totQLat 4720500 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 11301750 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 1755000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 13448.72 # Average queueing delay per DRAM burst -system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 32198.72 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 428.27 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 428.27 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 3.35 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 3.35 # Data bus utilization in percentage for reads -system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 270 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 76.92 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 149139.60 # Average gap between requests -system.mem_ctrl.pageHitRate 76.92 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 378420 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 189750 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 1813560 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 3687840.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 4500720 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 84480 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.actPowerDownEnergy 19212990 # Energy for active power-down per rank (pJ) -system.mem_ctrl_0.prePowerDownEnergy 88320 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrl_0.totalEnergy 29956080 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 571.095108 # Core power per rank (mW) -system.mem_ctrl_0.totalIdleTime 42304000 # Total Idle time Per DRAM Rank -system.mem_ctrl_0.memoryStateTime::IDLE 53000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 1560000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 229750 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 8478750 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 42131500 # Time in different power states -system.mem_ctrl_1.actEnergy 199920 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 94875 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 692580 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 3687840.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 2032620 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 139680 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.actPowerDownEnergy 19936320 # Energy for active power-down per rank (pJ) -system.mem_ctrl_1.prePowerDownEnergy 1502400 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrl_1.totalEnergy 28286235 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 539.260491 # Core power per rank (mW) -system.mem_ctrl_1.totalIdleTime 44784500 # Total Idle time Per DRAM Rank -system.mem_ctrl_1.memoryStateTime::IDLE 200000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 1560000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 3909750 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 3056250 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 43727000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 52453000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 52453 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 4988 # Number of instructions committed -system.cpu.committedOps 5770 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4977 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses -system.cpu.num_func_calls 215 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 800 # number of instructions that are conditional controls -system.cpu.num_int_insts 4977 # number of integer instructions -system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 8049 # number of times the integer registers were read -system.cpu.num_int_register_writes 2992 # number of times the integer registers were written -system.cpu.num_fp_register_reads 16 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 20681 # number of times the CC registers were read -system.cpu.num_cc_register_writes 2647 # number of times the CC registers were written -system.cpu.num_mem_refs 2035 # number of memory refs -system.cpu.num_load_insts 1085 # Number of load instructions -system.cpu.num_store_insts 950 # Number of store instructions -system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 52452.999000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1107 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 3789 64.98% 64.98% # Class of executed instruction -system.cpu.op_class::IntMult 4 0.07% 65.05% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 65.05% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.05% 65.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 65.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.10% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.10% # Class of executed instruction -system.cpu.op_class::MemRead 1085 18.61% 83.71% # Class of executed instruction -system.cpu.op_class::MemWrite 934 16.02% 99.73% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 99.73% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 16 0.27% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5831 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.380856 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1855 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.063380 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.380856 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.082403 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.082403 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.138672 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4136 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4136 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 951 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 951 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 882 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 882 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1833 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1833 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1833 # number of overall hits -system.cpu.dcache.overall_hits::total 1833 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 99 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 99 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 142 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 142 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 142 # number of overall misses -system.cpu.dcache.overall_misses::total 142 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9073000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9073000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4652000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4652000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13725000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13725000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13725000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13725000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1050 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1050 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1975 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1975 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1975 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1975 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.094286 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.094286 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046486 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.046486 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.071899 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.071899 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.071899 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.071899 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 91646.464646 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 91646.464646 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 108186.046512 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 108186.046512 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 96654.929577 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 96654.929577 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 96654.929577 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 96654.929577 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 99 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 99 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8875000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8875000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4566000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4566000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13441000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13441000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13441000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13441000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.094286 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.094286 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046486 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046486 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.071899 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.071899 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.071899 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.071899 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89646.464646 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89646.464646 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 106186.046512 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 106186.046512 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 94654.929577 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 94654.929577 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 94654.929577 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 94654.929577 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 70 # number of replacements -system.cpu.icache.tags.tagsinuse 96.586088 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 4779 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 249 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 19.192771 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 96.586088 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.377289 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.377289 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 179 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.699219 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 10305 # Number of tag accesses -system.cpu.icache.tags.data_accesses 10305 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 4779 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4779 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4779 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4779 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4779 # number of overall hits -system.cpu.icache.overall_hits::total 4779 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 249 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 249 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 249 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 249 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 249 # number of overall misses -system.cpu.icache.overall_misses::total 249 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25472000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25472000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25472000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25472000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25472000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25472000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5028 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5028 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5028 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5028 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5028 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5028 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.049523 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.049523 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.049523 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.049523 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.049523 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.049523 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 102297.188755 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 102297.188755 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 102297.188755 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 102297.188755 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 102297.188755 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 102297.188755 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 249 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 249 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 249 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 249 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24974000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24974000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24974000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24974000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24974000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24974000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.049523 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.049523 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.049523 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 100297.188755 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 100297.188755 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 100297.188755 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 100297.188755 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 100297.188755 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 100297.188755 # average overall mshr miss latency -system.l2bus.snoop_filter.tot_requests 461 # Total number of requests made to the snoop filter. -system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.l2bus.snoop_filter.hit_multi_requests 10 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.l2bus.trans_dist::ReadResp 348 # Transaction distribution -system.l2bus.trans_dist::CleanEvict 70 # Transaction distribution -system.l2bus.trans_dist::ReadExReq 43 # Transaction distribution -system.l2bus.trans_dist::ReadExResp 43 # Transaction distribution -system.l2bus.trans_dist::ReadSharedReq 348 # Transaction distribution -system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 568 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 284 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_count::total 852 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 15936 # Cumulative packet size per connected master and slave (bytes) -system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) -system.l2bus.pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes) -system.l2bus.snoops 0 # Total snoops (count) -system.l2bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.l2bus.snoop_fanout::samples 391 # Request fanout histogram -system.l2bus.snoop_fanout::mean 0.086957 # Request fanout histogram -system.l2bus.snoop_fanout::stdev 0.282132 # Request fanout histogram -system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::0 357 91.30% 91.30% # Request fanout histogram -system.l2bus.snoop_fanout::1 34 8.70% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram -system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram -system.l2bus.snoop_fanout::total 391 # Request fanout histogram -system.l2bus.reqLayer0.occupancy 461000 # Layer occupancy (ticks) -system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.l2bus.respLayer0.occupancy 747000 # Layer occupancy (ticks) -system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%) -system.l2bus.respLayer1.occupancy 426000 # Layer occupancy (ticks) -system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 184.362995 # Cycle average of tags in use -system.l2cache.tags.total_refs 100 # Total number of references to valid blocks. -system.l2cache.tags.sampled_refs 351 # Sample count of references to valid blocks. -system.l2cache.tags.avg_refs 0.284900 # Average number of references to valid blocks. -system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 107.367017 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 76.995978 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.026213 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.018798 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.045010 # Average percentage of cache occupancy -system.l2cache.tags.occ_task_id_blocks::1024 351 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::1 292 # Occupied blocks per task id -system.l2cache.tags.occ_task_id_percent::1024 0.085693 # Percentage of cache occupancy per task id -system.l2cache.tags.tag_accesses 3959 # Number of tag accesses -system.l2cache.tags.data_accesses 3959 # Number of data accesses -system.l2cache.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.l2cache.ReadSharedReq_hits::cpu.inst 24 # number of ReadSharedReq hits -system.l2cache.ReadSharedReq_hits::cpu.data 16 # number of ReadSharedReq hits -system.l2cache.ReadSharedReq_hits::total 40 # number of ReadSharedReq hits -system.l2cache.demand_hits::cpu.inst 24 # number of demand (read+write) hits -system.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits -system.l2cache.demand_hits::total 40 # number of demand (read+write) hits -system.l2cache.overall_hits::cpu.inst 24 # number of overall hits -system.l2cache.overall_hits::cpu.data 16 # number of overall hits -system.l2cache.overall_hits::total 40 # number of overall hits -system.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses -system.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses -system.l2cache.ReadSharedReq_misses::cpu.inst 225 # number of ReadSharedReq misses -system.l2cache.ReadSharedReq_misses::cpu.data 83 # number of ReadSharedReq misses -system.l2cache.ReadSharedReq_misses::total 308 # number of ReadSharedReq misses -system.l2cache.demand_misses::cpu.inst 225 # number of demand (read+write) misses -system.l2cache.demand_misses::cpu.data 126 # number of demand (read+write) misses -system.l2cache.demand_misses::total 351 # number of demand (read+write) misses -system.l2cache.overall_misses::cpu.inst 225 # number of overall misses -system.l2cache.overall_misses::cpu.data 126 # number of overall misses -system.l2cache.overall_misses::total 351 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 4437000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 4437000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 23683000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.data 8214000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 31897000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 23683000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 12651000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 36334000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 23683000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 12651000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 36334000 # number of overall miss cycles -system.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) -system.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) -system.l2cache.ReadSharedReq_accesses::cpu.inst 249 # number of ReadSharedReq accesses(hits+misses) -system.l2cache.ReadSharedReq_accesses::cpu.data 99 # number of ReadSharedReq accesses(hits+misses) -system.l2cache.ReadSharedReq_accesses::total 348 # number of ReadSharedReq accesses(hits+misses) -system.l2cache.demand_accesses::cpu.inst 249 # number of demand (read+write) accesses -system.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses -system.l2cache.demand_accesses::total 391 # number of demand (read+write) accesses -system.l2cache.overall_accesses::cpu.inst 249 # number of overall (read+write) accesses -system.l2cache.overall_accesses::cpu.data 142 # number of overall (read+write) accesses -system.l2cache.overall_accesses::total 391 # number of overall (read+write) accesses -system.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.l2cache.ReadSharedReq_miss_rate::cpu.inst 0.903614 # miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_miss_rate::cpu.data 0.838384 # miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_miss_rate::total 0.885057 # miss rate for ReadSharedReq accesses -system.l2cache.demand_miss_rate::cpu.inst 0.903614 # miss rate for demand accesses -system.l2cache.demand_miss_rate::cpu.data 0.887324 # miss rate for demand accesses -system.l2cache.demand_miss_rate::total 0.897698 # miss rate for demand accesses -system.l2cache.overall_miss_rate::cpu.inst 0.903614 # miss rate for overall accesses -system.l2cache.overall_miss_rate::cpu.data 0.887324 # miss rate for overall accesses -system.l2cache.overall_miss_rate::total 0.897698 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 103186.046512 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 103186.046512 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 105257.777778 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 98963.855422 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 103561.688312 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 105257.777778 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 100404.761905 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 103515.669516 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 105257.777778 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 100404.761905 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 103515.669516 # average overall miss latency -system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses -system.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses -system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 225 # number of ReadSharedReq MSHR misses -system.l2cache.ReadSharedReq_mshr_misses::cpu.data 83 # number of ReadSharedReq MSHR misses -system.l2cache.ReadSharedReq_mshr_misses::total 308 # number of ReadSharedReq MSHR misses -system.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses -system.l2cache.demand_mshr_misses::cpu.data 126 # number of demand (read+write) MSHR misses -system.l2cache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses -system.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses -system.l2cache.overall_mshr_misses::cpu.data 126 # number of overall MSHR misses -system.l2cache.overall_mshr_misses::total 351 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3577000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 3577000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19183000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6554000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 25737000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 19183000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 10131000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 29314000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 19183000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 10131000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 29314000 # number of overall MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.838384 # mshr miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.885057 # mshr miss rate for ReadSharedReq accesses -system.l2cache.demand_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for demand accesses -system.l2cache.demand_mshr_miss_rate::cpu.data 0.887324 # mshr miss rate for demand accesses -system.l2cache.demand_mshr_miss_rate::total 0.897698 # mshr miss rate for demand accesses -system.l2cache.overall_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for overall accesses -system.l2cache.overall_mshr_miss_rate::cpu.data 0.887324 # mshr miss rate for overall accesses -system.l2cache.overall_mshr_miss_rate::total 0.897698 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 83186.046512 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 83186.046512 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 85257.777778 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78963.855422 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 83561.688312 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 85257.777778 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 80404.761905 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 83515.669516 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 85257.777778 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80404.761905 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 83515.669516 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 351 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 308 # Transaction distribution -system.membus.trans_dist::ReadExReq 43 # Transaction distribution -system.membus.trans_dist::ReadExResp 43 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 308 # Transaction distribution -system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 702 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 702 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 22464 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22464 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 351 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 351 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 351 # Request fanout histogram -system.membus.reqLayer0.occupancy 351000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 1866250 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.6 # Layer utilization (%) +sim_seconds 0.000052 +sim_ticks 52453000 +final_tick 52453000 +sim_freq 1000000000000 +host_inst_rate 255460 +host_op_rate 295178 +host_tick_rate 2680706051 +host_mem_usage 666596 +host_seconds 0.02 +sim_insts 4988 +sim_ops 5770 +system.clk_domain.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 52453000 +system.mem_ctrl.bytes_read::cpu.inst 14400 +system.mem_ctrl.bytes_read::cpu.data 8064 +system.mem_ctrl.bytes_read::total 22464 +system.mem_ctrl.bytes_inst_read::cpu.inst 14400 +system.mem_ctrl.bytes_inst_read::total 14400 +system.mem_ctrl.num_reads::cpu.inst 225 +system.mem_ctrl.num_reads::cpu.data 126 +system.mem_ctrl.num_reads::total 351 +system.mem_ctrl.bw_read::cpu.inst 274531485 +system.mem_ctrl.bw_read::cpu.data 153737632 +system.mem_ctrl.bw_read::total 428269117 +system.mem_ctrl.bw_inst_read::cpu.inst 274531485 +system.mem_ctrl.bw_inst_read::total 274531485 +system.mem_ctrl.bw_total::cpu.inst 274531485 +system.mem_ctrl.bw_total::cpu.data 153737632 +system.mem_ctrl.bw_total::total 428269117 +system.mem_ctrl.readReqs 351 +system.mem_ctrl.writeReqs 0 +system.mem_ctrl.readBursts 351 +system.mem_ctrl.writeBursts 0 +system.mem_ctrl.bytesReadDRAM 22464 +system.mem_ctrl.bytesReadWrQ 0 +system.mem_ctrl.bytesWritten 0 +system.mem_ctrl.bytesReadSys 22464 +system.mem_ctrl.bytesWrittenSys 0 +system.mem_ctrl.servicedByWrQ 0 +system.mem_ctrl.mergedWrBursts 0 +system.mem_ctrl.neitherReadNorWriteReqs 0 +system.mem_ctrl.perBankRdBursts::0 78 +system.mem_ctrl.perBankRdBursts::1 42 +system.mem_ctrl.perBankRdBursts::2 13 +system.mem_ctrl.perBankRdBursts::3 33 +system.mem_ctrl.perBankRdBursts::4 14 +system.mem_ctrl.perBankRdBursts::5 31 +system.mem_ctrl.perBankRdBursts::6 34 +system.mem_ctrl.perBankRdBursts::7 9 +system.mem_ctrl.perBankRdBursts::8 4 +system.mem_ctrl.perBankRdBursts::9 6 +system.mem_ctrl.perBankRdBursts::10 25 +system.mem_ctrl.perBankRdBursts::11 43 +system.mem_ctrl.perBankRdBursts::12 8 +system.mem_ctrl.perBankRdBursts::13 5 +system.mem_ctrl.perBankRdBursts::14 0 +system.mem_ctrl.perBankRdBursts::15 6 +system.mem_ctrl.perBankWrBursts::0 0 +system.mem_ctrl.perBankWrBursts::1 0 +system.mem_ctrl.perBankWrBursts::2 0 +system.mem_ctrl.perBankWrBursts::3 0 +system.mem_ctrl.perBankWrBursts::4 0 +system.mem_ctrl.perBankWrBursts::5 0 +system.mem_ctrl.perBankWrBursts::6 0 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+system.membus.reqLayer0.utilization 0.7 +system.membus.respLayer0.occupancy 1866250 +system.membus.respLayer0.utilization 3.6 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/config.ini index d1ab85628..22ac65ead 100644 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/config.ini @@ -91,6 +91,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -120,7 +121,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=tests/test-progs/hello/bin/sparc/linux/hello cwd= drivers= @@ -133,10 +134,11 @@ executable= gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simerr b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simerr index 2f9507495..1cfcb3e18 100755 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simerr +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simerr @@ -1,3 +1,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simout index 4568a6760..4f2bfd587 100755 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simout +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linu gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 13 2016 20:43:27 -gem5 started Oct 13 2016 20:47:16 -gem5 executing on e108600-lin, pid 17418 -command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple +gem5 compiled Apr 3 2017 18:41:19 +gem5 started Apr 3 2017 18:41:38 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 64860 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple Global frequency set at 1000000000000 ticks per second Beginning simulation! -info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 380341000 because target called exit() +Hello World!Exiting @ tick 380341000 because exiting with last active thread context diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt index 25ad41fa6..c3baff489 100644 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt @@ -1,386 +1,386 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000380 # Number of seconds simulated -sim_ticks 380341000 # Number of ticks simulated -final_tick 380341000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 290732 # Simulator instruction rate (inst/s) -host_op_rate 290372 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 19883940078 # Simulator tick rate (ticks/s) -host_mem_usage 632768 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -sim_insts 5548 # Number of instructions simulated -sim_ops 5548 # Number of ops (including micro ops) simulated -system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 380341000 # Cumulative time (in ticks) in various power states -system.mem_ctrl.bytes_read::cpu.inst 22364 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::cpu.data 4640 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::total 27004 # Number of bytes read from this memory -system.mem_ctrl.bytes_inst_read::cpu.inst 22364 # Number of instructions bytes read from this memory -system.mem_ctrl.bytes_inst_read::total 22364 # Number of instructions bytes read from this memory -system.mem_ctrl.bytes_written::cpu.data 5065 # Number of bytes written to this memory -system.mem_ctrl.bytes_written::total 5065 # Number of bytes written to this memory -system.mem_ctrl.num_reads::cpu.inst 5591 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::cpu.data 718 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::total 6309 # Number of read requests responded to by this memory -system.mem_ctrl.num_writes::cpu.data 673 # Number of write requests responded to by this memory -system.mem_ctrl.num_writes::total 673 # Number of write requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 58799866 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 12199579 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 70999445 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 58799866 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 58799866 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::cpu.data 13316997 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::total 13316997 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 58799866 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 25516576 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 84316442 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.readReqs 6310 # Number of read requests accepted -system.mem_ctrl.writeReqs 673 # Number of write requests accepted -system.mem_ctrl.readBursts 6310 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrl.writeBursts 673 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 397760 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 6080 # Total number of bytes read from write queue -system.mem_ctrl.bytesWritten 6144 # Total number of bytes written to DRAM -system.mem_ctrl.bytesReadSys 27008 # Total read bytes from the system interface side -system.mem_ctrl.bytesWrittenSys 5065 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 95 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 548 # Number of DRAM write bursts merged with an existing one -system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrl.perBankRdBursts::0 220 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::1 84 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::2 2 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::3 199 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::4 0 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::5 1004 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::6 1555 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::7 875 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::8 710 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::9 348 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::10 99 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::11 623 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::12 56 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::13 162 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::14 200 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::15 78 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::5 16 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::6 42 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::7 19 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::9 5 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::12 4 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::13 10 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts -system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 380264000 # Total gap between requests -system.mem_ctrl.readPktSize::0 88 # Read request sizes (log2) -system.mem_ctrl.readPktSize::1 2 # Read request sizes (log2) -system.mem_ctrl.readPktSize::2 5711 # Read request sizes (log2) -system.mem_ctrl.readPktSize::3 509 # Read request sizes (log2) -system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::6 0 # Read request sizes (log2) -system.mem_ctrl.writePktSize::0 13 # Write request sizes (log2) -system.mem_ctrl.writePktSize::1 2 # Write request sizes (log2) -system.mem_ctrl.writePktSize::2 54 # Write request sizes (log2) -system.mem_ctrl.writePktSize::3 604 # Write request sizes (log2) -system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 6215 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::15 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::16 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::17 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::18 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::19 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::20 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::21 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::22 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::23 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::24 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::25 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::26 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::27 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::28 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::29 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::30 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::31 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::32 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 575 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 700.438261 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 528.229400 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 375.888489 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 45 7.83% 7.83% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 73 12.70% 20.52% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 37 6.43% 26.96% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 35 6.09% 33.04% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 26 4.52% 37.57% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 27 4.70% 42.26% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 26 4.52% 46.78% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 27 4.70% 51.48% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 279 48.52% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 575 # Bytes accessed per row activation -system.mem_ctrl.rdPerTurnAround::samples 6 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::mean 772.166667 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::gmean 643.154197 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::stdev 524.176084 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::256-319 2 33.33% 33.33% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::640-703 1 16.67% 50.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::704-767 1 16.67% 66.67% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::896-959 1 16.67% 83.33% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1664-1727 1 16.67% 100.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::total 6 # Reads before turning the bus around for writes -system.mem_ctrl.wrPerTurnAround::samples 6 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::16 6 100.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::total 6 # Writes before turning the bus around for reads -system.mem_ctrl.totQLat 59680000 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 176211250 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 31075000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 9602.57 # Average queueing delay per DRAM burst -system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 28352.57 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 1045.80 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 16.15 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 71.01 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 13.32 # Average system write bandwidth in MiByte/s -system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 8.30 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 8.17 # Data bus utilization in percentage for reads -system.mem_ctrl.busUtilWrite 0.13 # Data bus utilization in percentage for writes -system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 23.12 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 5650 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 83 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 90.91 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate 66.40 # Row buffer hit rate for writes -system.mem_ctrl.avgGap 54455.68 # Average gap between requests -system.mem_ctrl.pageHitRate 90.43 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 2598960 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 1377585 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 28124460 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 401940 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 29502720.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 55884510 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 903360 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.actPowerDownEnergy 108619200 # Energy for active power-down per rank (pJ) -system.mem_ctrl_0.prePowerDownEnergy 6618240 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrl_0.totalEnergy 234030975 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 615.318415 # Core power per rank (mW) -system.mem_ctrl_0.totalIdleTime 255286000 # Total Idle time Per DRAM Rank -system.mem_ctrl_0.memoryStateTime::IDLE 462000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 12480000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 17232500 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 111848750 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 238317750 # Time in different power states -system.mem_ctrl_1.actEnergy 1527960 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 804540 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 16243500 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 99180 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 28273440.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 35538930 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 1997760 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.actPowerDownEnergy 96272430 # Energy for active power-down per rank (pJ) -system.mem_ctrl_1.prePowerDownEnergy 16892160 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_1.selfRefreshEnergy 11758020 # Energy for self refresh per rank (pJ) -system.mem_ctrl_1.totalEnergy 209407920 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 550.579039 # Core power per rank (mW) -system.mem_ctrl_1.totalIdleTime 297220000 # Total Idle time Per DRAM Rank -system.mem_ctrl_1.memoryStateTime::IDLE 3473000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 11978000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::SREF 42087750 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 43986250 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 67670000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 211146000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 380341000 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 380341000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 380341 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5548 # Number of instructions committed -system.cpu.committedOps 5548 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4660 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 146 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 835 # number of instructions that are conditional controls -system.cpu.num_int_insts 4660 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 10977 # number of times the integer registers were read -system.cpu.num_int_register_writes 5062 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 1404 # number of memory refs -system.cpu.num_load_insts 726 # Number of load instructions -system.cpu.num_store_insts 678 # Number of store instructions -system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 380340.999000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1187 # Number of branches fetched -system.cpu.op_class::No_OpClass 173 3.09% 3.09% # Class of executed instruction -system.cpu.op_class::IntAlu 4014 71.79% 74.89% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::MemRead 726 12.99% 87.87% # Class of executed instruction -system.cpu.op_class::MemWrite 678 12.13% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5591 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 380341000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 6310 # Transaction distribution -system.membus.trans_dist::ReadResp 6309 # Transaction distribution -system.membus.trans_dist::WriteReq 673 # Transaction distribution -system.membus.trans_dist::WriteResp 673 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 11183 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 2782 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 13965 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 22364 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 9705 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 32069 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 6983 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 6983 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 6983 # Request fanout histogram -system.membus.reqLayer0.occupancy 7656000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 12691750 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 2300750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.6 # Layer utilization (%) +sim_seconds 0.000380 +sim_ticks 380341000 +final_tick 380341000 +sim_freq 1000000000000 +host_inst_rate 164409 +host_op_rate 164322 +host_tick_rate 11259796640 +host_mem_usage 644796 +host_seconds 0.03 +sim_insts 5548 +sim_ops 5548 +system.clk_domain.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 380341000 +system.mem_ctrl.bytes_read::cpu.inst 22364 +system.mem_ctrl.bytes_read::cpu.data 4640 +system.mem_ctrl.bytes_read::total 27004 +system.mem_ctrl.bytes_inst_read::cpu.inst 22364 +system.mem_ctrl.bytes_inst_read::total 22364 +system.mem_ctrl.bytes_written::cpu.data 5065 +system.mem_ctrl.bytes_written::total 5065 +system.mem_ctrl.num_reads::cpu.inst 5591 +system.mem_ctrl.num_reads::cpu.data 718 +system.mem_ctrl.num_reads::total 6309 +system.mem_ctrl.num_writes::cpu.data 673 +system.mem_ctrl.num_writes::total 673 +system.mem_ctrl.bw_read::cpu.inst 58799866 +system.mem_ctrl.bw_read::cpu.data 12199579 +system.mem_ctrl.bw_read::total 70999445 +system.mem_ctrl.bw_inst_read::cpu.inst 58799866 +system.mem_ctrl.bw_inst_read::total 58799866 +system.mem_ctrl.bw_write::cpu.data 13316997 +system.mem_ctrl.bw_write::total 13316997 +system.mem_ctrl.bw_total::cpu.inst 58799866 +system.mem_ctrl.bw_total::cpu.data 25516576 +system.mem_ctrl.bw_total::total 84316442 +system.mem_ctrl.readReqs 6310 +system.mem_ctrl.writeReqs 673 +system.mem_ctrl.readBursts 6310 +system.mem_ctrl.writeBursts 673 +system.mem_ctrl.bytesReadDRAM 397760 +system.mem_ctrl.bytesReadWrQ 6080 +system.mem_ctrl.bytesWritten 6144 +system.mem_ctrl.bytesReadSys 27008 +system.mem_ctrl.bytesWrittenSys 5065 +system.mem_ctrl.servicedByWrQ 95 +system.mem_ctrl.mergedWrBursts 548 +system.mem_ctrl.neitherReadNorWriteReqs 0 +system.mem_ctrl.perBankRdBursts::0 220 +system.mem_ctrl.perBankRdBursts::1 84 +system.mem_ctrl.perBankRdBursts::2 2 +system.mem_ctrl.perBankRdBursts::3 199 +system.mem_ctrl.perBankRdBursts::4 0 +system.mem_ctrl.perBankRdBursts::5 1004 +system.mem_ctrl.perBankRdBursts::6 1555 +system.mem_ctrl.perBankRdBursts::7 875 +system.mem_ctrl.perBankRdBursts::8 710 +system.mem_ctrl.perBankRdBursts::9 348 +system.mem_ctrl.perBankRdBursts::10 99 +system.mem_ctrl.perBankRdBursts::11 623 +system.mem_ctrl.perBankRdBursts::12 56 +system.mem_ctrl.perBankRdBursts::13 162 +system.mem_ctrl.perBankRdBursts::14 200 +system.mem_ctrl.perBankRdBursts::15 78 +system.mem_ctrl.perBankWrBursts::0 0 +system.mem_ctrl.perBankWrBursts::1 0 +system.mem_ctrl.perBankWrBursts::2 0 +system.mem_ctrl.perBankWrBursts::3 0 +system.mem_ctrl.perBankWrBursts::4 0 +system.mem_ctrl.perBankWrBursts::5 16 +system.mem_ctrl.perBankWrBursts::6 42 +system.mem_ctrl.perBankWrBursts::7 19 +system.mem_ctrl.perBankWrBursts::8 0 +system.mem_ctrl.perBankWrBursts::9 5 +system.mem_ctrl.perBankWrBursts::10 0 +system.mem_ctrl.perBankWrBursts::11 0 +system.mem_ctrl.perBankWrBursts::12 4 +system.mem_ctrl.perBankWrBursts::13 10 +system.mem_ctrl.perBankWrBursts::14 0 +system.mem_ctrl.perBankWrBursts::15 0 +system.mem_ctrl.numRdRetry 0 +system.mem_ctrl.numWrRetry 0 +system.mem_ctrl.totGap 380264000 +system.mem_ctrl.readPktSize::0 88 +system.mem_ctrl.readPktSize::1 2 +system.mem_ctrl.readPktSize::2 5711 +system.mem_ctrl.readPktSize::3 509 +system.mem_ctrl.readPktSize::4 0 +system.mem_ctrl.readPktSize::5 0 +system.mem_ctrl.readPktSize::6 0 +system.mem_ctrl.writePktSize::0 13 +system.mem_ctrl.writePktSize::1 2 +system.mem_ctrl.writePktSize::2 54 +system.mem_ctrl.writePktSize::3 604 +system.mem_ctrl.writePktSize::4 0 +system.mem_ctrl.writePktSize::5 0 +system.mem_ctrl.writePktSize::6 0 +system.mem_ctrl.rdQLenPdf::0 6215 +system.mem_ctrl.rdQLenPdf::1 0 +system.mem_ctrl.rdQLenPdf::2 0 +system.mem_ctrl.rdQLenPdf::3 0 +system.mem_ctrl.rdQLenPdf::4 0 +system.mem_ctrl.rdQLenPdf::5 0 +system.mem_ctrl.rdQLenPdf::6 0 +system.mem_ctrl.rdQLenPdf::7 0 +system.mem_ctrl.rdQLenPdf::8 0 +system.mem_ctrl.rdQLenPdf::9 0 +system.mem_ctrl.rdQLenPdf::10 0 +system.mem_ctrl.rdQLenPdf::11 0 +system.mem_ctrl.rdQLenPdf::12 0 +system.mem_ctrl.rdQLenPdf::13 0 +system.mem_ctrl.rdQLenPdf::14 0 +system.mem_ctrl.rdQLenPdf::15 0 +system.mem_ctrl.rdQLenPdf::16 0 +system.mem_ctrl.rdQLenPdf::17 0 +system.mem_ctrl.rdQLenPdf::18 0 +system.mem_ctrl.rdQLenPdf::19 0 +system.mem_ctrl.rdQLenPdf::20 0 +system.mem_ctrl.rdQLenPdf::21 0 +system.mem_ctrl.rdQLenPdf::22 0 +system.mem_ctrl.rdQLenPdf::23 0 +system.mem_ctrl.rdQLenPdf::24 0 +system.mem_ctrl.rdQLenPdf::25 0 +system.mem_ctrl.rdQLenPdf::26 0 +system.mem_ctrl.rdQLenPdf::27 0 +system.mem_ctrl.rdQLenPdf::28 0 +system.mem_ctrl.rdQLenPdf::29 0 +system.mem_ctrl.rdQLenPdf::30 0 +system.mem_ctrl.rdQLenPdf::31 0 +system.mem_ctrl.wrQLenPdf::0 1 +system.mem_ctrl.wrQLenPdf::1 1 +system.mem_ctrl.wrQLenPdf::2 1 +system.mem_ctrl.wrQLenPdf::3 1 +system.mem_ctrl.wrQLenPdf::4 1 +system.mem_ctrl.wrQLenPdf::5 1 +system.mem_ctrl.wrQLenPdf::6 1 +system.mem_ctrl.wrQLenPdf::7 1 +system.mem_ctrl.wrQLenPdf::8 1 +system.mem_ctrl.wrQLenPdf::9 1 +system.mem_ctrl.wrQLenPdf::10 1 +system.mem_ctrl.wrQLenPdf::11 1 +system.mem_ctrl.wrQLenPdf::12 1 +system.mem_ctrl.wrQLenPdf::13 1 +system.mem_ctrl.wrQLenPdf::14 1 +system.mem_ctrl.wrQLenPdf::15 1 +system.mem_ctrl.wrQLenPdf::16 1 +system.mem_ctrl.wrQLenPdf::17 7 +system.mem_ctrl.wrQLenPdf::18 7 +system.mem_ctrl.wrQLenPdf::19 7 +system.mem_ctrl.wrQLenPdf::20 7 +system.mem_ctrl.wrQLenPdf::21 7 +system.mem_ctrl.wrQLenPdf::22 7 +system.mem_ctrl.wrQLenPdf::23 7 +system.mem_ctrl.wrQLenPdf::24 7 +system.mem_ctrl.wrQLenPdf::25 7 +system.mem_ctrl.wrQLenPdf::26 7 +system.mem_ctrl.wrQLenPdf::27 7 +system.mem_ctrl.wrQLenPdf::28 7 +system.mem_ctrl.wrQLenPdf::29 6 +system.mem_ctrl.wrQLenPdf::30 6 +system.mem_ctrl.wrQLenPdf::31 6 +system.mem_ctrl.wrQLenPdf::32 6 +system.mem_ctrl.wrQLenPdf::33 0 +system.mem_ctrl.wrQLenPdf::34 0 +system.mem_ctrl.wrQLenPdf::35 0 +system.mem_ctrl.wrQLenPdf::36 0 +system.mem_ctrl.wrQLenPdf::37 0 +system.mem_ctrl.wrQLenPdf::38 0 +system.mem_ctrl.wrQLenPdf::39 0 +system.mem_ctrl.wrQLenPdf::40 0 +system.mem_ctrl.wrQLenPdf::41 0 +system.mem_ctrl.wrQLenPdf::42 0 +system.mem_ctrl.wrQLenPdf::43 0 +system.mem_ctrl.wrQLenPdf::44 0 +system.mem_ctrl.wrQLenPdf::45 0 +system.mem_ctrl.wrQLenPdf::46 0 +system.mem_ctrl.wrQLenPdf::47 0 +system.mem_ctrl.wrQLenPdf::48 0 +system.mem_ctrl.wrQLenPdf::49 0 +system.mem_ctrl.wrQLenPdf::50 0 +system.mem_ctrl.wrQLenPdf::51 0 +system.mem_ctrl.wrQLenPdf::52 0 +system.mem_ctrl.wrQLenPdf::53 0 +system.mem_ctrl.wrQLenPdf::54 0 +system.mem_ctrl.wrQLenPdf::55 0 +system.mem_ctrl.wrQLenPdf::56 0 +system.mem_ctrl.wrQLenPdf::57 0 +system.mem_ctrl.wrQLenPdf::58 0 +system.mem_ctrl.wrQLenPdf::59 0 +system.mem_ctrl.wrQLenPdf::60 0 +system.mem_ctrl.wrQLenPdf::61 0 +system.mem_ctrl.wrQLenPdf::62 0 +system.mem_ctrl.wrQLenPdf::63 0 +system.mem_ctrl.bytesPerActivate::samples 575 +system.mem_ctrl.bytesPerActivate::mean 700.438261 +system.mem_ctrl.bytesPerActivate::gmean 528.229400 +system.mem_ctrl.bytesPerActivate::stdev 375.888489 +system.mem_ctrl.bytesPerActivate::0-127 45 7.83% 7.83% +system.mem_ctrl.bytesPerActivate::128-255 73 12.70% 20.52% +system.mem_ctrl.bytesPerActivate::256-383 37 6.43% 26.96% +system.mem_ctrl.bytesPerActivate::384-511 35 6.09% 33.04% +system.mem_ctrl.bytesPerActivate::512-639 26 4.52% 37.57% +system.mem_ctrl.bytesPerActivate::640-767 27 4.70% 42.26% +system.mem_ctrl.bytesPerActivate::768-895 26 4.52% 46.78% +system.mem_ctrl.bytesPerActivate::896-1023 27 4.70% 51.48% +system.mem_ctrl.bytesPerActivate::1024-1151 279 48.52% 100.00% +system.mem_ctrl.bytesPerActivate::total 575 +system.mem_ctrl.rdPerTurnAround::samples 6 +system.mem_ctrl.rdPerTurnAround::mean 772.166667 +system.mem_ctrl.rdPerTurnAround::gmean 643.154197 +system.mem_ctrl.rdPerTurnAround::stdev 524.176084 +system.mem_ctrl.rdPerTurnAround::256-319 2 33.33% 33.33% +system.mem_ctrl.rdPerTurnAround::640-703 1 16.67% 50.00% +system.mem_ctrl.rdPerTurnAround::704-767 1 16.67% 66.67% +system.mem_ctrl.rdPerTurnAround::896-959 1 16.67% 83.33% +system.mem_ctrl.rdPerTurnAround::1664-1727 1 16.67% 100.00% +system.mem_ctrl.rdPerTurnAround::total 6 +system.mem_ctrl.wrPerTurnAround::samples 6 +system.mem_ctrl.wrPerTurnAround::mean 16 +system.mem_ctrl.wrPerTurnAround::gmean 16.000000 +system.mem_ctrl.wrPerTurnAround::16 6 100.00% 100.00% +system.mem_ctrl.wrPerTurnAround::total 6 +system.mem_ctrl.totQLat 59680000 +system.mem_ctrl.totMemAccLat 176211250 +system.mem_ctrl.totBusLat 31075000 +system.mem_ctrl.avgQLat 9602.57 +system.mem_ctrl.avgBusLat 5000.00 +system.mem_ctrl.avgMemAccLat 28352.57 +system.mem_ctrl.avgRdBW 1045.80 +system.mem_ctrl.avgWrBW 16.15 +system.mem_ctrl.avgRdBWSys 71.01 +system.mem_ctrl.avgWrBWSys 13.32 +system.mem_ctrl.peakBW 12800.00 +system.mem_ctrl.busUtil 8.30 +system.mem_ctrl.busUtilRead 8.17 +system.mem_ctrl.busUtilWrite 0.13 +system.mem_ctrl.avgRdQLen 1.00 +system.mem_ctrl.avgWrQLen 23.12 +system.mem_ctrl.readRowHits 5650 +system.mem_ctrl.writeRowHits 83 +system.mem_ctrl.readRowHitRate 90.91 +system.mem_ctrl.writeRowHitRate 66.40 +system.mem_ctrl.avgGap 54455.68 +system.mem_ctrl.pageHitRate 90.43 +system.mem_ctrl_0.actEnergy 2598960 +system.mem_ctrl_0.preEnergy 1377585 +system.mem_ctrl_0.readEnergy 28124460 +system.mem_ctrl_0.writeEnergy 401940 +system.mem_ctrl_0.refreshEnergy 29502720.000000 +system.mem_ctrl_0.actBackEnergy 55884510 +system.mem_ctrl_0.preBackEnergy 903360 +system.mem_ctrl_0.actPowerDownEnergy 108619200 +system.mem_ctrl_0.prePowerDownEnergy 6618240 +system.mem_ctrl_0.selfRefreshEnergy 0 +system.mem_ctrl_0.totalEnergy 234030975 +system.mem_ctrl_0.averagePower 615.318415 +system.mem_ctrl_0.totalIdleTime 255286000 +system.mem_ctrl_0.memoryStateTime::IDLE 462000 +system.mem_ctrl_0.memoryStateTime::REF 12480000 +system.mem_ctrl_0.memoryStateTime::SREF 0 +system.mem_ctrl_0.memoryStateTime::PRE_PDN 17232500 +system.mem_ctrl_0.memoryStateTime::ACT 111848750 +system.mem_ctrl_0.memoryStateTime::ACT_PDN 238317750 +system.mem_ctrl_1.actEnergy 1527960 +system.mem_ctrl_1.preEnergy 804540 +system.mem_ctrl_1.readEnergy 16243500 +system.mem_ctrl_1.writeEnergy 99180 +system.mem_ctrl_1.refreshEnergy 28273440.000000 +system.mem_ctrl_1.actBackEnergy 35538930 +system.mem_ctrl_1.preBackEnergy 1997760 +system.mem_ctrl_1.actPowerDownEnergy 96272430 +system.mem_ctrl_1.prePowerDownEnergy 16892160 +system.mem_ctrl_1.selfRefreshEnergy 11758020 +system.mem_ctrl_1.totalEnergy 209407920 +system.mem_ctrl_1.averagePower 550.579039 +system.mem_ctrl_1.totalIdleTime 297220000 +system.mem_ctrl_1.memoryStateTime::IDLE 3473000 +system.mem_ctrl_1.memoryStateTime::REF 11978000 +system.mem_ctrl_1.memoryStateTime::SREF 42087750 +system.mem_ctrl_1.memoryStateTime::PRE_PDN 43986250 +system.mem_ctrl_1.memoryStateTime::ACT 67670000 +system.mem_ctrl_1.memoryStateTime::ACT_PDN 211146000 +system.pwrStateResidencyTicks::UNDEFINED 380341000 +system.cpu.workload.numSyscalls 11 +system.cpu.pwrStateResidencyTicks::ON 380341000 +system.cpu.numCycles 380341 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 5548 +system.cpu.committedOps 5548 +system.cpu.num_int_alu_accesses 4660 +system.cpu.num_fp_alu_accesses 0 +system.cpu.num_func_calls 146 +system.cpu.num_conditional_control_insts 835 +system.cpu.num_int_insts 4660 +system.cpu.num_fp_insts 0 +system.cpu.num_int_register_reads 10977 +system.cpu.num_int_register_writes 5062 +system.cpu.num_fp_register_reads 0 +system.cpu.num_fp_register_writes 0 +system.cpu.num_mem_refs 1404 +system.cpu.num_load_insts 726 +system.cpu.num_store_insts 678 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 380341 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 1187 +system.cpu.op_class::No_OpClass 173 3.09% 3.09% +system.cpu.op_class::IntAlu 4014 71.79% 74.89% +system.cpu.op_class::IntMult 0 0.00% 74.89% +system.cpu.op_class::IntDiv 0 0.00% 74.89% +system.cpu.op_class::FloatAdd 0 0.00% 74.89% +system.cpu.op_class::FloatCmp 0 0.00% 74.89% +system.cpu.op_class::FloatCvt 0 0.00% 74.89% +system.cpu.op_class::FloatMult 0 0.00% 74.89% +system.cpu.op_class::FloatMultAcc 0 0.00% 74.89% +system.cpu.op_class::FloatDiv 0 0.00% 74.89% +system.cpu.op_class::FloatMisc 0 0.00% 74.89% +system.cpu.op_class::FloatSqrt 0 0.00% 74.89% +system.cpu.op_class::SimdAdd 0 0.00% 74.89% +system.cpu.op_class::SimdAddAcc 0 0.00% 74.89% +system.cpu.op_class::SimdAlu 0 0.00% 74.89% +system.cpu.op_class::SimdCmp 0 0.00% 74.89% +system.cpu.op_class::SimdCvt 0 0.00% 74.89% +system.cpu.op_class::SimdMisc 0 0.00% 74.89% +system.cpu.op_class::SimdMult 0 0.00% 74.89% +system.cpu.op_class::SimdMultAcc 0 0.00% 74.89% +system.cpu.op_class::SimdShift 0 0.00% 74.89% +system.cpu.op_class::SimdShiftAcc 0 0.00% 74.89% +system.cpu.op_class::SimdSqrt 0 0.00% 74.89% +system.cpu.op_class::SimdFloatAdd 0 0.00% 74.89% +system.cpu.op_class::SimdFloatAlu 0 0.00% 74.89% +system.cpu.op_class::SimdFloatCmp 0 0.00% 74.89% +system.cpu.op_class::SimdFloatCvt 0 0.00% 74.89% +system.cpu.op_class::SimdFloatDiv 0 0.00% 74.89% +system.cpu.op_class::SimdFloatMisc 0 0.00% 74.89% +system.cpu.op_class::SimdFloatMult 0 0.00% 74.89% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 74.89% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 74.89% +system.cpu.op_class::MemRead 726 12.99% 87.87% +system.cpu.op_class::MemWrite 678 12.13% 100.00% +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 5591 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 380341000 +system.membus.trans_dist::ReadReq 6310 +system.membus.trans_dist::ReadResp 6309 +system.membus.trans_dist::WriteReq 673 +system.membus.trans_dist::WriteResp 673 +system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 11183 +system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 2782 +system.membus.pkt_count::total 13965 +system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 22364 +system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 9705 +system.membus.pkt_size::total 32069 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 6983 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 6983 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 6983 +system.membus.reqLayer0.occupancy 7656000 +system.membus.reqLayer0.utilization 2.0 +system.membus.respLayer0.occupancy 12691750 +system.membus.respLayer0.utilization 3.3 +system.membus.respLayer1.occupancy 2300750 +system.membus.respLayer1.utilization 0.6 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/config.ini index d90641228..ec35c6b67 100644 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/config.ini @@ -91,6 +91,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -104,10 +105,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -121,6 +122,7 @@ response_latency=2 sequential_access=false size=65536 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -133,15 +135,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=65536 +tag_latency=2 [system.cpu.dtb] type=SparcTLB @@ -155,10 +158,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -172,6 +175,7 @@ response_latency=2 sequential_access=false size=16384 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -184,15 +188,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=16384 +tag_latency=2 [system.cpu.interrupts] type=SparcInterrupts @@ -212,7 +217,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=tests/test-progs/hello/bin/sparc/linux/hello cwd= drivers= @@ -225,10 +230,11 @@ executable= gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -278,10 +284,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -295,6 +301,7 @@ response_latency=20 sequential_access=false size=262144 system=system +tag_latency=20 tags=system.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -307,15 +314,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=20 [system.mem_ctrl] type=DRAMCtrl diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simerr b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simerr index 2f9507495..1cfcb3e18 100755 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simerr +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simerr @@ -1,3 +1,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simout index 95530f5be..ca7e9e456 100755 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simout +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linu gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 13 2016 20:43:27 -gem5 started Oct 13 2016 20:45:43 -gem5 executing on e108600-lin, pid 17392 -command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level +gem5 compiled Apr 3 2017 18:41:19 +gem5 started Apr 3 2017 18:43:32 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 66465 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level Global frequency set at 1000000000000 ticks per second Beginning simulation! -info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 56511000 because target called exit() +Hello World!Exiting @ tick 56511000 because exiting with last active thread context diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt index 86dd54128..c0123cf6a 100644 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt @@ -1,716 +1,716 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000057 # Number of seconds simulated -sim_ticks 56511000 # Number of ticks simulated -final_tick 56511000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 572788 # Simulator instruction rate (inst/s) -host_op_rate 572177 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5822018151 # Simulator tick rate (ticks/s) -host_mem_usage 636864 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 5548 # Number of instructions simulated -sim_ops 5548 # Number of ops (including micro ops) simulated -system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states -system.mem_ctrl.bytes_read::cpu.inst 16448 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::cpu.data 8768 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::total 25216 # Number of bytes read from this memory -system.mem_ctrl.bytes_inst_read::cpu.inst 16448 # Number of instructions bytes read from this memory -system.mem_ctrl.bytes_inst_read::total 16448 # Number of instructions bytes read from this memory -system.mem_ctrl.num_reads::cpu.inst 257 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::cpu.data 137 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::total 394 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 291058378 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 155155633 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 446214011 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 291058378 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 291058378 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 291058378 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 155155633 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 446214011 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.readReqs 394 # Number of read requests accepted -system.mem_ctrl.writeReqs 0 # Number of write requests accepted -system.mem_ctrl.readBursts 394 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 25216 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue -system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM -system.mem_ctrl.bytesReadSys 25216 # Total read bytes from the system interface side -system.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrl.perBankRdBursts::0 21 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::1 7 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::2 1 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::3 7 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::4 0 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::5 69 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::6 79 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::7 62 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::8 32 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::9 17 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::10 9 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::11 47 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::12 10 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::13 21 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::14 5 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::15 7 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts -system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 56394000 # Total gap between requests -system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::6 394 # Read request sizes (log2) -system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 394 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 98 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 248.816327 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 183.748429 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 196.431638 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 26 26.53% 26.53% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 31 31.63% 58.16% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 15 15.31% 73.47% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 13 13.27% 86.73% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 9 9.18% 95.92% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 2 2.04% 97.96% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 1 1.02% 98.98% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 1 1.02% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 98 # Bytes accessed per row activation -system.mem_ctrl.totQLat 5793000 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 13180500 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 1970000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 14703.05 # Average queueing delay per DRAM burst -system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 33453.05 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 446.21 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 446.21 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 3.49 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 3.49 # Data bus utilization in percentage for reads -system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 292 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 74.11 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 143131.98 # Average gap between requests -system.mem_ctrl.pageHitRate 74.11 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 421260 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 216315 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 1756440 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 4075500 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 122880 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.actPowerDownEnergy 21123630 # Energy for active power-down per rank (pJ) -system.mem_ctrl_0.prePowerDownEnergy 357120 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrl_0.totalEnergy 32375625 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 572.905837 # Core power per rank (mW) -system.mem_ctrl_0.totalIdleTime 47002000 # Total Idle time Per DRAM Rank -system.mem_ctrl_0.memoryStateTime::IDLE 71000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 929250 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 7357750 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 46333000 # Time in different power states -system.mem_ctrl_1.actEnergy 307020 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 155595 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 1056720 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 2785590 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 293760 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.actPowerDownEnergy 20523420 # Energy for active power-down per rank (pJ) -system.mem_ctrl_1.prePowerDownEnergy 1777920 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrl_1.totalEnergy 31202505 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 552.146785 # Core power per rank (mW) -system.mem_ctrl_1.totalIdleTime 49582750 # Total Idle time Per DRAM Rank -system.mem_ctrl_1.memoryStateTime::IDLE 557000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 4629500 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 4495750 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 45008750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 56511000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 56511 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5548 # Number of instructions committed -system.cpu.committedOps 5548 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4660 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 146 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 835 # number of instructions that are conditional controls -system.cpu.num_int_insts 4660 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 10977 # number of times the integer registers were read -system.cpu.num_int_register_writes 5062 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 1404 # number of memory refs -system.cpu.num_load_insts 726 # Number of load instructions -system.cpu.num_store_insts 678 # Number of store instructions -system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 56510.999000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1187 # Number of branches fetched -system.cpu.op_class::No_OpClass 173 3.09% 3.09% # Class of executed instruction -system.cpu.op_class::IntAlu 4014 71.79% 74.89% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 74.89% # Class of executed instruction -system.cpu.op_class::MemRead 726 12.99% 87.87% # Class of executed instruction -system.cpu.op_class::MemWrite 678 12.13% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5591 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 83.847801 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.079710 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 83.847801 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.081883 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.081883 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.134766 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 2920 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 2920 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 662 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 662 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 591 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 591 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits -system.cpu.dcache.overall_hits::total 1253 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 56 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 56 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 82 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 82 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses -system.cpu.dcache.overall_misses::total 138 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6576000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6576000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8937000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8937000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15513000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15513000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15513000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15513000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 718 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 718 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1391 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1391 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1391 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1391 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.077994 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.077994 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.121842 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.121842 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.099209 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.099209 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.099209 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.099209 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 117428.571429 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 117428.571429 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 108987.804878 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 108987.804878 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 112413.043478 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 112413.043478 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 112413.043478 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 112413.043478 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 56 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 82 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6464000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6464000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8773000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8773000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15237000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15237000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15237000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15237000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.077994 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.077994 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.121842 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.121842 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.099209 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.099209 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.099209 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.099209 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 115428.571429 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 115428.571429 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 106987.804878 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 106987.804878 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 110413.043478 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 110413.043478 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 110413.043478 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 110413.043478 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 71 # number of replacements -system.cpu.icache.tags.tagsinuse 98.324434 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 5333 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 259 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 20.590734 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 98.324434 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.384080 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.384080 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 188 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.734375 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 11443 # Number of tag accesses -system.cpu.icache.tags.data_accesses 11443 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 5333 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 5333 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 5333 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 5333 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 5333 # number of overall hits -system.cpu.icache.overall_hits::total 5333 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 259 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 259 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 259 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 259 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 259 # number of overall misses -system.cpu.icache.overall_misses::total 259 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 27828000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 27828000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 27828000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 27828000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 27828000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 27828000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5592 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5592 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5592 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5592 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5592 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5592 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.046316 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.046316 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.046316 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.046316 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.046316 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.046316 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 107444.015444 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 107444.015444 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 107444.015444 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 107444.015444 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 107444.015444 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 107444.015444 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 259 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 259 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 259 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 259 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 259 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27310000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 27310000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27310000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 27310000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27310000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 27310000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.046316 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.046316 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.046316 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 105444.015444 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 105444.015444 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 105444.015444 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 105444.015444 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 105444.015444 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 105444.015444 # average overall mshr miss latency -system.l2bus.snoop_filter.tot_requests 468 # Total number of requests made to the snoop filter. -system.l2bus.snoop_filter.hit_single_requests 73 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.l2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states -system.l2bus.trans_dist::ReadResp 315 # Transaction distribution -system.l2bus.trans_dist::CleanEvict 71 # Transaction distribution -system.l2bus.trans_dist::ReadExReq 82 # Transaction distribution -system.l2bus.trans_dist::ReadExResp 82 # Transaction distribution -system.l2bus.trans_dist::ReadSharedReq 315 # Transaction distribution -system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 589 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_count::total 865 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 16576 # Cumulative packet size per connected master and slave (bytes) -system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) -system.l2bus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) -system.l2bus.snoops 0 # Total snoops (count) -system.l2bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.l2bus.snoop_fanout::samples 397 # Request fanout histogram -system.l2bus.snoop_fanout::mean 0.007557 # Request fanout histogram -system.l2bus.snoop_fanout::stdev 0.086709 # Request fanout histogram -system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::0 394 99.24% 99.24% # Request fanout histogram -system.l2bus.snoop_fanout::1 3 0.76% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram -system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram -system.l2bus.snoop_fanout::total 397 # Request fanout histogram -system.l2bus.reqLayer0.occupancy 468000 # Layer occupancy (ticks) -system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.l2bus.respLayer0.occupancy 777000 # Layer occupancy (ticks) -system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%) -system.l2bus.respLayer1.occupancy 414000 # Layer occupancy (ticks) -system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states -system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 201.052259 # Cycle average of tags in use -system.l2cache.tags.total_refs 73 # Total number of references to valid blocks. -system.l2cache.tags.sampled_refs 394 # Sample count of references to valid blocks. -system.l2cache.tags.avg_refs 0.185279 # Average number of references to valid blocks. -system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 118.133782 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 82.918477 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.028841 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.020244 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.049085 # Average percentage of cache occupancy -system.l2cache.tags.occ_task_id_blocks::1024 394 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::1 332 # Occupied blocks per task id -system.l2cache.tags.occ_task_id_percent::1024 0.096191 # Percentage of cache occupancy per task id -system.l2cache.tags.tag_accesses 4130 # Number of tag accesses -system.l2cache.tags.data_accesses 4130 # Number of data accesses -system.l2cache.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states -system.l2cache.ReadSharedReq_hits::cpu.inst 2 # number of ReadSharedReq hits -system.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits -system.l2cache.ReadSharedReq_hits::total 3 # number of ReadSharedReq hits -system.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits -system.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits -system.l2cache.demand_hits::total 3 # number of demand (read+write) hits -system.l2cache.overall_hits::cpu.inst 2 # number of overall hits -system.l2cache.overall_hits::cpu.data 1 # number of overall hits -system.l2cache.overall_hits::total 3 # number of overall hits -system.l2cache.ReadExReq_misses::cpu.data 82 # number of ReadExReq misses -system.l2cache.ReadExReq_misses::total 82 # number of ReadExReq misses -system.l2cache.ReadSharedReq_misses::cpu.inst 257 # number of ReadSharedReq misses -system.l2cache.ReadSharedReq_misses::cpu.data 55 # number of ReadSharedReq misses -system.l2cache.ReadSharedReq_misses::total 312 # number of ReadSharedReq misses -system.l2cache.demand_misses::cpu.inst 257 # number of demand (read+write) misses -system.l2cache.demand_misses::cpu.data 137 # number of demand (read+write) misses -system.l2cache.demand_misses::total 394 # number of demand (read+write) misses -system.l2cache.overall_misses::cpu.inst 257 # number of overall misses -system.l2cache.overall_misses::cpu.data 137 # number of overall misses -system.l2cache.overall_misses::total 394 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 8527000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 8527000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 26487000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.data 6273000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 32760000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 26487000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 14800000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 41287000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 26487000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 14800000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 41287000 # number of overall miss cycles -system.l2cache.ReadExReq_accesses::cpu.data 82 # number of ReadExReq accesses(hits+misses) -system.l2cache.ReadExReq_accesses::total 82 # number of ReadExReq accesses(hits+misses) -system.l2cache.ReadSharedReq_accesses::cpu.inst 259 # number of ReadSharedReq accesses(hits+misses) -system.l2cache.ReadSharedReq_accesses::cpu.data 56 # number of ReadSharedReq accesses(hits+misses) -system.l2cache.ReadSharedReq_accesses::total 315 # number of ReadSharedReq accesses(hits+misses) -system.l2cache.demand_accesses::cpu.inst 259 # number of demand (read+write) accesses -system.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses -system.l2cache.demand_accesses::total 397 # number of demand (read+write) accesses -system.l2cache.overall_accesses::cpu.inst 259 # number of overall (read+write) accesses -system.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses -system.l2cache.overall_accesses::total 397 # number of overall (read+write) accesses -system.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.l2cache.ReadSharedReq_miss_rate::cpu.inst 0.992278 # miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_miss_rate::cpu.data 0.982143 # miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_miss_rate::total 0.990476 # miss rate for ReadSharedReq accesses -system.l2cache.demand_miss_rate::cpu.inst 0.992278 # miss rate for demand accesses -system.l2cache.demand_miss_rate::cpu.data 0.992754 # miss rate for demand accesses -system.l2cache.demand_miss_rate::total 0.992443 # miss rate for demand accesses -system.l2cache.overall_miss_rate::cpu.inst 0.992278 # miss rate for overall accesses -system.l2cache.overall_miss_rate::cpu.data 0.992754 # miss rate for overall accesses -system.l2cache.overall_miss_rate::total 0.992443 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 103987.804878 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 103987.804878 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 103062.256809 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 114054.545455 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 105000 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 103062.256809 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 108029.197080 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 104789.340102 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 103062.256809 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 108029.197080 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 104789.340102 # average overall miss latency -system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2cache.ReadExReq_mshr_misses::cpu.data 82 # number of ReadExReq MSHR misses -system.l2cache.ReadExReq_mshr_misses::total 82 # number of ReadExReq MSHR misses -system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 257 # number of ReadSharedReq MSHR misses -system.l2cache.ReadSharedReq_mshr_misses::cpu.data 55 # number of ReadSharedReq MSHR misses -system.l2cache.ReadSharedReq_mshr_misses::total 312 # number of ReadSharedReq MSHR misses -system.l2cache.demand_mshr_misses::cpu.inst 257 # number of demand (read+write) MSHR misses -system.l2cache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses -system.l2cache.demand_mshr_misses::total 394 # number of demand (read+write) MSHR misses -system.l2cache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses -system.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses -system.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6887000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 6887000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 21347000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5173000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 26520000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 21347000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 12060000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 33407000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 21347000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 12060000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 33407000 # number of overall MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.982143 # mshr miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.990476 # mshr miss rate for ReadSharedReq accesses -system.l2cache.demand_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for demand accesses -system.l2cache.demand_mshr_miss_rate::cpu.data 0.992754 # mshr miss rate for demand accesses -system.l2cache.demand_mshr_miss_rate::total 0.992443 # mshr miss rate for demand accesses -system.l2cache.overall_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for overall accesses -system.l2cache.overall_mshr_miss_rate::cpu.data 0.992754 # mshr miss rate for overall accesses -system.l2cache.overall_mshr_miss_rate::total 0.992443 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 83987.804878 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 83987.804878 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 83062.256809 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 94054.545455 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 85000 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 83062.256809 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 88029.197080 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 84789.340102 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 83062.256809 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 88029.197080 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 84789.340102 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 394 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 312 # Transaction distribution -system.membus.trans_dist::ReadExReq 82 # Transaction distribution -system.membus.trans_dist::ReadExResp 82 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 312 # Transaction distribution -system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 788 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 788 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 25216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 25216 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 394 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 394 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 394 # Request fanout histogram -system.membus.reqLayer0.occupancy 394000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 2102500 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.7 # Layer utilization (%) +sim_seconds 0.000057 +sim_ticks 56511000 +final_tick 56511000 +sim_freq 1000000000000 +host_inst_rate 336003 +host_op_rate 335612 +host_tick_rate 3415114336 +host_mem_usage 648892 +host_seconds 0.02 +sim_insts 5548 +sim_ops 5548 +system.clk_domain.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 56511000 +system.mem_ctrl.bytes_read::cpu.inst 16448 +system.mem_ctrl.bytes_read::cpu.data 8768 +system.mem_ctrl.bytes_read::total 25216 +system.mem_ctrl.bytes_inst_read::cpu.inst 16448 +system.mem_ctrl.bytes_inst_read::total 16448 +system.mem_ctrl.num_reads::cpu.inst 257 +system.mem_ctrl.num_reads::cpu.data 137 +system.mem_ctrl.num_reads::total 394 +system.mem_ctrl.bw_read::cpu.inst 291058378 +system.mem_ctrl.bw_read::cpu.data 155155633 +system.mem_ctrl.bw_read::total 446214011 +system.mem_ctrl.bw_inst_read::cpu.inst 291058378 +system.mem_ctrl.bw_inst_read::total 291058378 +system.mem_ctrl.bw_total::cpu.inst 291058378 +system.mem_ctrl.bw_total::cpu.data 155155633 +system.mem_ctrl.bw_total::total 446214011 +system.mem_ctrl.readReqs 394 +system.mem_ctrl.writeReqs 0 +system.mem_ctrl.readBursts 394 +system.mem_ctrl.writeBursts 0 +system.mem_ctrl.bytesReadDRAM 25216 +system.mem_ctrl.bytesReadWrQ 0 +system.mem_ctrl.bytesWritten 0 +system.mem_ctrl.bytesReadSys 25216 +system.mem_ctrl.bytesWrittenSys 0 +system.mem_ctrl.servicedByWrQ 0 +system.mem_ctrl.mergedWrBursts 0 +system.mem_ctrl.neitherReadNorWriteReqs 0 +system.mem_ctrl.perBankRdBursts::0 21 +system.mem_ctrl.perBankRdBursts::1 7 +system.mem_ctrl.perBankRdBursts::2 1 +system.mem_ctrl.perBankRdBursts::3 7 +system.mem_ctrl.perBankRdBursts::4 0 +system.mem_ctrl.perBankRdBursts::5 69 +system.mem_ctrl.perBankRdBursts::6 79 +system.mem_ctrl.perBankRdBursts::7 62 +system.mem_ctrl.perBankRdBursts::8 32 +system.mem_ctrl.perBankRdBursts::9 17 +system.mem_ctrl.perBankRdBursts::10 9 +system.mem_ctrl.perBankRdBursts::11 47 +system.mem_ctrl.perBankRdBursts::12 10 +system.mem_ctrl.perBankRdBursts::13 21 +system.mem_ctrl.perBankRdBursts::14 5 +system.mem_ctrl.perBankRdBursts::15 7 +system.mem_ctrl.perBankWrBursts::0 0 +system.mem_ctrl.perBankWrBursts::1 0 +system.mem_ctrl.perBankWrBursts::2 0 +system.mem_ctrl.perBankWrBursts::3 0 +system.mem_ctrl.perBankWrBursts::4 0 +system.mem_ctrl.perBankWrBursts::5 0 +system.mem_ctrl.perBankWrBursts::6 0 +system.mem_ctrl.perBankWrBursts::7 0 +system.mem_ctrl.perBankWrBursts::8 0 +system.mem_ctrl.perBankWrBursts::9 0 +system.mem_ctrl.perBankWrBursts::10 0 +system.mem_ctrl.perBankWrBursts::11 0 +system.mem_ctrl.perBankWrBursts::12 0 +system.mem_ctrl.perBankWrBursts::13 0 +system.mem_ctrl.perBankWrBursts::14 0 +system.mem_ctrl.perBankWrBursts::15 0 +system.mem_ctrl.numRdRetry 0 +system.mem_ctrl.numWrRetry 0 +system.mem_ctrl.totGap 56394000 +system.mem_ctrl.readPktSize::0 0 +system.mem_ctrl.readPktSize::1 0 +system.mem_ctrl.readPktSize::2 0 +system.mem_ctrl.readPktSize::3 0 +system.mem_ctrl.readPktSize::4 0 +system.mem_ctrl.readPktSize::5 0 +system.mem_ctrl.readPktSize::6 394 +system.mem_ctrl.writePktSize::0 0 +system.mem_ctrl.writePktSize::1 0 +system.mem_ctrl.writePktSize::2 0 +system.mem_ctrl.writePktSize::3 0 +system.mem_ctrl.writePktSize::4 0 +system.mem_ctrl.writePktSize::5 0 +system.mem_ctrl.writePktSize::6 0 +system.mem_ctrl.rdQLenPdf::0 394 +system.mem_ctrl.rdQLenPdf::1 0 +system.mem_ctrl.rdQLenPdf::2 0 +system.mem_ctrl.rdQLenPdf::3 0 +system.mem_ctrl.rdQLenPdf::4 0 +system.mem_ctrl.rdQLenPdf::5 0 +system.mem_ctrl.rdQLenPdf::6 0 +system.mem_ctrl.rdQLenPdf::7 0 +system.mem_ctrl.rdQLenPdf::8 0 +system.mem_ctrl.rdQLenPdf::9 0 +system.mem_ctrl.rdQLenPdf::10 0 +system.mem_ctrl.rdQLenPdf::11 0 +system.mem_ctrl.rdQLenPdf::12 0 +system.mem_ctrl.rdQLenPdf::13 0 +system.mem_ctrl.rdQLenPdf::14 0 +system.mem_ctrl.rdQLenPdf::15 0 +system.mem_ctrl.rdQLenPdf::16 0 +system.mem_ctrl.rdQLenPdf::17 0 +system.mem_ctrl.rdQLenPdf::18 0 +system.mem_ctrl.rdQLenPdf::19 0 +system.mem_ctrl.rdQLenPdf::20 0 +system.mem_ctrl.rdQLenPdf::21 0 +system.mem_ctrl.rdQLenPdf::22 0 +system.mem_ctrl.rdQLenPdf::23 0 +system.mem_ctrl.rdQLenPdf::24 0 +system.mem_ctrl.rdQLenPdf::25 0 +system.mem_ctrl.rdQLenPdf::26 0 +system.mem_ctrl.rdQLenPdf::27 0 +system.mem_ctrl.rdQLenPdf::28 0 +system.mem_ctrl.rdQLenPdf::29 0 +system.mem_ctrl.rdQLenPdf::30 0 +system.mem_ctrl.rdQLenPdf::31 0 +system.mem_ctrl.wrQLenPdf::0 0 +system.mem_ctrl.wrQLenPdf::1 0 +system.mem_ctrl.wrQLenPdf::2 0 +system.mem_ctrl.wrQLenPdf::3 0 +system.mem_ctrl.wrQLenPdf::4 0 +system.mem_ctrl.wrQLenPdf::5 0 +system.mem_ctrl.wrQLenPdf::6 0 +system.mem_ctrl.wrQLenPdf::7 0 +system.mem_ctrl.wrQLenPdf::8 0 +system.mem_ctrl.wrQLenPdf::9 0 +system.mem_ctrl.wrQLenPdf::10 0 +system.mem_ctrl.wrQLenPdf::11 0 +system.mem_ctrl.wrQLenPdf::12 0 +system.mem_ctrl.wrQLenPdf::13 0 +system.mem_ctrl.wrQLenPdf::14 0 +system.mem_ctrl.wrQLenPdf::15 0 +system.mem_ctrl.wrQLenPdf::16 0 +system.mem_ctrl.wrQLenPdf::17 0 +system.mem_ctrl.wrQLenPdf::18 0 +system.mem_ctrl.wrQLenPdf::19 0 +system.mem_ctrl.wrQLenPdf::20 0 +system.mem_ctrl.wrQLenPdf::21 0 +system.mem_ctrl.wrQLenPdf::22 0 +system.mem_ctrl.wrQLenPdf::23 0 +system.mem_ctrl.wrQLenPdf::24 0 +system.mem_ctrl.wrQLenPdf::25 0 +system.mem_ctrl.wrQLenPdf::26 0 +system.mem_ctrl.wrQLenPdf::27 0 +system.mem_ctrl.wrQLenPdf::28 0 +system.mem_ctrl.wrQLenPdf::29 0 +system.mem_ctrl.wrQLenPdf::30 0 +system.mem_ctrl.wrQLenPdf::31 0 +system.mem_ctrl.wrQLenPdf::32 0 +system.mem_ctrl.wrQLenPdf::33 0 +system.mem_ctrl.wrQLenPdf::34 0 +system.mem_ctrl.wrQLenPdf::35 0 +system.mem_ctrl.wrQLenPdf::36 0 +system.mem_ctrl.wrQLenPdf::37 0 +system.mem_ctrl.wrQLenPdf::38 0 +system.mem_ctrl.wrQLenPdf::39 0 +system.mem_ctrl.wrQLenPdf::40 0 +system.mem_ctrl.wrQLenPdf::41 0 +system.mem_ctrl.wrQLenPdf::42 0 +system.mem_ctrl.wrQLenPdf::43 0 +system.mem_ctrl.wrQLenPdf::44 0 +system.mem_ctrl.wrQLenPdf::45 0 +system.mem_ctrl.wrQLenPdf::46 0 +system.mem_ctrl.wrQLenPdf::47 0 +system.mem_ctrl.wrQLenPdf::48 0 +system.mem_ctrl.wrQLenPdf::49 0 +system.mem_ctrl.wrQLenPdf::50 0 +system.mem_ctrl.wrQLenPdf::51 0 +system.mem_ctrl.wrQLenPdf::52 0 +system.mem_ctrl.wrQLenPdf::53 0 +system.mem_ctrl.wrQLenPdf::54 0 +system.mem_ctrl.wrQLenPdf::55 0 +system.mem_ctrl.wrQLenPdf::56 0 +system.mem_ctrl.wrQLenPdf::57 0 +system.mem_ctrl.wrQLenPdf::58 0 +system.mem_ctrl.wrQLenPdf::59 0 +system.mem_ctrl.wrQLenPdf::60 0 +system.mem_ctrl.wrQLenPdf::61 0 +system.mem_ctrl.wrQLenPdf::62 0 +system.mem_ctrl.wrQLenPdf::63 0 +system.mem_ctrl.bytesPerActivate::samples 98 +system.mem_ctrl.bytesPerActivate::mean 248.816327 +system.mem_ctrl.bytesPerActivate::gmean 183.748429 +system.mem_ctrl.bytesPerActivate::stdev 196.431638 +system.mem_ctrl.bytesPerActivate::0-127 26 26.53% 26.53% +system.mem_ctrl.bytesPerActivate::128-255 31 31.63% 58.16% +system.mem_ctrl.bytesPerActivate::256-383 15 15.31% 73.47% +system.mem_ctrl.bytesPerActivate::384-511 13 13.27% 86.73% +system.mem_ctrl.bytesPerActivate::512-639 9 9.18% 95.92% +system.mem_ctrl.bytesPerActivate::640-767 2 2.04% 97.96% +system.mem_ctrl.bytesPerActivate::896-1023 1 1.02% 98.98% +system.mem_ctrl.bytesPerActivate::1024-1151 1 1.02% 100.00% +system.mem_ctrl.bytesPerActivate::total 98 +system.mem_ctrl.totQLat 5793000 +system.mem_ctrl.totMemAccLat 13180500 +system.mem_ctrl.totBusLat 1970000 +system.mem_ctrl.avgQLat 14703.05 +system.mem_ctrl.avgBusLat 5000.00 +system.mem_ctrl.avgMemAccLat 33453.05 +system.mem_ctrl.avgRdBW 446.21 +system.mem_ctrl.avgWrBW 0.00 +system.mem_ctrl.avgRdBWSys 446.21 +system.mem_ctrl.avgWrBWSys 0.00 +system.mem_ctrl.peakBW 12800.00 +system.mem_ctrl.busUtil 3.49 +system.mem_ctrl.busUtilRead 3.49 +system.mem_ctrl.busUtilWrite 0.00 +system.mem_ctrl.avgRdQLen 1.00 +system.mem_ctrl.avgWrQLen 0.00 +system.mem_ctrl.readRowHits 292 +system.mem_ctrl.writeRowHits 0 +system.mem_ctrl.readRowHitRate 74.11 +system.mem_ctrl.writeRowHitRate nan +system.mem_ctrl.avgGap 143131.98 +system.mem_ctrl.pageHitRate 74.11 +system.mem_ctrl_0.actEnergy 421260 +system.mem_ctrl_0.preEnergy 216315 +system.mem_ctrl_0.readEnergy 1756440 +system.mem_ctrl_0.writeEnergy 0 +system.mem_ctrl_0.refreshEnergy 4302480.000000 +system.mem_ctrl_0.actBackEnergy 4075500 +system.mem_ctrl_0.preBackEnergy 122880 +system.mem_ctrl_0.actPowerDownEnergy 21123630 +system.mem_ctrl_0.prePowerDownEnergy 357120 +system.mem_ctrl_0.selfRefreshEnergy 0 +system.mem_ctrl_0.totalEnergy 32375625 +system.mem_ctrl_0.averagePower 572.905837 +system.mem_ctrl_0.totalIdleTime 47002000 +system.mem_ctrl_0.memoryStateTime::IDLE 71000 +system.mem_ctrl_0.memoryStateTime::REF 1820000 +system.mem_ctrl_0.memoryStateTime::SREF 0 +system.mem_ctrl_0.memoryStateTime::PRE_PDN 929250 +system.mem_ctrl_0.memoryStateTime::ACT 7357750 +system.mem_ctrl_0.memoryStateTime::ACT_PDN 46333000 +system.mem_ctrl_1.actEnergy 307020 +system.mem_ctrl_1.preEnergy 155595 +system.mem_ctrl_1.readEnergy 1056720 +system.mem_ctrl_1.writeEnergy 0 +system.mem_ctrl_1.refreshEnergy 4302480.000000 +system.mem_ctrl_1.actBackEnergy 2785590 +system.mem_ctrl_1.preBackEnergy 293760 +system.mem_ctrl_1.actPowerDownEnergy 20523420 +system.mem_ctrl_1.prePowerDownEnergy 1777920 +system.mem_ctrl_1.selfRefreshEnergy 0 +system.mem_ctrl_1.totalEnergy 31202505 +system.mem_ctrl_1.averagePower 552.146785 +system.mem_ctrl_1.totalIdleTime 49582750 +system.mem_ctrl_1.memoryStateTime::IDLE 557000 +system.mem_ctrl_1.memoryStateTime::REF 1820000 +system.mem_ctrl_1.memoryStateTime::SREF 0 +system.mem_ctrl_1.memoryStateTime::PRE_PDN 4629500 +system.mem_ctrl_1.memoryStateTime::ACT 4495750 +system.mem_ctrl_1.memoryStateTime::ACT_PDN 45008750 +system.pwrStateResidencyTicks::UNDEFINED 56511000 +system.cpu.workload.numSyscalls 11 +system.cpu.pwrStateResidencyTicks::ON 56511000 +system.cpu.numCycles 56511 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 5548 +system.cpu.committedOps 5548 +system.cpu.num_int_alu_accesses 4660 +system.cpu.num_fp_alu_accesses 0 +system.cpu.num_func_calls 146 +system.cpu.num_conditional_control_insts 835 +system.cpu.num_int_insts 4660 +system.cpu.num_fp_insts 0 +system.cpu.num_int_register_reads 10977 +system.cpu.num_int_register_writes 5062 +system.cpu.num_fp_register_reads 0 +system.cpu.num_fp_register_writes 0 +system.cpu.num_mem_refs 1404 +system.cpu.num_load_insts 726 +system.cpu.num_store_insts 678 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 56511 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 1187 +system.cpu.op_class::No_OpClass 173 3.09% 3.09% +system.cpu.op_class::IntAlu 4014 71.79% 74.89% +system.cpu.op_class::IntMult 0 0.00% 74.89% +system.cpu.op_class::IntDiv 0 0.00% 74.89% +system.cpu.op_class::FloatAdd 0 0.00% 74.89% +system.cpu.op_class::FloatCmp 0 0.00% 74.89% +system.cpu.op_class::FloatCvt 0 0.00% 74.89% +system.cpu.op_class::FloatMult 0 0.00% 74.89% +system.cpu.op_class::FloatMultAcc 0 0.00% 74.89% +system.cpu.op_class::FloatDiv 0 0.00% 74.89% +system.cpu.op_class::FloatMisc 0 0.00% 74.89% +system.cpu.op_class::FloatSqrt 0 0.00% 74.89% +system.cpu.op_class::SimdAdd 0 0.00% 74.89% +system.cpu.op_class::SimdAddAcc 0 0.00% 74.89% +system.cpu.op_class::SimdAlu 0 0.00% 74.89% +system.cpu.op_class::SimdCmp 0 0.00% 74.89% +system.cpu.op_class::SimdCvt 0 0.00% 74.89% +system.cpu.op_class::SimdMisc 0 0.00% 74.89% +system.cpu.op_class::SimdMult 0 0.00% 74.89% +system.cpu.op_class::SimdMultAcc 0 0.00% 74.89% +system.cpu.op_class::SimdShift 0 0.00% 74.89% +system.cpu.op_class::SimdShiftAcc 0 0.00% 74.89% +system.cpu.op_class::SimdSqrt 0 0.00% 74.89% +system.cpu.op_class::SimdFloatAdd 0 0.00% 74.89% +system.cpu.op_class::SimdFloatAlu 0 0.00% 74.89% +system.cpu.op_class::SimdFloatCmp 0 0.00% 74.89% +system.cpu.op_class::SimdFloatCvt 0 0.00% 74.89% +system.cpu.op_class::SimdFloatDiv 0 0.00% 74.89% +system.cpu.op_class::SimdFloatMisc 0 0.00% 74.89% +system.cpu.op_class::SimdFloatMult 0 0.00% 74.89% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 74.89% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 74.89% +system.cpu.op_class::MemRead 726 12.99% 87.87% +system.cpu.op_class::MemWrite 678 12.13% 100.00% +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 5591 +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 56511000 +system.cpu.dcache.tags.replacements 0 +system.cpu.dcache.tags.tagsinuse 83.847801 +system.cpu.dcache.tags.total_refs 1253 +system.cpu.dcache.tags.sampled_refs 138 +system.cpu.dcache.tags.avg_refs 9.079710 +system.cpu.dcache.tags.warmup_cycle 0 +system.cpu.dcache.tags.occ_blocks::cpu.data 83.847801 +system.cpu.dcache.tags.occ_percent::cpu.data 0.081883 +system.cpu.dcache.tags.occ_percent::total 0.081883 +system.cpu.dcache.tags.occ_task_id_blocks::1024 138 +system.cpu.dcache.tags.age_task_id_blocks_1024::0 10 +system.cpu.dcache.tags.age_task_id_blocks_1024::1 128 +system.cpu.dcache.tags.occ_task_id_percent::1024 0.134766 +system.cpu.dcache.tags.tag_accesses 2920 +system.cpu.dcache.tags.data_accesses 2920 +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 56511000 +system.cpu.dcache.ReadReq_hits::cpu.data 662 +system.cpu.dcache.ReadReq_hits::total 662 +system.cpu.dcache.WriteReq_hits::cpu.data 591 +system.cpu.dcache.WriteReq_hits::total 591 +system.cpu.dcache.demand_hits::cpu.data 1253 +system.cpu.dcache.demand_hits::total 1253 +system.cpu.dcache.overall_hits::cpu.data 1253 +system.cpu.dcache.overall_hits::total 1253 +system.cpu.dcache.ReadReq_misses::cpu.data 56 +system.cpu.dcache.ReadReq_misses::total 56 +system.cpu.dcache.WriteReq_misses::cpu.data 82 +system.cpu.dcache.WriteReq_misses::total 82 +system.cpu.dcache.demand_misses::cpu.data 138 +system.cpu.dcache.demand_misses::total 138 +system.cpu.dcache.overall_misses::cpu.data 138 +system.cpu.dcache.overall_misses::total 138 +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6576000 +system.cpu.dcache.ReadReq_miss_latency::total 6576000 +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8937000 +system.cpu.dcache.WriteReq_miss_latency::total 8937000 +system.cpu.dcache.demand_miss_latency::cpu.data 15513000 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+system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 25216 +system.membus.pkt_size::total 25216 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 394 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 394 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 394 +system.membus.reqLayer0.occupancy 394000 +system.membus.reqLayer0.utilization 0.7 +system.membus.respLayer0.occupancy 2102500 +system.membus.respLayer0.utilization 3.7 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini index 612b72e20..55e4fb657 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=timing @@ -91,6 +92,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -167,7 +169,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=tests/test-progs/hello/bin/x86/linux/hello cwd= drivers= @@ -180,10 +182,11 @@ executable= gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simerr b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simerr index 2f9507495..1cfcb3e18 100755 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simerr +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simerr @@ -1,3 +1,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simout index 3227a9df4..7864b0cf9 100755 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simout +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/le gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 21:11:23 -gem5 executing on e108600-lin, pid 17668 -command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:23 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87205 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple Global frequency set at 1000000000000 ticks per second Beginning simulation! -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 507841000 because target called exit() +Exiting @ tick 507841000 because exiting with last active thread context diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt index 7797c05db..b34dd3952 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt @@ -1,398 +1,398 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000508 # Number of seconds simulated -sim_ticks 507841000 # Number of ticks simulated -final_tick 507841000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 118772 # Simulator instruction rate (inst/s) -host_op_rate 214398 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10553661963 # Simulator tick rate (ticks/s) -host_mem_usage 651408 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -sim_insts 5712 # Number of instructions simulated -sim_ops 10314 # Number of ops (including micro ops) simulated -system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 507841000 # Cumulative time (in ticks) in various power states -system.mem_ctrl.bytes_read::cpu.inst 58264 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::cpu.data 7167 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::total 65431 # Number of bytes read from this memory -system.mem_ctrl.bytes_inst_read::cpu.inst 58264 # Number of instructions bytes read from this memory -system.mem_ctrl.bytes_inst_read::total 58264 # Number of instructions bytes read from this memory -system.mem_ctrl.bytes_written::cpu.data 7160 # Number of bytes written to this memory -system.mem_ctrl.bytes_written::total 7160 # Number of bytes written to this memory -system.mem_ctrl.num_reads::cpu.inst 7283 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::cpu.data 1084 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::total 8367 # Number of read requests responded to by this memory -system.mem_ctrl.num_writes::cpu.data 941 # Number of write requests responded to by this memory -system.mem_ctrl.num_writes::total 941 # Number of write requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 114728823 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 14112685 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 128841507 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 114728823 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 114728823 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::cpu.data 14098901 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::total 14098901 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 114728823 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 28211586 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 142940409 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.readReqs 8367 # Number of read requests accepted -system.mem_ctrl.writeReqs 941 # Number of write requests accepted -system.mem_ctrl.readBursts 8367 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrl.writeBursts 941 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 525184 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 10304 # Total number of bytes read from write queue -system.mem_ctrl.bytesWritten 7168 # Total number of bytes written to DRAM -system.mem_ctrl.bytesReadSys 65431 # Total read bytes from the system interface side -system.mem_ctrl.bytesWrittenSys 7160 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 161 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 810 # Number of DRAM write bursts merged with an existing one -system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrl.perBankRdBursts::0 277 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::1 4 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::2 227 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::3 102 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::4 1619 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::5 965 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::6 1103 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::7 906 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::8 703 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::9 490 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::10 1059 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::11 59 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::12 11 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::13 489 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::14 78 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::15 114 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::0 10 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::8 3 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::9 54 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::10 34 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::11 7 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::15 4 # Per bank write bursts -system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 507709000 # Total gap between requests -system.mem_ctrl.readPktSize::0 135 # Read request sizes (log2) -system.mem_ctrl.readPktSize::1 14 # Read request sizes (log2) -system.mem_ctrl.readPktSize::2 119 # Read request sizes (log2) -system.mem_ctrl.readPktSize::3 8099 # Read request sizes (log2) -system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::6 0 # Read request sizes (log2) -system.mem_ctrl.writePktSize::0 14 # Write request sizes (log2) -system.mem_ctrl.writePktSize::1 3 # Write request sizes (log2) -system.mem_ctrl.writePktSize::2 63 # Write request sizes (log2) -system.mem_ctrl.writePktSize::3 861 # Write request sizes (log2) -system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 8206 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::15 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::16 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::17 8 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::18 8 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::19 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::20 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::21 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::22 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::23 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::24 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::25 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::26 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::27 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::28 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::29 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::30 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::31 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::32 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 856 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 618.018692 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 421.107711 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 393.969749 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 148 17.29% 17.29% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 75 8.76% 26.05% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 73 8.53% 34.58% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 52 6.07% 40.65% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 57 6.66% 47.31% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 49 5.72% 53.04% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 36 4.21% 57.24% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 15 1.75% 59.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 351 41.00% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 856 # Bytes accessed per row activation -system.mem_ctrl.rdPerTurnAround::samples 7 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::mean 1165.285714 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::gmean 941.793638 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::stdev 714.559471 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::256-383 1 14.29% 14.29% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::384-511 1 14.29% 28.57% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::640-767 1 14.29% 42.86% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1280-1407 1 14.29% 57.14% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1408-1535 1 14.29% 71.43% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1920-2047 1 14.29% 85.71% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::2048-2175 1 14.29% 100.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::total 7 # Reads before turning the bus around for writes -system.mem_ctrl.wrPerTurnAround::samples 7 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::16 7 100.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::total 7 # Writes before turning the bus around for reads -system.mem_ctrl.totQLat 82515500 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 236378000 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 41030000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 10055.51 # Average queueing delay per DRAM burst -system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 28805.51 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 1034.15 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 14.11 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 128.84 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 14.10 # Average system write bandwidth in MiByte/s -system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 8.19 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 8.08 # Data bus utilization in percentage for reads -system.mem_ctrl.busUtilWrite 0.11 # Data bus utilization in percentage for writes -system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 23.79 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 7357 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 98 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 89.65 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate 74.81 # Row buffer hit rate for writes -system.mem_ctrl.avgGap 54545.44 # Average gap between requests -system.mem_ctrl.pageHitRate 89.42 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 3127320 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 1647030 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 37149420 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 52200 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 36263760.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 70559160 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 1716480 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.actPowerDownEnergy 113314290 # Energy for active power-down per rank (pJ) -system.mem_ctrl_0.prePowerDownEnergy 13222080 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_0.selfRefreshEnergy 17426520 # Energy for self refresh per rank (pJ) -system.mem_ctrl_0.totalEnergy 294478260 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 579.862821 # Core power per rank (mW) -system.mem_ctrl_0.totalIdleTime 347720500 # Total Idle time Per DRAM Rank -system.mem_ctrl_0.memoryStateTime::IDLE 1584000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 15358000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::SREF 65707000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 34427500 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 142245250 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 248519250 # Time in different power states -system.mem_ctrl_1.actEnergy 3034500 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 1601490 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 21441420 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 532440 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 39336960.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 51598110 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 1155360 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.actPowerDownEnergy 151289970 # Energy for active power-down per rank (pJ) -system.mem_ctrl_1.prePowerDownEnergy 18740160 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_1.selfRefreshEnergy 3216240 # Energy for self refresh per rank (pJ) -system.mem_ctrl_1.totalEnergy 291946650 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 574.877779 # Core power per rank (mW) -system.mem_ctrl_1.totalIdleTime 391695500 # Total Idle time Per DRAM Rank -system.mem_ctrl_1.memoryStateTime::IDLE 757000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 16646000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::SREF 11100000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 48800500 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 98712250 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 331825250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 507841000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 507841000 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 16000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 507841000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 507841000 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 507841000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 507841 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5712 # Number of instructions committed -system.cpu.committedOps 10314 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 10205 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 221 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 986 # number of instructions that are conditional controls -system.cpu.num_int_insts 10205 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 19296 # number of times the integer registers were read -system.cpu.num_int_register_writes 7977 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 7020 # number of times the CC registers were read -system.cpu.num_cc_register_writes 3825 # number of times the CC registers were written -system.cpu.num_mem_refs 2025 # number of memory refs -system.cpu.num_load_insts 1084 # Number of load instructions -system.cpu.num_store_insts 941 # Number of store instructions -system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 507840.999000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1306 # Number of branches fetched -system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction -system.cpu.op_class::IntAlu 8275 80.23% 80.24% # Class of executed instruction -system.cpu.op_class::IntMult 6 0.06% 80.30% # Class of executed instruction -system.cpu.op_class::IntDiv 7 0.07% 80.37% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::MemRead 1084 10.51% 90.88% # Class of executed instruction -system.cpu.op_class::MemWrite 941 9.12% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 10314 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 507841000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 8367 # Transaction distribution -system.membus.trans_dist::ReadResp 8367 # Transaction distribution -system.membus.trans_dist::WriteReq 941 # Transaction distribution -system.membus.trans_dist::WriteResp 941 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 14566 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.icache_port::total 14566 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 4050 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::total 4050 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 18616 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 58264 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::total 58264 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 14327 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::total 14327 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 72591 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 9308 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 9308 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 9308 # Request fanout histogram -system.membus.reqLayer2.occupancy 10249000 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 2.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 16544750 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 3432250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.7 # Layer utilization (%) +sim_seconds 0.000508 +sim_ticks 507841000 +final_tick 507841000 +sim_freq 1000000000000 +host_inst_rate 110016 +host_op_rate 198569 +host_tick_rate 9773316243 +host_mem_usage 663056 +host_seconds 0.05 +sim_insts 5712 +sim_ops 10314 +system.clk_domain.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 507841000 +system.mem_ctrl.bytes_read::cpu.inst 58264 +system.mem_ctrl.bytes_read::cpu.data 7167 +system.mem_ctrl.bytes_read::total 65431 +system.mem_ctrl.bytes_inst_read::cpu.inst 58264 +system.mem_ctrl.bytes_inst_read::total 58264 +system.mem_ctrl.bytes_written::cpu.data 7160 +system.mem_ctrl.bytes_written::total 7160 +system.mem_ctrl.num_reads::cpu.inst 7283 +system.mem_ctrl.num_reads::cpu.data 1084 +system.mem_ctrl.num_reads::total 8367 +system.mem_ctrl.num_writes::cpu.data 941 +system.mem_ctrl.num_writes::total 941 +system.mem_ctrl.bw_read::cpu.inst 114728823 +system.mem_ctrl.bw_read::cpu.data 14112685 +system.mem_ctrl.bw_read::total 128841507 +system.mem_ctrl.bw_inst_read::cpu.inst 114728823 +system.mem_ctrl.bw_inst_read::total 114728823 +system.mem_ctrl.bw_write::cpu.data 14098901 +system.mem_ctrl.bw_write::total 14098901 +system.mem_ctrl.bw_total::cpu.inst 114728823 +system.mem_ctrl.bw_total::cpu.data 28211586 +system.mem_ctrl.bw_total::total 142940409 +system.mem_ctrl.readReqs 8368 +system.mem_ctrl.writeReqs 941 +system.mem_ctrl.readBursts 8368 +system.mem_ctrl.writeBursts 941 +system.mem_ctrl.bytesReadDRAM 525248 +system.mem_ctrl.bytesReadWrQ 10304 +system.mem_ctrl.bytesWritten 7168 +system.mem_ctrl.bytesReadSys 65439 +system.mem_ctrl.bytesWrittenSys 7160 +system.mem_ctrl.servicedByWrQ 161 +system.mem_ctrl.mergedWrBursts 810 +system.mem_ctrl.neitherReadNorWriteReqs 0 +system.mem_ctrl.perBankRdBursts::0 277 +system.mem_ctrl.perBankRdBursts::1 4 +system.mem_ctrl.perBankRdBursts::2 227 +system.mem_ctrl.perBankRdBursts::3 102 +system.mem_ctrl.perBankRdBursts::4 1619 +system.mem_ctrl.perBankRdBursts::5 965 +system.mem_ctrl.perBankRdBursts::6 1103 +system.mem_ctrl.perBankRdBursts::7 906 +system.mem_ctrl.perBankRdBursts::8 703 +system.mem_ctrl.perBankRdBursts::9 491 +system.mem_ctrl.perBankRdBursts::10 1059 +system.mem_ctrl.perBankRdBursts::11 59 +system.mem_ctrl.perBankRdBursts::12 11 +system.mem_ctrl.perBankRdBursts::13 489 +system.mem_ctrl.perBankRdBursts::14 78 +system.mem_ctrl.perBankRdBursts::15 114 +system.mem_ctrl.perBankWrBursts::0 10 +system.mem_ctrl.perBankWrBursts::1 0 +system.mem_ctrl.perBankWrBursts::2 0 +system.mem_ctrl.perBankWrBursts::3 0 +system.mem_ctrl.perBankWrBursts::4 0 +system.mem_ctrl.perBankWrBursts::5 0 +system.mem_ctrl.perBankWrBursts::6 0 +system.mem_ctrl.perBankWrBursts::7 0 +system.mem_ctrl.perBankWrBursts::8 3 +system.mem_ctrl.perBankWrBursts::9 54 +system.mem_ctrl.perBankWrBursts::10 34 +system.mem_ctrl.perBankWrBursts::11 7 +system.mem_ctrl.perBankWrBursts::12 0 +system.mem_ctrl.perBankWrBursts::13 0 +system.mem_ctrl.perBankWrBursts::14 0 +system.mem_ctrl.perBankWrBursts::15 4 +system.mem_ctrl.numRdRetry 0 +system.mem_ctrl.numWrRetry 0 +system.mem_ctrl.totGap 507764000 +system.mem_ctrl.readPktSize::0 135 +system.mem_ctrl.readPktSize::1 14 +system.mem_ctrl.readPktSize::2 119 +system.mem_ctrl.readPktSize::3 8100 +system.mem_ctrl.readPktSize::4 0 +system.mem_ctrl.readPktSize::5 0 +system.mem_ctrl.readPktSize::6 0 +system.mem_ctrl.writePktSize::0 14 +system.mem_ctrl.writePktSize::1 3 +system.mem_ctrl.writePktSize::2 63 +system.mem_ctrl.writePktSize::3 861 +system.mem_ctrl.writePktSize::4 0 +system.mem_ctrl.writePktSize::5 0 +system.mem_ctrl.writePktSize::6 0 +system.mem_ctrl.rdQLenPdf::0 8207 +system.mem_ctrl.rdQLenPdf::1 0 +system.mem_ctrl.rdQLenPdf::2 0 +system.mem_ctrl.rdQLenPdf::3 0 +system.mem_ctrl.rdQLenPdf::4 0 +system.mem_ctrl.rdQLenPdf::5 0 +system.mem_ctrl.rdQLenPdf::6 0 +system.mem_ctrl.rdQLenPdf::7 0 +system.mem_ctrl.rdQLenPdf::8 0 +system.mem_ctrl.rdQLenPdf::9 0 +system.mem_ctrl.rdQLenPdf::10 0 +system.mem_ctrl.rdQLenPdf::11 0 +system.mem_ctrl.rdQLenPdf::12 0 +system.mem_ctrl.rdQLenPdf::13 0 +system.mem_ctrl.rdQLenPdf::14 0 +system.mem_ctrl.rdQLenPdf::15 0 +system.mem_ctrl.rdQLenPdf::16 0 +system.mem_ctrl.rdQLenPdf::17 0 +system.mem_ctrl.rdQLenPdf::18 0 +system.mem_ctrl.rdQLenPdf::19 0 +system.mem_ctrl.rdQLenPdf::20 0 +system.mem_ctrl.rdQLenPdf::21 0 +system.mem_ctrl.rdQLenPdf::22 0 +system.mem_ctrl.rdQLenPdf::23 0 +system.mem_ctrl.rdQLenPdf::24 0 +system.mem_ctrl.rdQLenPdf::25 0 +system.mem_ctrl.rdQLenPdf::26 0 +system.mem_ctrl.rdQLenPdf::27 0 +system.mem_ctrl.rdQLenPdf::28 0 +system.mem_ctrl.rdQLenPdf::29 0 +system.mem_ctrl.rdQLenPdf::30 0 +system.mem_ctrl.rdQLenPdf::31 0 +system.mem_ctrl.wrQLenPdf::0 1 +system.mem_ctrl.wrQLenPdf::1 1 +system.mem_ctrl.wrQLenPdf::2 1 +system.mem_ctrl.wrQLenPdf::3 1 +system.mem_ctrl.wrQLenPdf::4 1 +system.mem_ctrl.wrQLenPdf::5 1 +system.mem_ctrl.wrQLenPdf::6 1 +system.mem_ctrl.wrQLenPdf::7 1 +system.mem_ctrl.wrQLenPdf::8 1 +system.mem_ctrl.wrQLenPdf::9 1 +system.mem_ctrl.wrQLenPdf::10 1 +system.mem_ctrl.wrQLenPdf::11 1 +system.mem_ctrl.wrQLenPdf::12 1 +system.mem_ctrl.wrQLenPdf::13 1 +system.mem_ctrl.wrQLenPdf::14 1 +system.mem_ctrl.wrQLenPdf::15 1 +system.mem_ctrl.wrQLenPdf::16 1 +system.mem_ctrl.wrQLenPdf::17 8 +system.mem_ctrl.wrQLenPdf::18 8 +system.mem_ctrl.wrQLenPdf::19 7 +system.mem_ctrl.wrQLenPdf::20 7 +system.mem_ctrl.wrQLenPdf::21 7 +system.mem_ctrl.wrQLenPdf::22 7 +system.mem_ctrl.wrQLenPdf::23 7 +system.mem_ctrl.wrQLenPdf::24 7 +system.mem_ctrl.wrQLenPdf::25 7 +system.mem_ctrl.wrQLenPdf::26 7 +system.mem_ctrl.wrQLenPdf::27 7 +system.mem_ctrl.wrQLenPdf::28 7 +system.mem_ctrl.wrQLenPdf::29 7 +system.mem_ctrl.wrQLenPdf::30 7 +system.mem_ctrl.wrQLenPdf::31 7 +system.mem_ctrl.wrQLenPdf::32 7 +system.mem_ctrl.wrQLenPdf::33 0 +system.mem_ctrl.wrQLenPdf::34 0 +system.mem_ctrl.wrQLenPdf::35 0 +system.mem_ctrl.wrQLenPdf::36 0 +system.mem_ctrl.wrQLenPdf::37 0 +system.mem_ctrl.wrQLenPdf::38 0 +system.mem_ctrl.wrQLenPdf::39 0 +system.mem_ctrl.wrQLenPdf::40 0 +system.mem_ctrl.wrQLenPdf::41 0 +system.mem_ctrl.wrQLenPdf::42 0 +system.mem_ctrl.wrQLenPdf::43 0 +system.mem_ctrl.wrQLenPdf::44 0 +system.mem_ctrl.wrQLenPdf::45 0 +system.mem_ctrl.wrQLenPdf::46 0 +system.mem_ctrl.wrQLenPdf::47 0 +system.mem_ctrl.wrQLenPdf::48 0 +system.mem_ctrl.wrQLenPdf::49 0 +system.mem_ctrl.wrQLenPdf::50 0 +system.mem_ctrl.wrQLenPdf::51 0 +system.mem_ctrl.wrQLenPdf::52 0 +system.mem_ctrl.wrQLenPdf::53 0 +system.mem_ctrl.wrQLenPdf::54 0 +system.mem_ctrl.wrQLenPdf::55 0 +system.mem_ctrl.wrQLenPdf::56 0 +system.mem_ctrl.wrQLenPdf::57 0 +system.mem_ctrl.wrQLenPdf::58 0 +system.mem_ctrl.wrQLenPdf::59 0 +system.mem_ctrl.wrQLenPdf::60 0 +system.mem_ctrl.wrQLenPdf::61 0 +system.mem_ctrl.wrQLenPdf::62 0 +system.mem_ctrl.wrQLenPdf::63 0 +system.mem_ctrl.bytesPerActivate::samples 856 +system.mem_ctrl.bytesPerActivate::mean 618.018692 +system.mem_ctrl.bytesPerActivate::gmean 421.107711 +system.mem_ctrl.bytesPerActivate::stdev 393.969749 +system.mem_ctrl.bytesPerActivate::0-127 148 17.29% 17.29% +system.mem_ctrl.bytesPerActivate::128-255 75 8.76% 26.05% +system.mem_ctrl.bytesPerActivate::256-383 73 8.53% 34.58% +system.mem_ctrl.bytesPerActivate::384-511 52 6.07% 40.65% +system.mem_ctrl.bytesPerActivate::512-639 57 6.66% 47.31% +system.mem_ctrl.bytesPerActivate::640-767 49 5.72% 53.04% +system.mem_ctrl.bytesPerActivate::768-895 36 4.21% 57.24% +system.mem_ctrl.bytesPerActivate::896-1023 15 1.75% 59.00% +system.mem_ctrl.bytesPerActivate::1024-1151 351 41.00% 100.00% +system.mem_ctrl.bytesPerActivate::total 856 +system.mem_ctrl.rdPerTurnAround::samples 7 +system.mem_ctrl.rdPerTurnAround::mean 1165.285714 +system.mem_ctrl.rdPerTurnAround::gmean 941.793638 +system.mem_ctrl.rdPerTurnAround::stdev 714.559471 +system.mem_ctrl.rdPerTurnAround::256-383 1 14.29% 14.29% +system.mem_ctrl.rdPerTurnAround::384-511 1 14.29% 28.57% +system.mem_ctrl.rdPerTurnAround::640-767 1 14.29% 42.86% +system.mem_ctrl.rdPerTurnAround::1280-1407 1 14.29% 57.14% +system.mem_ctrl.rdPerTurnAround::1408-1535 1 14.29% 71.43% +system.mem_ctrl.rdPerTurnAround::1920-2047 1 14.29% 85.71% +system.mem_ctrl.rdPerTurnAround::2048-2175 1 14.29% 100.00% +system.mem_ctrl.rdPerTurnAround::total 7 +system.mem_ctrl.wrPerTurnAround::samples 7 +system.mem_ctrl.wrPerTurnAround::mean 16 +system.mem_ctrl.wrPerTurnAround::gmean 16.000000 +system.mem_ctrl.wrPerTurnAround::16 7 100.00% 100.00% +system.mem_ctrl.wrPerTurnAround::total 7 +system.mem_ctrl.totQLat 82521500 +system.mem_ctrl.totMemAccLat 236402750 +system.mem_ctrl.totBusLat 41035000 +system.mem_ctrl.avgQLat 10055.01 +system.mem_ctrl.avgBusLat 5000.00 +system.mem_ctrl.avgMemAccLat 28805.01 +system.mem_ctrl.avgRdBW 1034.28 +system.mem_ctrl.avgWrBW 14.11 +system.mem_ctrl.avgRdBWSys 128.86 +system.mem_ctrl.avgWrBWSys 14.10 +system.mem_ctrl.peakBW 12800.00 +system.mem_ctrl.busUtil 8.19 +system.mem_ctrl.busUtilRead 8.08 +system.mem_ctrl.busUtilWrite 0.11 +system.mem_ctrl.avgRdQLen 1.00 +system.mem_ctrl.avgWrQLen 23.79 +system.mem_ctrl.readRowHits 7358 +system.mem_ctrl.writeRowHits 98 +system.mem_ctrl.readRowHitRate 89.66 +system.mem_ctrl.writeRowHitRate 74.81 +system.mem_ctrl.avgGap 54545.49 +system.mem_ctrl.pageHitRate 89.42 +system.mem_ctrl_0.actEnergy 3127320 +system.mem_ctrl_0.preEnergy 1647030 +system.mem_ctrl_0.readEnergy 37149420 +system.mem_ctrl_0.writeEnergy 52200 +system.mem_ctrl_0.refreshEnergy 36263760.000000 +system.mem_ctrl_0.actBackEnergy 70559160 +system.mem_ctrl_0.preBackEnergy 1716480 +system.mem_ctrl_0.actPowerDownEnergy 113314290 +system.mem_ctrl_0.prePowerDownEnergy 13222080 +system.mem_ctrl_0.selfRefreshEnergy 17426520 +system.mem_ctrl_0.totalEnergy 294478260 +system.mem_ctrl_0.averagePower 579.862821 +system.mem_ctrl_0.totalIdleTime 347720500 +system.mem_ctrl_0.memoryStateTime::IDLE 1584000 +system.mem_ctrl_0.memoryStateTime::REF 15358000 +system.mem_ctrl_0.memoryStateTime::SREF 65707000 +system.mem_ctrl_0.memoryStateTime::PRE_PDN 34427500 +system.mem_ctrl_0.memoryStateTime::ACT 142245250 +system.mem_ctrl_0.memoryStateTime::ACT_PDN 248519250 +system.mem_ctrl_1.actEnergy 3034500 +system.mem_ctrl_1.preEnergy 1601490 +system.mem_ctrl_1.readEnergy 21441420 +system.mem_ctrl_1.writeEnergy 532440 +system.mem_ctrl_1.refreshEnergy 39336960.000000 +system.mem_ctrl_1.actBackEnergy 51598110 +system.mem_ctrl_1.preBackEnergy 1155360 +system.mem_ctrl_1.actPowerDownEnergy 151289970 +system.mem_ctrl_1.prePowerDownEnergy 18740160 +system.mem_ctrl_1.selfRefreshEnergy 3216240 +system.mem_ctrl_1.totalEnergy 291946650 +system.mem_ctrl_1.averagePower 574.877779 +system.mem_ctrl_1.totalIdleTime 391725750 +system.mem_ctrl_1.memoryStateTime::IDLE 757000 +system.mem_ctrl_1.memoryStateTime::REF 16646000 +system.mem_ctrl_1.memoryStateTime::SREF 11100000 +system.mem_ctrl_1.memoryStateTime::PRE_PDN 48800500 +system.mem_ctrl_1.memoryStateTime::ACT 98712250 +system.mem_ctrl_1.memoryStateTime::ACT_PDN 331825250 +system.pwrStateResidencyTicks::UNDEFINED 507841000 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 507841000 +system.cpu.apic_clk_domain.clock 16000 +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 507841000 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 507841000 +system.cpu.workload.numSyscalls 11 +system.cpu.pwrStateResidencyTicks::ON 507841000 +system.cpu.numCycles 507841 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 5712 +system.cpu.committedOps 10314 +system.cpu.num_int_alu_accesses 10205 +system.cpu.num_fp_alu_accesses 0 +system.cpu.num_func_calls 221 +system.cpu.num_conditional_control_insts 986 +system.cpu.num_int_insts 10205 +system.cpu.num_fp_insts 0 +system.cpu.num_int_register_reads 19296 +system.cpu.num_int_register_writes 7977 +system.cpu.num_fp_register_reads 0 +system.cpu.num_fp_register_writes 0 +system.cpu.num_cc_register_reads 7020 +system.cpu.num_cc_register_writes 3825 +system.cpu.num_mem_refs 2025 +system.cpu.num_load_insts 1084 +system.cpu.num_store_insts 941 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 507841 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 1306 +system.cpu.op_class::No_OpClass 1 0.01% 0.01% +system.cpu.op_class::IntAlu 8275 80.23% 80.24% +system.cpu.op_class::IntMult 6 0.06% 80.30% +system.cpu.op_class::IntDiv 7 0.07% 80.37% +system.cpu.op_class::FloatAdd 0 0.00% 80.37% +system.cpu.op_class::FloatCmp 0 0.00% 80.37% +system.cpu.op_class::FloatCvt 0 0.00% 80.37% +system.cpu.op_class::FloatMult 0 0.00% 80.37% +system.cpu.op_class::FloatMultAcc 0 0.00% 80.37% +system.cpu.op_class::FloatDiv 0 0.00% 80.37% +system.cpu.op_class::FloatMisc 0 0.00% 80.37% +system.cpu.op_class::FloatSqrt 0 0.00% 80.37% +system.cpu.op_class::SimdAdd 0 0.00% 80.37% +system.cpu.op_class::SimdAddAcc 0 0.00% 80.37% +system.cpu.op_class::SimdAlu 0 0.00% 80.37% +system.cpu.op_class::SimdCmp 0 0.00% 80.37% +system.cpu.op_class::SimdCvt 0 0.00% 80.37% +system.cpu.op_class::SimdMisc 0 0.00% 80.37% +system.cpu.op_class::SimdMult 0 0.00% 80.37% +system.cpu.op_class::SimdMultAcc 0 0.00% 80.37% +system.cpu.op_class::SimdShift 0 0.00% 80.37% +system.cpu.op_class::SimdShiftAcc 0 0.00% 80.37% +system.cpu.op_class::SimdSqrt 0 0.00% 80.37% +system.cpu.op_class::SimdFloatAdd 0 0.00% 80.37% +system.cpu.op_class::SimdFloatAlu 0 0.00% 80.37% +system.cpu.op_class::SimdFloatCmp 0 0.00% 80.37% +system.cpu.op_class::SimdFloatCvt 0 0.00% 80.37% +system.cpu.op_class::SimdFloatDiv 0 0.00% 80.37% +system.cpu.op_class::SimdFloatMisc 0 0.00% 80.37% +system.cpu.op_class::SimdFloatMult 0 0.00% 80.37% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 80.37% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 80.37% +system.cpu.op_class::MemRead 1084 10.51% 90.88% +system.cpu.op_class::MemWrite 941 9.12% 100.00% +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 10314 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 507841000 +system.membus.trans_dist::ReadReq 8368 +system.membus.trans_dist::ReadResp 8367 +system.membus.trans_dist::WriteReq 941 +system.membus.trans_dist::WriteResp 941 +system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 14567 +system.membus.pkt_count_system.cpu.icache_port::total 14567 +system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 4050 +system.membus.pkt_count_system.cpu.dcache_port::total 4050 +system.membus.pkt_count::total 18617 +system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 58264 +system.membus.pkt_size_system.cpu.icache_port::total 58264 +system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 14327 +system.membus.pkt_size_system.cpu.dcache_port::total 14327 +system.membus.pkt_size::total 72591 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 9309 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 9309 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 9309 +system.membus.reqLayer2.occupancy 10250000 +system.membus.reqLayer2.utilization 2.0 +system.membus.respLayer0.occupancy 16544750 +system.membus.respLayer0.utilization 3.3 +system.membus.respLayer1.occupancy 3432250 +system.membus.respLayer1.utilization 0.7 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini index c3a9301a3..be3d0013c 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=timing @@ -91,6 +92,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -110,10 +112,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -127,6 +129,7 @@ response_latency=2 sequential_access=false size=65536 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -139,15 +142,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=65536 +tag_latency=2 [system.cpu.dtb] type=X86TLB @@ -175,10 +179,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -192,6 +196,7 @@ response_latency=2 sequential_access=false size=16384 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -204,15 +209,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=16384 +tag_latency=2 [system.cpu.interrupts] type=X86LocalApic @@ -259,7 +265,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=tests/test-progs/hello/bin/x86/linux/hello cwd= drivers= @@ -272,10 +278,11 @@ executable= gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -325,10 +332,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -342,6 +349,7 @@ response_latency=20 sequential_access=false size=262144 system=system +tag_latency=20 tags=system.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -354,15 +362,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=20 [system.mem_ctrl] type=DRAMCtrl diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simerr b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simerr index 2f9507495..1cfcb3e18 100755 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simerr +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simerr @@ -1,3 +1,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simout index 736ff89ea..51ea33107 100755 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simout +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/le gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 21:09:22 -gem5 executing on e108600-lin, pid 17647 -command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:21 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87157 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level Global frequency set at 1000000000000 ticks per second Beginning simulation! -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 58513000 because target called exit() +Exiting @ tick 58513000 because exiting with last active thread context diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt index c7497d010..5f55051fc 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt @@ -1,722 +1,722 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000059 # Number of seconds simulated -sim_ticks 58513000 # Number of ticks simulated -final_tick 58513000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 297973 # Simulator instruction rate (inst/s) -host_op_rate 537391 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3045372421 # Simulator tick rate (ticks/s) -host_mem_usage 656016 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -sim_insts 5712 # Number of instructions simulated -sim_ops 10314 # Number of ops (including micro ops) simulated -system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.mem_ctrl.bytes_read::cpu.inst 14656 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::cpu.data 8640 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::total 23296 # Number of bytes read from this memory -system.mem_ctrl.bytes_inst_read::cpu.inst 14656 # Number of instructions bytes read from this memory -system.mem_ctrl.bytes_inst_read::total 14656 # Number of instructions bytes read from this memory -system.mem_ctrl.num_reads::cpu.inst 229 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::cpu.data 135 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::total 364 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 250474254 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 147659494 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 398133748 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 250474254 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 250474254 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 250474254 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 147659494 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 398133748 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.readReqs 364 # Number of read requests accepted -system.mem_ctrl.writeReqs 0 # Number of write requests accepted -system.mem_ctrl.readBursts 364 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 23296 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue -system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM -system.mem_ctrl.bytesReadSys 23296 # Total read bytes from the system interface side -system.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrl.perBankRdBursts::0 30 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::1 1 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::2 5 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::3 8 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::4 43 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::5 40 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::6 13 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::7 24 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::8 17 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::9 71 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::10 62 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::11 14 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::12 2 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::13 14 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::14 4 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::15 16 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts -system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 58376000 # Total gap between requests -system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::6 364 # Read request sizes (log2) -system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 364 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 108 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 199.703704 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 135.091179 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 199.282229 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 52 48.15% 48.15% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 21 19.44% 67.59% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 15 13.89% 81.48% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 8 7.41% 88.89% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 7 6.48% 95.37% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 2 1.85% 97.22% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 1 0.93% 98.15% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 1 0.93% 99.07% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 1 0.93% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 108 # Bytes accessed per row activation -system.mem_ctrl.totQLat 5858750 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 12683750 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 1820000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 16095.47 # Average queueing delay per DRAM burst -system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 34845.47 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 398.13 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 398.13 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 3.11 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 3.11 # Data bus utilization in percentage for reads -system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 248 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 68.13 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 160373.63 # Average gap between requests -system.mem_ctrl.pageHitRate 68.13 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 292740 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 136620 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 1170960 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 2975970 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 96960 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.actPowerDownEnergy 20164320 # Energy for active power-down per rank (pJ) -system.mem_ctrl_0.prePowerDownEnergy 2885760 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrl_0.totalEnergy 32025810 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 547.321100 # Core power per rank (mW) -system.mem_ctrl_0.totalIdleTime 51467750 # Total Idle time Per DRAM Rank -system.mem_ctrl_0.memoryStateTime::IDLE 59000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 7513000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 4902000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 44219000 # Time in different power states -system.mem_ctrl_1.actEnergy 535500 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 273240 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 1428000 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 3735210 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 150720 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.actPowerDownEnergy 22328040 # Energy for active power-down per rank (pJ) -system.mem_ctrl_1.prePowerDownEnergy 370560 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrl_1.totalEnergy 33123750 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 566.084895 # Core power per rank (mW) -system.mem_ctrl_1.totalIdleTime 49870500 # Total Idle time Per DRAM Rank -system.mem_ctrl_1.memoryStateTime::IDLE 184000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 965000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 6563000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 48981000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 16000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 58513000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 58513 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5712 # Number of instructions committed -system.cpu.committedOps 10314 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 10205 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 221 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 986 # number of instructions that are conditional controls -system.cpu.num_int_insts 10205 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 19296 # number of times the integer registers were read -system.cpu.num_int_register_writes 7977 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 7020 # number of times the CC registers were read -system.cpu.num_cc_register_writes 3825 # number of times the CC registers were written -system.cpu.num_mem_refs 2025 # number of memory refs -system.cpu.num_load_insts 1084 # Number of load instructions -system.cpu.num_store_insts 941 # Number of store instructions -system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 58512.999000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1306 # Number of branches fetched -system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction -system.cpu.op_class::IntAlu 8275 80.23% 80.24% # Class of executed instruction -system.cpu.op_class::IntMult 6 0.06% 80.30% # Class of executed instruction -system.cpu.op_class::IntDiv 7 0.07% 80.37% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 80.37% # Class of executed instruction -system.cpu.op_class::MemRead 1084 10.51% 90.88% # Class of executed instruction -system.cpu.op_class::MemWrite 941 9.12% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 10314 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 81.299644 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1890 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 14 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 81.299644 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.079394 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.079394 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.131836 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4185 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4185 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1028 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1028 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 862 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 862 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1890 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1890 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1890 # number of overall hits -system.cpu.dcache.overall_hits::total 1890 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 56 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 56 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses -system.cpu.dcache.overall_misses::total 135 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6406000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6406000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8602000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8602000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15008000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15008000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15008000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15008000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1084 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1084 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 941 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 941 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2025 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2025 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2025 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2025 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.051661 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.051661 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.083953 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.083953 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.066667 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.066667 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.066667 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.066667 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 114392.857143 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 114392.857143 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 108886.075949 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 108886.075949 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 111170.370370 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 111170.370370 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 111170.370370 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 111170.370370 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 56 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6294000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6294000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8444000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8444000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14738000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14738000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14738000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14738000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051661 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051661 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083953 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083953 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066667 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.066667 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066667 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.066667 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 112392.857143 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 112392.857143 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 106886.075949 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 106886.075949 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 109170.370370 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 109170.370370 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 109170.370370 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 109170.370370 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 58 # number of replacements -system.cpu.icache.tags.tagsinuse 90.704136 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7048 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 235 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 29.991489 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 90.704136 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.354313 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.354313 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 177 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 14801 # Number of tag accesses -system.cpu.icache.tags.data_accesses 14801 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 7048 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7048 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7048 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7048 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7048 # number of overall hits -system.cpu.icache.overall_hits::total 7048 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 235 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 235 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 235 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 235 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 235 # number of overall misses -system.cpu.icache.overall_misses::total 235 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25629000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25629000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25629000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25629000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25629000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25629000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 7283 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 7283 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 7283 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 7283 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 7283 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 7283 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.032267 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.032267 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.032267 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.032267 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.032267 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.032267 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 109059.574468 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 109059.574468 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 109059.574468 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 109059.574468 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 109059.574468 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 109059.574468 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 235 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 235 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 235 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 235 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 235 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 235 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25159000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 25159000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25159000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 25159000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25159000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 25159000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.032267 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.032267 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.032267 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 107059.574468 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 107059.574468 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 107059.574468 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 107059.574468 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 107059.574468 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 107059.574468 # average overall mshr miss latency -system.l2bus.snoop_filter.tot_requests 428 # Total number of requests made to the snoop filter. -system.l2bus.snoop_filter.hit_single_requests 59 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.l2bus.trans_dist::ReadResp 291 # Transaction distribution -system.l2bus.trans_dist::CleanEvict 58 # Transaction distribution -system.l2bus.trans_dist::ReadExReq 79 # Transaction distribution -system.l2bus.trans_dist::ReadExResp 79 # Transaction distribution -system.l2bus.trans_dist::ReadSharedReq 291 # Transaction distribution -system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 528 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_count::total 798 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 15040 # Cumulative packet size per connected master and slave (bytes) -system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes) -system.l2bus.pkt_size::total 23680 # Cumulative packet size per connected master and slave (bytes) -system.l2bus.snoops 0 # Total snoops (count) -system.l2bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.l2bus.snoop_fanout::samples 370 # Request fanout histogram -system.l2bus.snoop_fanout::mean 0.002703 # Request fanout histogram -system.l2bus.snoop_fanout::stdev 0.051988 # Request fanout histogram -system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::0 369 99.73% 99.73% # Request fanout histogram -system.l2bus.snoop_fanout::1 1 0.27% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram -system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram -system.l2bus.snoop_fanout::total 370 # Request fanout histogram -system.l2bus.reqLayer0.occupancy 428000 # Layer occupancy (ticks) -system.l2bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.l2bus.respLayer0.occupancy 705000 # Layer occupancy (ticks) -system.l2bus.respLayer0.utilization 1.2 # Layer utilization (%) -system.l2bus.respLayer1.occupancy 405000 # Layer occupancy (ticks) -system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 187.541609 # Cycle average of tags in use -system.l2cache.tags.total_refs 64 # Total number of references to valid blocks. -system.l2cache.tags.sampled_refs 364 # Sample count of references to valid blocks. -system.l2cache.tags.avg_refs 0.175824 # Average number of references to valid blocks. -system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 106.193515 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 81.348095 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.025926 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.019860 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.045787 # Average percentage of cache occupancy -system.l2cache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id -system.l2cache.tags.occ_task_id_percent::1024 0.088867 # Percentage of cache occupancy per task id -system.l2cache.tags.tag_accesses 3788 # Number of tag accesses -system.l2cache.tags.data_accesses 3788 # Number of data accesses -system.l2cache.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.l2cache.ReadSharedReq_hits::cpu.inst 6 # number of ReadSharedReq hits -system.l2cache.ReadSharedReq_hits::total 6 # number of ReadSharedReq hits -system.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits -system.l2cache.demand_hits::total 6 # number of demand (read+write) hits -system.l2cache.overall_hits::cpu.inst 6 # number of overall hits -system.l2cache.overall_hits::total 6 # number of overall hits -system.l2cache.ReadExReq_misses::cpu.data 79 # number of ReadExReq misses -system.l2cache.ReadExReq_misses::total 79 # number of ReadExReq misses -system.l2cache.ReadSharedReq_misses::cpu.inst 229 # number of ReadSharedReq misses -system.l2cache.ReadSharedReq_misses::cpu.data 56 # number of ReadSharedReq misses -system.l2cache.ReadSharedReq_misses::total 285 # number of ReadSharedReq misses -system.l2cache.demand_misses::cpu.inst 229 # number of demand (read+write) misses -system.l2cache.demand_misses::cpu.data 135 # number of demand (read+write) misses -system.l2cache.demand_misses::total 364 # number of demand (read+write) misses -system.l2cache.overall_misses::cpu.inst 229 # number of overall misses -system.l2cache.overall_misses::cpu.data 135 # number of overall misses -system.l2cache.overall_misses::total 364 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 8207000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 8207000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 24326000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.data 6126000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 30452000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 24326000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 14333000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 38659000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 24326000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 14333000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 38659000 # number of overall miss cycles -system.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses) -system.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses) -system.l2cache.ReadSharedReq_accesses::cpu.inst 235 # number of ReadSharedReq accesses(hits+misses) -system.l2cache.ReadSharedReq_accesses::cpu.data 56 # number of ReadSharedReq accesses(hits+misses) -system.l2cache.ReadSharedReq_accesses::total 291 # number of ReadSharedReq accesses(hits+misses) -system.l2cache.demand_accesses::cpu.inst 235 # number of demand (read+write) accesses -system.l2cache.demand_accesses::cpu.data 135 # number of demand (read+write) accesses -system.l2cache.demand_accesses::total 370 # number of demand (read+write) accesses -system.l2cache.overall_accesses::cpu.inst 235 # number of overall (read+write) accesses -system.l2cache.overall_accesses::cpu.data 135 # number of overall (read+write) accesses -system.l2cache.overall_accesses::total 370 # number of overall (read+write) accesses -system.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.l2cache.ReadSharedReq_miss_rate::cpu.inst 0.974468 # miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_miss_rate::total 0.979381 # miss rate for ReadSharedReq accesses -system.l2cache.demand_miss_rate::cpu.inst 0.974468 # miss rate for demand accesses -system.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.l2cache.demand_miss_rate::total 0.983784 # miss rate for demand accesses -system.l2cache.overall_miss_rate::cpu.inst 0.974468 # miss rate for overall accesses -system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.l2cache.overall_miss_rate::total 0.983784 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 103886.075949 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 103886.075949 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 106227.074236 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 109392.857143 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 106849.122807 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 106227.074236 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 106170.370370 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 106206.043956 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 106227.074236 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 106170.370370 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 106206.043956 # average overall miss latency -system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses -system.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses -system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 229 # number of ReadSharedReq MSHR misses -system.l2cache.ReadSharedReq_mshr_misses::cpu.data 56 # number of ReadSharedReq MSHR misses -system.l2cache.ReadSharedReq_mshr_misses::total 285 # number of ReadSharedReq MSHR misses -system.l2cache.demand_mshr_misses::cpu.inst 229 # number of demand (read+write) MSHR misses -system.l2cache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses -system.l2cache.demand_mshr_misses::total 364 # number of demand (read+write) MSHR misses -system.l2cache.overall_mshr_misses::cpu.inst 229 # number of overall MSHR misses -system.l2cache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses -system.l2cache.overall_mshr_misses::total 364 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6627000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 6627000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19746000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5006000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 24752000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 19746000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 11633000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 31379000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 19746000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 11633000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 31379000 # number of overall MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.979381 # mshr miss rate for ReadSharedReq accesses -system.l2cache.demand_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for demand accesses -system.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.l2cache.demand_mshr_miss_rate::total 0.983784 # mshr miss rate for demand accesses -system.l2cache.overall_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for overall accesses -system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.l2cache.overall_mshr_miss_rate::total 0.983784 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 83886.075949 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 83886.075949 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 86227.074236 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 89392.857143 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 86849.122807 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 86227.074236 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 86170.370370 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 86206.043956 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 86227.074236 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 86170.370370 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 86206.043956 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 364 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 285 # Transaction distribution -system.membus.trans_dist::ReadExReq 79 # Transaction distribution -system.membus.trans_dist::ReadExResp 79 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 285 # Transaction distribution -system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 728 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2cache.mem_side::total 728 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 728 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 23296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2cache.mem_side::total 23296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 23296 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 364 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 364 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 364 # Request fanout histogram -system.membus.reqLayer2.occupancy 364000 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.6 # Layer utilization (%) -system.membus.respLayer0.occupancy 1951250 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.3 # Layer utilization (%) +sim_seconds 0.000059 +sim_ticks 58513000 +final_tick 58513000 +sim_freq 1000000000000 +host_inst_rate 157408 +host_op_rate 284057 +host_tick_rate 1610644917 +host_mem_usage 667152 +host_seconds 0.04 +sim_insts 5712 +sim_ops 10314 +system.clk_domain.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 58513000 +system.mem_ctrl.bytes_read::cpu.inst 14656 +system.mem_ctrl.bytes_read::cpu.data 8640 +system.mem_ctrl.bytes_read::total 23296 +system.mem_ctrl.bytes_inst_read::cpu.inst 14656 +system.mem_ctrl.bytes_inst_read::total 14656 +system.mem_ctrl.num_reads::cpu.inst 229 +system.mem_ctrl.num_reads::cpu.data 135 +system.mem_ctrl.num_reads::total 364 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+system.mem_ctrl.perBankRdBursts::6 13 +system.mem_ctrl.perBankRdBursts::7 24 +system.mem_ctrl.perBankRdBursts::8 17 +system.mem_ctrl.perBankRdBursts::9 71 +system.mem_ctrl.perBankRdBursts::10 62 +system.mem_ctrl.perBankRdBursts::11 14 +system.mem_ctrl.perBankRdBursts::12 2 +system.mem_ctrl.perBankRdBursts::13 14 +system.mem_ctrl.perBankRdBursts::14 4 +system.mem_ctrl.perBankRdBursts::15 16 +system.mem_ctrl.perBankWrBursts::0 0 +system.mem_ctrl.perBankWrBursts::1 0 +system.mem_ctrl.perBankWrBursts::2 0 +system.mem_ctrl.perBankWrBursts::3 0 +system.mem_ctrl.perBankWrBursts::4 0 +system.mem_ctrl.perBankWrBursts::5 0 +system.mem_ctrl.perBankWrBursts::6 0 +system.mem_ctrl.perBankWrBursts::7 0 +system.mem_ctrl.perBankWrBursts::8 0 +system.mem_ctrl.perBankWrBursts::9 0 +system.mem_ctrl.perBankWrBursts::10 0 +system.mem_ctrl.perBankWrBursts::11 0 +system.mem_ctrl.perBankWrBursts::12 0 +system.mem_ctrl.perBankWrBursts::13 0 +system.mem_ctrl.perBankWrBursts::14 0 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+system.mem_ctrl.wrQLenPdf::39 0 +system.mem_ctrl.wrQLenPdf::40 0 +system.mem_ctrl.wrQLenPdf::41 0 +system.mem_ctrl.wrQLenPdf::42 0 +system.mem_ctrl.wrQLenPdf::43 0 +system.mem_ctrl.wrQLenPdf::44 0 +system.mem_ctrl.wrQLenPdf::45 0 +system.mem_ctrl.wrQLenPdf::46 0 +system.mem_ctrl.wrQLenPdf::47 0 +system.mem_ctrl.wrQLenPdf::48 0 +system.mem_ctrl.wrQLenPdf::49 0 +system.mem_ctrl.wrQLenPdf::50 0 +system.mem_ctrl.wrQLenPdf::51 0 +system.mem_ctrl.wrQLenPdf::52 0 +system.mem_ctrl.wrQLenPdf::53 0 +system.mem_ctrl.wrQLenPdf::54 0 +system.mem_ctrl.wrQLenPdf::55 0 +system.mem_ctrl.wrQLenPdf::56 0 +system.mem_ctrl.wrQLenPdf::57 0 +system.mem_ctrl.wrQLenPdf::58 0 +system.mem_ctrl.wrQLenPdf::59 0 +system.mem_ctrl.wrQLenPdf::60 0 +system.mem_ctrl.wrQLenPdf::61 0 +system.mem_ctrl.wrQLenPdf::62 0 +system.mem_ctrl.wrQLenPdf::63 0 +system.mem_ctrl.bytesPerActivate::samples 108 +system.mem_ctrl.bytesPerActivate::mean 199.703704 +system.mem_ctrl.bytesPerActivate::gmean 135.091179 +system.mem_ctrl.bytesPerActivate::stdev 199.282229 +system.mem_ctrl.bytesPerActivate::0-127 52 48.15% 48.15% +system.mem_ctrl.bytesPerActivate::128-255 21 19.44% 67.59% +system.mem_ctrl.bytesPerActivate::256-383 15 13.89% 81.48% +system.mem_ctrl.bytesPerActivate::384-511 8 7.41% 88.89% +system.mem_ctrl.bytesPerActivate::512-639 7 6.48% 95.37% +system.mem_ctrl.bytesPerActivate::640-767 2 1.85% 97.22% +system.mem_ctrl.bytesPerActivate::768-895 1 0.93% 98.15% +system.mem_ctrl.bytesPerActivate::896-1023 1 0.93% 99.07% +system.mem_ctrl.bytesPerActivate::1024-1151 1 0.93% 100.00% +system.mem_ctrl.bytesPerActivate::total 108 +system.mem_ctrl.totQLat 5858750 +system.mem_ctrl.totMemAccLat 12683750 +system.mem_ctrl.totBusLat 1820000 +system.mem_ctrl.avgQLat 16095.47 +system.mem_ctrl.avgBusLat 5000.00 +system.mem_ctrl.avgMemAccLat 34845.47 +system.mem_ctrl.avgRdBW 398.13 +system.mem_ctrl.avgWrBW 0.00 +system.mem_ctrl.avgRdBWSys 398.13 +system.mem_ctrl.avgWrBWSys 0.00 +system.mem_ctrl.peakBW 12800.00 +system.mem_ctrl.busUtil 3.11 +system.mem_ctrl.busUtilRead 3.11 +system.mem_ctrl.busUtilWrite 0.00 +system.mem_ctrl.avgRdQLen 1.00 +system.mem_ctrl.avgWrQLen 0.00 +system.mem_ctrl.readRowHits 248 +system.mem_ctrl.writeRowHits 0 +system.mem_ctrl.readRowHitRate 68.13 +system.mem_ctrl.writeRowHitRate nan +system.mem_ctrl.avgGap 160373.63 +system.mem_ctrl.pageHitRate 68.13 +system.mem_ctrl_0.actEnergy 292740 +system.mem_ctrl_0.preEnergy 136620 +system.mem_ctrl_0.readEnergy 1170960 +system.mem_ctrl_0.writeEnergy 0 +system.mem_ctrl_0.refreshEnergy 4302480.000000 +system.mem_ctrl_0.actBackEnergy 2975970 +system.mem_ctrl_0.preBackEnergy 96960 +system.mem_ctrl_0.actPowerDownEnergy 20164320 +system.mem_ctrl_0.prePowerDownEnergy 2885760 +system.mem_ctrl_0.selfRefreshEnergy 0 +system.mem_ctrl_0.totalEnergy 32025810 +system.mem_ctrl_0.averagePower 547.321100 +system.mem_ctrl_0.totalIdleTime 51467750 +system.mem_ctrl_0.memoryStateTime::IDLE 59000 +system.mem_ctrl_0.memoryStateTime::REF 1820000 +system.mem_ctrl_0.memoryStateTime::SREF 0 +system.mem_ctrl_0.memoryStateTime::PRE_PDN 7513000 +system.mem_ctrl_0.memoryStateTime::ACT 4902000 +system.mem_ctrl_0.memoryStateTime::ACT_PDN 44219000 +system.mem_ctrl_1.actEnergy 535500 +system.mem_ctrl_1.preEnergy 273240 +system.mem_ctrl_1.readEnergy 1428000 +system.mem_ctrl_1.writeEnergy 0 +system.mem_ctrl_1.refreshEnergy 4302480.000000 +system.mem_ctrl_1.actBackEnergy 3735210 +system.mem_ctrl_1.preBackEnergy 150720 +system.mem_ctrl_1.actPowerDownEnergy 22328040 +system.mem_ctrl_1.prePowerDownEnergy 370560 +system.mem_ctrl_1.selfRefreshEnergy 0 +system.mem_ctrl_1.totalEnergy 33123750 +system.mem_ctrl_1.averagePower 566.084895 +system.mem_ctrl_1.totalIdleTime 49870500 +system.mem_ctrl_1.memoryStateTime::IDLE 184000 +system.mem_ctrl_1.memoryStateTime::REF 1820000 +system.mem_ctrl_1.memoryStateTime::SREF 0 +system.mem_ctrl_1.memoryStateTime::PRE_PDN 965000 +system.mem_ctrl_1.memoryStateTime::ACT 6563000 +system.mem_ctrl_1.memoryStateTime::ACT_PDN 48981000 +system.pwrStateResidencyTicks::UNDEFINED 58513000 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58513000 +system.cpu.apic_clk_domain.clock 16000 +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 58513000 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58513000 +system.cpu.workload.numSyscalls 11 +system.cpu.pwrStateResidencyTicks::ON 58513000 +system.cpu.numCycles 58513 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 5712 +system.cpu.committedOps 10314 +system.cpu.num_int_alu_accesses 10205 +system.cpu.num_fp_alu_accesses 0 +system.cpu.num_func_calls 221 +system.cpu.num_conditional_control_insts 986 +system.cpu.num_int_insts 10205 +system.cpu.num_fp_insts 0 +system.cpu.num_int_register_reads 19296 +system.cpu.num_int_register_writes 7977 +system.cpu.num_fp_register_reads 0 +system.cpu.num_fp_register_writes 0 +system.cpu.num_cc_register_reads 7020 +system.cpu.num_cc_register_writes 3825 +system.cpu.num_mem_refs 2025 +system.cpu.num_load_insts 1084 +system.cpu.num_store_insts 941 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 58513 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 1306 +system.cpu.op_class::No_OpClass 1 0.01% 0.01% +system.cpu.op_class::IntAlu 8275 80.23% 80.24% +system.cpu.op_class::IntMult 6 0.06% 80.30% +system.cpu.op_class::IntDiv 7 0.07% 80.37% +system.cpu.op_class::FloatAdd 0 0.00% 80.37% +system.cpu.op_class::FloatCmp 0 0.00% 80.37% +system.cpu.op_class::FloatCvt 0 0.00% 80.37% +system.cpu.op_class::FloatMult 0 0.00% 80.37% +system.cpu.op_class::FloatMultAcc 0 0.00% 80.37% +system.cpu.op_class::FloatDiv 0 0.00% 80.37% +system.cpu.op_class::FloatMisc 0 0.00% 80.37% +system.cpu.op_class::FloatSqrt 0 0.00% 80.37% +system.cpu.op_class::SimdAdd 0 0.00% 80.37% +system.cpu.op_class::SimdAddAcc 0 0.00% 80.37% +system.cpu.op_class::SimdAlu 0 0.00% 80.37% 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+system.membus.pkt_size_system.l2cache.mem_side::total 23296 +system.membus.pkt_size::total 23296 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 364 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 364 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 364 +system.membus.reqLayer2.occupancy 364000 +system.membus.reqLayer2.utilization 0.6 +system.membus.respLayer0.occupancy 1951250 +system.membus.respLayer0.utilization 3.3 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/config.ini b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/config.ini index 66d67b951..634dac451 100644 --- a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/config.ini +++ b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/config.ini @@ -1234,6 +1234,7 @@ type=RubyDirectoryMemory eventq_index=0 numa_high_bit=5 size=536870912 +system=system version=0 [system.dir_cntrl0.probeToCore] diff --git a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simout b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simout index 6c1fcd449..3b8d8439d 100755 --- a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simout +++ b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ru gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 28 2017 16:47:29 -gem5 started Mar 28 2017 16:47:45 -gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 50774 +gem5 compiled Mar 29 2017 16:09:06 +gem5 started Mar 29 2017 16:09:22 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54093 command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/HSAIL_X86/gem5.opt -d build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO Using GPU kernel code file(s) /usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm @@ -19,4 +19,4 @@ Forcing maxCoalescedReqs to 32 (TLB assoc.) keys = 0x7b2bc0, &keys = 0x798998, keys[0] = 23 the gpu says: elloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloe -Exiting @ tick 667407500 because target called exit() +Exiting @ tick 667407500 because exiting with last active thread context diff --git a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt index ef3da5994..8bd8eadec 100644 --- a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt +++ b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000667 sim_ticks 667407500 final_tick 667407500 sim_freq 1000000000000 -host_inst_rate 219740 -host_op_rate 451865 -host_tick_rate 2189959227 -host_mem_usage 1336836 -host_seconds 0.30 +host_inst_rate 212660 +host_op_rate 437306 +host_tick_rate 2119397283 +host_mem_usage 1336868 +host_seconds 0.32 sim_insts 66963 sim_ops 137705 system.voltage_domain.voltage 1 @@ -299,12 +299,12 @@ system.pwrStateResidencyTicks::UNDEFINED 667407500 system.ruby.pwrStateResidencyTicks::UNDEFINED 667407500 system.ruby.outstanding_req_hist_seqr::bucket_size 1 system.ruby.outstanding_req_hist_seqr::max_bucket 9 -system.ruby.outstanding_req_hist_seqr::samples 114203 +system.ruby.outstanding_req_hist_seqr::samples 114204 system.ruby.outstanding_req_hist_seqr::mean 1.000035 system.ruby.outstanding_req_hist_seqr::gmean 1.000024 system.ruby.outstanding_req_hist_seqr::stdev 0.005918 -system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 114199 100.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 114203 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 114200 100.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 114204 system.ruby.outstanding_req_hist_coalsr::bucket_size 1 system.ruby.outstanding_req_hist_coalsr::max_bucket 9 system.ruby.outstanding_req_hist_coalsr::samples 27 @@ -431,8 +431,8 @@ system.cpu0.num_cc_register_writes 42183 system.cpu0.num_mem_refs 27198 system.cpu0.num_load_insts 16684 system.cpu0.num_store_insts 10514 -system.cpu0.num_idle_cycles 4191.003994 -system.cpu0.num_busy_cycles 1330623.996006 +system.cpu0.num_idle_cycles 4191.001994 +system.cpu0.num_busy_cycles 1330623.998006 system.cpu0.not_idle_fraction 0.996860 system.cpu0.idle_fraction 0.003140 system.cpu0.Branches 16199 diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini index 01ff6a1ab..ac0dae266 100644 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini @@ -90,6 +90,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -165,8 +166,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -177,8 +176,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -239,7 +236,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=mcf mcf.in cwd=build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-atomic drivers= @@ -248,14 +245,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/mcf +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/mcf gid=100 -input=/arm/projectscratch/randd/systems/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=55300000000 system=system uid=100 @@ -279,6 +277,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -290,7 +289,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -298,6 +297,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -306,6 +312,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -313,7 +320,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:268435455 +range=0:268435455:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simerr b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simerr index aadc3d011..c0b55d123 100755 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simerr +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simout index fcb337fda..5142942fc 100755 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simout +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-atomi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:38:23 -gem5 executing on e108600-lin, pid 23089 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/10.mcf/arm/linux/simple-atomic +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 17:56:13 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54233 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/10.mcf/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... MCF SPEC version 1.6.I by Andreas Loebel @@ -26,4 +25,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 54141000500 because target called exit() +Exiting @ tick 54141000500 because exiting with last active thread context diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt index c0847e153..5844293a7 100644 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -1,262 +1,262 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.054141 # Number of seconds simulated -sim_ticks 54141000500 # Number of ticks simulated -final_tick 54141000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2113722 # Simulator instruction rate (inst/s) -host_op_rate 2124249 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1263089948 # Simulator tick rate (ticks/s) -host_mem_usage 393096 # Number of bytes of host memory used -host_seconds 42.86 # Real time elapsed on the host -sim_insts 90602408 # Number of instructions simulated -sim_ops 91053639 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 54141000500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 431323084 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 90016598 # Number of bytes read from this memory -system.physmem.bytes_read::total 521339682 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 431323084 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 431323084 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 18908138 # Number of bytes written to this memory -system.physmem.bytes_written::total 18908138 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 107830771 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 22461532 # Number of read requests responded to by this memory -system.physmem.num_reads::total 130292303 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 4738868 # Number of write requests responded to by this memory -system.physmem.num_writes::total 4738868 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7966662604 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1662632703 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9629295306 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7966662604 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7966662604 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 349238799 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 349238799 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7966662604 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2011871502 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9978534106 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 54141000500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 54141000500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 54141000500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 54141000500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 54141000500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 442 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 54141000500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 108282002 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 90602408 # Number of instructions committed -system.cpu.committedOps 91053639 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses -system.cpu.num_func_calls 112245 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15520157 # number of instructions that are conditional controls -system.cpu.num_int_insts 72326352 # number of integer instructions -system.cpu.num_fp_insts 48 # number of float instructions -system.cpu.num_int_register_reads 124257600 # number of times the integer registers were read -system.cpu.num_int_register_writes 52782988 # number of times the integer registers were written -system.cpu.num_fp_register_reads 54 # number of times the floating registers were read -system.cpu.num_fp_register_writes 30 # number of times the floating registers were written -system.cpu.num_cc_register_reads 271814243 # number of times the CC registers were read -system.cpu.num_cc_register_writes 53956115 # number of times the CC registers were written -system.cpu.num_mem_refs 27220755 # number of memory refs -system.cpu.num_load_insts 22475911 # Number of load instructions -system.cpu.num_store_insts 4744844 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 108282001.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 18732305 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 63822829 70.09% 70.09% # Class of executed instruction -system.cpu.op_class::IntMult 10474 0.01% 70.10% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 6 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::MemRead 22475905 24.68% 94.79% # Class of executed instruction -system.cpu.op_class::MemWrite 4744822 5.21% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 6 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 22 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 91054081 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 54141000500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 130287906 # Transaction distribution -system.membus.trans_dist::ReadResp 130291793 # Transaction distribution -system.membus.trans_dist::WriteReq 4734981 # Transaction distribution -system.membus.trans_dist::WriteResp 4734981 # Transaction distribution -system.membus.trans_dist::SoftPFReq 510 # Transaction distribution -system.membus.trans_dist::SoftPFResp 510 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 3887 # Transaction distribution -system.membus.trans_dist::StoreCondReq 3887 # Transaction distribution -system.membus.trans_dist::StoreCondResp 3887 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 215661542 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 54400800 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 270062342 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 431323084 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 108924736 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 540247820 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 135031171 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 135031171 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 135031171 # Request fanout histogram +sim_seconds 0.054141 +sim_ticks 54141000500 +final_tick 54141000500 +sim_freq 1000000000000 +host_inst_rate 903691 +host_op_rate 908191 +host_tick_rate 540015581 +host_mem_usage 404604 +host_seconds 100.26 +sim_insts 90602408 +sim_ops 91053639 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 54141000500 +system.physmem.bytes_read::cpu.inst 431323084 +system.physmem.bytes_read::cpu.data 90016598 +system.physmem.bytes_read::total 521339682 +system.physmem.bytes_inst_read::cpu.inst 431323084 +system.physmem.bytes_inst_read::total 431323084 +system.physmem.bytes_written::cpu.data 18908138 +system.physmem.bytes_written::total 18908138 +system.physmem.num_reads::cpu.inst 107830771 +system.physmem.num_reads::cpu.data 22461532 +system.physmem.num_reads::total 130292303 +system.physmem.num_writes::cpu.data 4738868 +system.physmem.num_writes::total 4738868 +system.physmem.bw_read::cpu.inst 7966662604 +system.physmem.bw_read::cpu.data 1662632703 +system.physmem.bw_read::total 9629295306 +system.physmem.bw_inst_read::cpu.inst 7966662604 +system.physmem.bw_inst_read::total 7966662604 +system.physmem.bw_write::cpu.data 349238799 +system.physmem.bw_write::total 349238799 +system.physmem.bw_total::cpu.inst 7966662604 +system.physmem.bw_total::cpu.data 2011871502 +system.physmem.bw_total::total 9978534106 +system.pwrStateResidencyTicks::UNDEFINED 54141000500 +system.cpu_clk_domain.clock 500 +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 54141000500 +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.hits 0 +system.cpu.dstage2_mmu.stage2_tlb.misses 0 +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 54141000500 +system.cpu.dtb.walker.walks 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dtb.walker.walkRequestOrigin::total 0 +system.cpu.dtb.inst_hits 0 +system.cpu.dtb.inst_misses 0 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.flush_tlb 0 +system.cpu.dtb.flush_tlb_mva 0 +system.cpu.dtb.flush_tlb_mva_asid 0 +system.cpu.dtb.flush_tlb_asid 0 +system.cpu.dtb.flush_entries 0 +system.cpu.dtb.align_faults 0 +system.cpu.dtb.prefetch_faults 0 +system.cpu.dtb.domain_faults 0 +system.cpu.dtb.perms_faults 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.inst_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 54141000500 +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.hits 0 +system.cpu.istage2_mmu.stage2_tlb.misses 0 +system.cpu.istage2_mmu.stage2_tlb.accesses 0 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 54141000500 +system.cpu.itb.walker.walks 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.itb.walker.walkRequestOrigin::total 0 +system.cpu.itb.inst_hits 0 +system.cpu.itb.inst_misses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.flush_tlb 0 +system.cpu.itb.flush_tlb_mva 0 +system.cpu.itb.flush_tlb_mva_asid 0 +system.cpu.itb.flush_tlb_asid 0 +system.cpu.itb.flush_entries 0 +system.cpu.itb.align_faults 0 +system.cpu.itb.prefetch_faults 0 +system.cpu.itb.domain_faults 0 +system.cpu.itb.perms_faults 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.inst_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 442 +system.cpu.pwrStateResidencyTicks::ON 54141000500 +system.cpu.numCycles 108282002 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 90602408 +system.cpu.committedOps 91053639 +system.cpu.num_int_alu_accesses 72326352 +system.cpu.num_fp_alu_accesses 48 +system.cpu.num_func_calls 112245 +system.cpu.num_conditional_control_insts 15520157 +system.cpu.num_int_insts 72326352 +system.cpu.num_fp_insts 48 +system.cpu.num_int_register_reads 124257600 +system.cpu.num_int_register_writes 52782988 +system.cpu.num_fp_register_reads 54 +system.cpu.num_fp_register_writes 30 +system.cpu.num_cc_register_reads 271814243 +system.cpu.num_cc_register_writes 53956115 +system.cpu.num_mem_refs 27220755 +system.cpu.num_load_insts 22475911 +system.cpu.num_store_insts 4744844 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 108282002 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 18732305 +system.cpu.op_class::No_OpClass 0 0.00% 0.00% +system.cpu.op_class::IntAlu 63822829 70.09% 70.09% +system.cpu.op_class::IntMult 10474 0.01% 70.10% +system.cpu.op_class::IntDiv 0 0.00% 70.10% +system.cpu.op_class::FloatAdd 0 0.00% 70.10% +system.cpu.op_class::FloatCmp 0 0.00% 70.10% +system.cpu.op_class::FloatCvt 0 0.00% 70.10% +system.cpu.op_class::FloatMult 0 0.00% 70.10% +system.cpu.op_class::FloatMultAcc 0 0.00% 70.10% +system.cpu.op_class::FloatDiv 0 0.00% 70.10% +system.cpu.op_class::FloatMisc 0 0.00% 70.10% +system.cpu.op_class::FloatSqrt 0 0.00% 70.10% +system.cpu.op_class::SimdAdd 0 0.00% 70.10% +system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% +system.cpu.op_class::SimdAlu 0 0.00% 70.10% +system.cpu.op_class::SimdCmp 0 0.00% 70.10% +system.cpu.op_class::SimdCvt 0 0.00% 70.10% +system.cpu.op_class::SimdMisc 0 0.00% 70.10% +system.cpu.op_class::SimdMult 0 0.00% 70.10% +system.cpu.op_class::SimdMultAcc 0 0.00% 70.10% +system.cpu.op_class::SimdShift 0 0.00% 70.10% +system.cpu.op_class::SimdShiftAcc 0 0.00% 70.10% +system.cpu.op_class::SimdSqrt 0 0.00% 70.10% +system.cpu.op_class::SimdFloatAdd 0 0.00% 70.10% +system.cpu.op_class::SimdFloatAlu 0 0.00% 70.10% +system.cpu.op_class::SimdFloatCmp 0 0.00% 70.10% +system.cpu.op_class::SimdFloatCvt 6 0.00% 70.10% +system.cpu.op_class::SimdFloatDiv 0 0.00% 70.10% +system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10% +system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% +system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% +system.cpu.op_class::MemRead 22475905 24.68% 94.79% +system.cpu.op_class::MemWrite 4744822 5.21% 100.00% +system.cpu.op_class::FloatMemRead 6 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 22 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 91054081 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 54141000500 +system.membus.trans_dist::ReadReq 130287906 +system.membus.trans_dist::ReadResp 130291793 +system.membus.trans_dist::WriteReq 4734981 +system.membus.trans_dist::WriteResp 4734981 +system.membus.trans_dist::SoftPFReq 510 +system.membus.trans_dist::SoftPFResp 510 +system.membus.trans_dist::LoadLockedReq 3887 +system.membus.trans_dist::StoreCondReq 3887 +system.membus.trans_dist::StoreCondResp 3887 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 215661542 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 54400800 +system.membus.pkt_count::total 270062342 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 431323084 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 108924736 +system.membus.pkt_size::total 540247820 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 135031171 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 135031171 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 135031171 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/config.ini index 8e2469e68..65ada4bb2 100644 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/config.ini +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/config.ini @@ -87,6 +87,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -96,14 +97,14 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -117,6 +118,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -129,15 +131,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dstage2_mmu] type=ArmStage2MMU @@ -193,14 +196,14 @@ port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -214,6 +217,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -226,15 +230,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=ArmInterrupts @@ -253,8 +258,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -265,8 +268,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -325,14 +326,14 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -346,6 +347,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -358,15 +360,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -402,7 +405,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=mcf mcf.in cwd=build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-timing drivers= @@ -411,14 +414,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/mcf +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/mcf gid=100 -input=/arm/projectscratch/randd/systems/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=55300000000 system=system uid=100 @@ -442,6 +446,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -453,7 +458,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -461,6 +466,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -469,6 +481,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -476,7 +489,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:268435455 +range=0:268435455:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simerr b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simerr index aadc3d011..c0b55d123 100755 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simerr +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simout b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simout index 70c7c951b..b4d1d6fbf 100755 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simout +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-timin gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:58:41 -gem5 executing on e108600-lin, pid 24094 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/10.mcf/arm/linux/simple-timing +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 17:56:13 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54228 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/10.mcf/arm/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/10.mcf/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... MCF SPEC version 1.6.I by Andreas Loebel @@ -26,4 +25,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 147148719500 because target called exit() +Exiting @ tick 147164058500 because exiting with last active thread context diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index 208468615..54d266736 100644 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -1,673 +1,673 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.147164 # Number of seconds simulated -sim_ticks 147164058500 # Number of ticks simulated -final_tick 147164058500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1482184 # Simulator instruction rate (inst/s) -host_op_rate 1489549 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2408165715 # Simulator tick rate (ticks/s) -host_mem_usage 404112 # Number of bytes of host memory used -host_seconds 61.11 # Real time elapsed on the host -sim_insts 90576862 # Number of instructions simulated -sim_ops 91026991 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 36928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 944832 # Number of bytes read from this memory -system.physmem.bytes_read::total 981760 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 36928 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 36928 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 577 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14763 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 250931 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6420263 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6671194 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 250931 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 250931 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 250931 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6420263 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6671194 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 442 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 147164058500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 294328117 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 90576862 # Number of instructions committed -system.cpu.committedOps 91026991 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses -system.cpu.num_func_calls 112245 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15520157 # number of instructions that are conditional controls -system.cpu.num_int_insts 72326352 # number of integer instructions -system.cpu.num_fp_insts 48 # number of float instructions -system.cpu.num_int_register_reads 124236934 # number of times the integer registers were read -system.cpu.num_int_register_writes 52782988 # number of times the integer registers were written -system.cpu.num_fp_register_reads 54 # number of times the floating registers were read -system.cpu.num_fp_register_writes 30 # number of times the floating registers were written -system.cpu.num_cc_register_reads 339191621 # number of times the CC registers were read -system.cpu.num_cc_register_writes 53956115 # number of times the CC registers were written -system.cpu.num_mem_refs 27220755 # number of memory refs -system.cpu.num_load_insts 22475911 # Number of load instructions -system.cpu.num_store_insts 4744844 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 294328116.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 18732305 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 63822829 70.09% 70.09% # Class of executed instruction -system.cpu.op_class::IntMult 10474 0.01% 70.10% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 6 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::MemRead 22475905 24.68% 94.79% # Class of executed instruction -system.cpu.op_class::MemWrite 4744822 5.21% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 6 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 22 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 91054081 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 942702 # number of replacements -system.cpu.dcache.tags.tagsinuse 3565.461526 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 54459450500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3565.461526 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.870474 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.870474 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1358 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2564 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 55347598 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 55347598 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 21556948 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21556948 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 507 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 507 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 26245320 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26245320 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26245827 # number of overall hits -system.cpu.dcache.overall_hits::total 26245827 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 900187 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 900187 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 46609 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 46609 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 946796 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 946796 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 946799 # number of overall misses -system.cpu.dcache.overall_misses::total 946799 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11713223000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11713223000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1333567500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1333567500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13046790500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13046790500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13046790500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13046790500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22457135 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22457135 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 510 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 510 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 27192116 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 27192116 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 27192626 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 27192626 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040085 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040085 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.009844 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005882 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.005882 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.034819 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.034819 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.034818 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.034818 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13011.988620 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13011.988620 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28611.802442 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28611.802442 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13779.938339 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13779.938339 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13779.894677 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13779.894677 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 942334 # number of writebacks -system.cpu.dcache.writebacks::total 942334 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 900186 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 900186 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46609 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 46609 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 946795 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 946795 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10812989000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10812989000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1286958500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1286958500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 136000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 136000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12099947500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12099947500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12100083500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12100083500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040085 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040085 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009844 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005882 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005882 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034819 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.034819 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034818 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.034818 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12011.949753 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12011.949753 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27611.802442 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27611.802442 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 45333.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 45333.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12779.902196 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12779.902196 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12780.005344 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12780.005344 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 2 # number of replacements -system.cpu.icache.tags.tagsinuse 510.110453 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 107830173 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 180016.983306 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.110453 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.249077 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.249077 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 597 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 552 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.291504 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 215662143 # Number of tag accesses -system.cpu.icache.tags.data_accesses 215662143 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 107830173 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 107830173 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 107830173 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 107830173 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 107830173 # number of overall hits -system.cpu.icache.overall_hits::total 107830173 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 599 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 599 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 599 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses -system.cpu.icache.overall_misses::total 599 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 36670000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 36670000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 36670000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 36670000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 36670000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 36670000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 107830772 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 107830772 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 107830772 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 107830772 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 107830772 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 107830772 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000006 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61218.697830 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61218.697830 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61218.697830 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61218.697830 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61218.697830 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61218.697830 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 2 # number of writebacks -system.cpu.icache.writebacks::total 2 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 599 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 599 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 599 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36071000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 36071000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36071000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 36071000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36071000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 36071000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000006 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60218.697830 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60218.697830 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60218.697830 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 60218.697830 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60218.697830 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 60218.697830 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 10666.571104 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1874647 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 15340 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 122.206454 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.163402 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 10172.407702 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015081 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.310437 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.325518 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15340 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15229 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.468140 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 15135236 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 15135236 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 942334 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 942334 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 32061 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 32061 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 22 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 22 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 899974 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 899974 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 932035 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 932057 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 932035 # number of overall hits -system.cpu.l2cache.overall_hits::total 932057 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 14548 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 14548 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 577 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 577 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 215 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 215 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 577 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 14763 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 15340 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 577 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 14763 # number of overall misses -system.cpu.l2cache.overall_misses::total 15340 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 880404500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 880404500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 34920500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 34920500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13009500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 13009500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 34920500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 893414000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 928334500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 34920500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 893414000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 928334500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 942334 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 942334 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 46609 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 46609 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 599 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 599 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 900189 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 900189 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 599 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 946798 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 947397 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 599 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 946798 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 947397 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.312129 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.312129 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.963272 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.963272 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000239 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000239 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963272 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.015593 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.016192 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963272 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.015593 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.016192 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60517.218862 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60517.218862 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60520.797227 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60520.797227 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60509.302326 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60509.302326 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60520.797227 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60517.103570 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60517.242503 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60520.797227 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60517.103570 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60517.242503 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14548 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 14548 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 577 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 577 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 215 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 215 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 577 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 14763 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 15340 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 577 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 14763 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 15340 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 734924500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 734924500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 29150500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 29150500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10859500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10859500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 29150500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 745784000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 774934500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29150500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 745784000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 774934500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.312129 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.312129 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.963272 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000239 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000239 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015593 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016192 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015593 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016192 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50517.218862 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50517.218862 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50520.797227 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50520.797227 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50509.302326 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50509.302326 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50520.797227 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50517.103570 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50517.242503 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50520.797227 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50517.103570 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50517.242503 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1890101 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 942715 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 942334 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 368 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 46609 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 46609 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 599 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 900189 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1200 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2836298 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2837498 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38464 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120904448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 120942912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 947397 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000132 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.011486 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 947272 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 125 0.01% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 947397 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1887386500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 898500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1420197000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 15340 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 792 # Transaction distribution -system.membus.trans_dist::ReadExReq 14548 # Transaction distribution -system.membus.trans_dist::ReadExResp 14548 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 792 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 30680 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 30680 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 981760 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 981760 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 15340 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 15340 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 15340 # Request fanout histogram -system.membus.reqLayer0.occupancy 15604500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 76700000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +sim_seconds 0.147164 +sim_ticks 147164058500 +final_tick 147164058500 +sim_freq 1000000000000 +host_inst_rate 652695 +host_op_rate 655939 +host_tick_rate 1060461195 +host_mem_usage 414592 +host_seconds 138.77 +sim_insts 90576862 +sim_ops 91026991 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 147164058500 +system.physmem.bytes_read::cpu.inst 36928 +system.physmem.bytes_read::cpu.data 944832 +system.physmem.bytes_read::total 981760 +system.physmem.bytes_inst_read::cpu.inst 36928 +system.physmem.bytes_inst_read::total 36928 +system.physmem.num_reads::cpu.inst 577 +system.physmem.num_reads::cpu.data 14763 +system.physmem.num_reads::total 15340 +system.physmem.bw_read::cpu.inst 250931 +system.physmem.bw_read::cpu.data 6420263 +system.physmem.bw_read::total 6671194 +system.physmem.bw_inst_read::cpu.inst 250931 +system.physmem.bw_inst_read::total 250931 +system.physmem.bw_total::cpu.inst 250931 +system.physmem.bw_total::cpu.data 6420263 +system.physmem.bw_total::total 6671194 +system.pwrStateResidencyTicks::UNDEFINED 147164058500 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0.00% 0.00% +system.cpu.op_class::IntAlu 63822829 70.09% 70.09% +system.cpu.op_class::IntMult 10474 0.01% 70.10% +system.cpu.op_class::IntDiv 0 0.00% 70.10% +system.cpu.op_class::FloatAdd 0 0.00% 70.10% +system.cpu.op_class::FloatCmp 0 0.00% 70.10% +system.cpu.op_class::FloatCvt 0 0.00% 70.10% +system.cpu.op_class::FloatMult 0 0.00% 70.10% +system.cpu.op_class::FloatMultAcc 0 0.00% 70.10% +system.cpu.op_class::FloatDiv 0 0.00% 70.10% +system.cpu.op_class::FloatMisc 0 0.00% 70.10% +system.cpu.op_class::FloatSqrt 0 0.00% 70.10% +system.cpu.op_class::SimdAdd 0 0.00% 70.10% +system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% +system.cpu.op_class::SimdAlu 0 0.00% 70.10% +system.cpu.op_class::SimdCmp 0 0.00% 70.10% +system.cpu.op_class::SimdCvt 0 0.00% 70.10% +system.cpu.op_class::SimdMisc 0 0.00% 70.10% +system.cpu.op_class::SimdMult 0 0.00% 70.10% +system.cpu.op_class::SimdMultAcc 0 0.00% 70.10% +system.cpu.op_class::SimdShift 0 0.00% 70.10% +system.cpu.op_class::SimdShiftAcc 0 0.00% 70.10% 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3565.461526 +system.cpu.dcache.tags.total_refs 26253601 +system.cpu.dcache.tags.sampled_refs 946798 +system.cpu.dcache.tags.avg_refs 27.728830 +system.cpu.dcache.tags.warmup_cycle 54459450500 +system.cpu.dcache.tags.occ_blocks::cpu.data 3565.461526 +system.cpu.dcache.tags.occ_percent::cpu.data 0.870474 +system.cpu.dcache.tags.occ_percent::total 0.870474 +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 +system.cpu.dcache.tags.age_task_id_blocks_1024::0 118 +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1358 +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2564 +system.cpu.dcache.tags.age_task_id_blocks_1024::3 56 +system.cpu.dcache.tags.occ_task_id_percent::1024 1 +system.cpu.dcache.tags.tag_accesses 55347598 +system.cpu.dcache.tags.data_accesses 55347598 +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 147164058500 +system.cpu.dcache.ReadReq_hits::cpu.data 21556948 +system.cpu.dcache.ReadReq_hits::total 21556948 +system.cpu.dcache.WriteReq_hits::cpu.data 4688372 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+system.cpu.toL2Bus.pkt_size::total 120942912 +system.cpu.toL2Bus.snoops 0 +system.cpu.toL2Bus.snoopTraffic 0 +system.cpu.toL2Bus.snoop_fanout::samples 947397 +system.cpu.toL2Bus.snoop_fanout::mean 0.000132 +system.cpu.toL2Bus.snoop_fanout::stdev 0.011486 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 947272 99.99% 99.99% +system.cpu.toL2Bus.snoop_fanout::1 125 0.01% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 1 +system.cpu.toL2Bus.snoop_fanout::total 947397 +system.cpu.toL2Bus.reqLayer0.occupancy 1887386500 +system.cpu.toL2Bus.reqLayer0.utilization 1.3 +system.cpu.toL2Bus.respLayer0.occupancy 898500 +system.cpu.toL2Bus.respLayer0.utilization 0.0 +system.cpu.toL2Bus.respLayer1.occupancy 1420197000 +system.cpu.toL2Bus.respLayer1.utilization 1.0 +system.membus.snoop_filter.tot_requests 15340 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 147164058500 +system.membus.trans_dist::ReadResp 792 +system.membus.trans_dist::ReadExReq 14548 +system.membus.trans_dist::ReadExResp 14548 +system.membus.trans_dist::ReadSharedReq 792 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 30680 +system.membus.pkt_count::total 30680 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 981760 +system.membus.pkt_size::total 981760 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 15340 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 15340 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 15340 +system.membus.reqLayer0.occupancy 15604500 +system.membus.reqLayer0.utilization 0.0 +system.membus.respLayer1.occupancy 76700000 +system.membus.respLayer1.utilization 0.1 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini index c9c77a327..37e37c5a9 100644 --- a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini @@ -88,6 +88,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -118,7 +119,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=mcf mcf.in cwd=build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic drivers= @@ -127,14 +128,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/sparc/linux/mcf +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/sparc/linux/mcf gid=100 -input=/arm/projectscratch/randd/systems/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=55300000000 system=system uid=100 @@ -158,6 +160,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -169,7 +172,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -177,6 +180,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -185,6 +195,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -192,7 +203,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:268435455 +range=0:268435455:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simerr b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simerr index aadc3d011..c0b55d123 100755 --- a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simerr +++ b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simout index 99db763e0..bfb274bdd 100755 --- a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-a gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:30:06 -gem5 started Jul 21 2016 14:30:35 -gem5 executing on e108600-lin, pid 38668 -command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/10.mcf/sparc/linux/simple-atomic +gem5 compiled Apr 3 2017 18:41:19 +gem5 started Apr 3 2017 18:41:41 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 64903 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/10.mcf/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... MCF SPEC version 1.6.I by Andreas Loebel @@ -26,4 +25,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 122215823500 because target called exit() +Exiting @ tick 122215823500 because exiting with last active thread context diff --git a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt index 735a3d4df..505667cfa 100644 --- a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt @@ -1,139 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.122216 # Number of seconds simulated -sim_ticks 122215823500 # Number of ticks simulated -final_tick 122215823500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2760120 # Simulator instruction rate (inst/s) -host_op_rate 2760234 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1383492525 # Simulator tick rate (ticks/s) -host_mem_usage 373928 # Number of bytes of host memory used -host_seconds 88.34 # Real time elapsed on the host -sim_insts 243825150 # Number of instructions simulated -sim_ops 243835265 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 122215823500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 977685992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 328674008 # Number of bytes read from this memory -system.physmem.bytes_read::total 1306360000 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 977685992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 977685992 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 91606089 # Number of bytes written to this memory -system.physmem.bytes_written::total 91606089 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 244421498 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 82220433 # Number of read requests responded to by this memory -system.physmem.num_reads::total 326641931 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 22901951 # Number of write requests responded to by this memory -system.physmem.num_writes::total 22901951 # Number of write requests responded to by this memory -system.physmem.num_other::cpu.data 3886 # Number of other requests responded to by this memory -system.physmem.num_other::total 3886 # Number of other requests responded to by this memory -system.physmem.bw_read::cpu.inst 7999667834 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2689291768 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10688959601 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7999667834 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7999667834 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 749543606 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 749543606 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7999667834 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3438835373 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11438503207 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 122215823500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.numSyscalls 443 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 122215823500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 244431648 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 243825150 # Number of instructions committed -system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses -system.cpu.num_func_calls 4252956 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls -system.cpu.num_int_insts 194726494 # number of integer instructions -system.cpu.num_fp_insts 11630 # number of float instructions -system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read -system.cpu.num_int_register_writes 215451554 # number of times the integer registers were written -system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read -system.cpu.num_fp_register_writes 90 # number of times the floating registers were written -system.cpu.num_mem_refs 105711441 # number of memory refs -system.cpu.num_load_insts 82803521 # Number of load instructions -system.cpu.num_store_insts 22907920 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 244431647.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 29302884 # Number of branches fetched -system.cpu.op_class::No_OpClass 28877736 11.81% 11.81% # Class of executed instruction -system.cpu.op_class::IntAlu 109842388 44.94% 56.75% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatAdd 42 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::MemRead 82803516 33.88% 90.63% # Class of executed instruction -system.cpu.op_class::MemWrite 22896343 9.37% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 11 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 11577 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 244431613 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 122215823500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 326641931 # Transaction distribution -system.membus.trans_dist::ReadResp 326641931 # Transaction distribution -system.membus.trans_dist::WriteReq 22901951 # Transaction distribution -system.membus.trans_dist::WriteResp 22901951 # Transaction distribution -system.membus.trans_dist::SwapReq 3886 # Transaction distribution -system.membus.trans_dist::SwapResp 3886 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 488842996 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 210252540 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 699095536 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 977685992 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 420311185 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1397997177 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 349547768 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 349547768 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 349547768 # Request fanout histogram +sim_seconds 0.122216 +sim_ticks 122215823500 +final_tick 122215823500 +sim_freq 1000000000000 +host_inst_rate 1246885 +host_op_rate 1246936 +host_tick_rate 624993047 +host_mem_usage 386196 +host_seconds 195.55 +sim_insts 243825150 +sim_ops 243835265 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 122215823500 +system.physmem.bytes_read::cpu.inst 977685992 +system.physmem.bytes_read::cpu.data 328674008 +system.physmem.bytes_read::total 1306360000 +system.physmem.bytes_inst_read::cpu.inst 977685992 +system.physmem.bytes_inst_read::total 977685992 +system.physmem.bytes_written::cpu.data 91606089 +system.physmem.bytes_written::total 91606089 +system.physmem.num_reads::cpu.inst 244421498 +system.physmem.num_reads::cpu.data 82220433 +system.physmem.num_reads::total 326641931 +system.physmem.num_writes::cpu.data 22901951 +system.physmem.num_writes::total 22901951 +system.physmem.num_other::cpu.data 3886 +system.physmem.num_other::total 3886 +system.physmem.bw_read::cpu.inst 7999667834 +system.physmem.bw_read::cpu.data 2689291768 +system.physmem.bw_read::total 10688959601 +system.physmem.bw_inst_read::cpu.inst 7999667834 +system.physmem.bw_inst_read::total 7999667834 +system.physmem.bw_write::cpu.data 749543606 +system.physmem.bw_write::total 749543606 +system.physmem.bw_total::cpu.inst 7999667834 +system.physmem.bw_total::cpu.data 3438835373 +system.physmem.bw_total::total 11438503207 +system.pwrStateResidencyTicks::UNDEFINED 122215823500 +system.cpu_clk_domain.clock 500 +system.cpu.workload.numSyscalls 443 +system.cpu.pwrStateResidencyTicks::ON 122215823500 +system.cpu.numCycles 244431648 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 243825150 +system.cpu.committedOps 243835265 +system.cpu.num_int_alu_accesses 194726494 +system.cpu.num_fp_alu_accesses 11630 +system.cpu.num_func_calls 4252956 +system.cpu.num_conditional_control_insts 18619959 +system.cpu.num_int_insts 194726494 +system.cpu.num_fp_insts 11630 +system.cpu.num_int_register_reads 456818988 +system.cpu.num_int_register_writes 215451554 +system.cpu.num_fp_register_reads 23256 +system.cpu.num_fp_register_writes 90 +system.cpu.num_mem_refs 105711441 +system.cpu.num_load_insts 82803521 +system.cpu.num_store_insts 22907920 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 244431648 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 29302884 +system.cpu.op_class::No_OpClass 28877736 11.81% 11.81% +system.cpu.op_class::IntAlu 109842388 44.94% 56.75% +system.cpu.op_class::IntMult 0 0.00% 56.75% +system.cpu.op_class::IntDiv 0 0.00% 56.75% +system.cpu.op_class::FloatAdd 42 0.00% 56.75% +system.cpu.op_class::FloatCmp 0 0.00% 56.75% +system.cpu.op_class::FloatCvt 0 0.00% 56.75% +system.cpu.op_class::FloatMult 0 0.00% 56.75% +system.cpu.op_class::FloatMultAcc 0 0.00% 56.75% +system.cpu.op_class::FloatDiv 0 0.00% 56.75% +system.cpu.op_class::FloatMisc 0 0.00% 56.75% +system.cpu.op_class::FloatSqrt 0 0.00% 56.75% +system.cpu.op_class::SimdAdd 0 0.00% 56.75% +system.cpu.op_class::SimdAddAcc 0 0.00% 56.75% +system.cpu.op_class::SimdAlu 0 0.00% 56.75% +system.cpu.op_class::SimdCmp 0 0.00% 56.75% +system.cpu.op_class::SimdCvt 0 0.00% 56.75% +system.cpu.op_class::SimdMisc 0 0.00% 56.75% +system.cpu.op_class::SimdMult 0 0.00% 56.75% +system.cpu.op_class::SimdMultAcc 0 0.00% 56.75% +system.cpu.op_class::SimdShift 0 0.00% 56.75% +system.cpu.op_class::SimdShiftAcc 0 0.00% 56.75% +system.cpu.op_class::SimdSqrt 0 0.00% 56.75% +system.cpu.op_class::SimdFloatAdd 0 0.00% 56.75% +system.cpu.op_class::SimdFloatAlu 0 0.00% 56.75% +system.cpu.op_class::SimdFloatCmp 0 0.00% 56.75% +system.cpu.op_class::SimdFloatCvt 0 0.00% 56.75% +system.cpu.op_class::SimdFloatDiv 0 0.00% 56.75% +system.cpu.op_class::SimdFloatMisc 0 0.00% 56.75% +system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% +system.cpu.op_class::MemRead 82803516 33.88% 90.63% +system.cpu.op_class::MemWrite 22896343 9.37% 100.00% +system.cpu.op_class::FloatMemRead 11 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 11577 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 244431613 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 122215823500 +system.membus.trans_dist::ReadReq 326641931 +system.membus.trans_dist::ReadResp 326641931 +system.membus.trans_dist::WriteReq 22901951 +system.membus.trans_dist::WriteResp 22901951 +system.membus.trans_dist::SwapReq 3886 +system.membus.trans_dist::SwapResp 3886 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 488842996 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 210252540 +system.membus.pkt_count::total 699095536 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 977685992 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 420311185 +system.membus.pkt_size::total 1397997177 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 349547768 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 349547768 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 349547768 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/config.ini index b442fbc66..92c3012b0 100644 --- a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=atomic @@ -88,6 +89,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -167,7 +169,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=mcf mcf.in cwd=build/X86/tests/opt/quick/se/10.mcf/x86/linux/simple-atomic drivers= @@ -176,14 +178,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/mcf +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/mcf gid=100 -input=/arm/projectscratch/randd/systems/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=55300000000 system=system uid=100 @@ -207,6 +210,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -218,7 +222,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -226,6 +230,13 @@ width=16 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -234,6 +245,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -241,7 +253,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:268435455 +range=0:268435455:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simerr b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simerr index aadc3d011..c0b55d123 100755 --- a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simerr +++ b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simout index 42e1355e1..9dc643081 100755 --- a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simout +++ b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/X86/tests/opt/quick/se/10.mcf/x86/linux/simple-atomi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:35:23 -gem5 started Jul 21 2016 14:36:17 -gem5 executing on e108600-lin, pid 18547 -command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/10.mcf/x86/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/10.mcf/x86/linux/simple-atomic +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:21 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87179 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/10.mcf/x86/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/10.mcf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... MCF SPEC version 1.6.I by Andreas Loebel @@ -26,4 +25,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 168950040000 because target called exit() +Exiting @ tick 168950040000 because exiting with last active thread context diff --git a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt index e47781d66..eabb3db7d 100644 --- a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -1,145 +1,145 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.168950 # Number of seconds simulated -sim_ticks 168950040000 # Number of ticks simulated -final_tick 168950040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1482871 # Simulator instruction rate (inst/s) -host_op_rate 2611098 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1585754680 # Simulator tick rate (ticks/s) -host_mem_usage 400496 # Number of bytes of host memory used -host_seconds 106.54 # Real time elapsed on the host -sim_insts 157988548 # Number of instructions simulated -sim_ops 278192465 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 168950040000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 1741569312 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 717246013 # Number of bytes read from this memory -system.physmem.bytes_read::total 2458815325 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1741569312 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1741569312 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 243173117 # Number of bytes written to this memory -system.physmem.bytes_written::total 243173117 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 217696164 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 90779447 # Number of read requests responded to by this memory -system.physmem.num_reads::total 308475611 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 31439752 # Number of write requests responded to by this memory -system.physmem.num_writes::total 31439752 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 10308191179 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4245314254 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14553505433 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 10308191179 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 10308191179 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1439319677 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1439319677 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 10308191179 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5684633931 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 15992825110 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 168950040000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 168950040000 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 168950040000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 168950040000 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 444 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 168950040000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 337900081 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 157988548 # Number of instructions committed -system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 278169482 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses -system.cpu.num_func_calls 8475189 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls -system.cpu.num_int_insts 278169482 # number of integer instructions -system.cpu.num_fp_insts 40 # number of float instructions -system.cpu.num_int_register_reads 635379407 # number of times the integer registers were read -system.cpu.num_int_register_writes 217447860 # number of times the integer registers were written -system.cpu.num_fp_register_reads 40 # number of times the floating registers were read -system.cpu.num_fp_register_writes 26 # number of times the floating registers were written -system.cpu.num_cc_register_reads 104140596 # number of times the CC registers were read -system.cpu.num_cc_register_writes 61764861 # number of times the CC registers were written -system.cpu.num_mem_refs 122219137 # number of memory refs -system.cpu.num_load_insts 90779385 # Number of load instructions -system.cpu.num_store_insts 31439752 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 337900080.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 29309705 # Number of branches fetched -system.cpu.op_class::No_OpClass 16695 0.01% 0.01% # Class of executed instruction -system.cpu.op_class::IntAlu 155945354 56.06% 56.06% # Class of executed instruction -system.cpu.op_class::IntMult 10938 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::IntDiv 329 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatAdd 12 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::MemRead 90779371 32.63% 88.70% # Class of executed instruction -system.cpu.op_class::MemWrite 31439738 11.30% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 14 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 14 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 278192465 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 168950040000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 308475611 # Transaction distribution -system.membus.trans_dist::ReadResp 308475611 # Transaction distribution -system.membus.trans_dist::WriteReq 31439752 # Transaction distribution -system.membus.trans_dist::WriteResp 31439752 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 435392328 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.icache_port::total 435392328 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 244438398 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::total 244438398 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 679830726 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1741569312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::total 1741569312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 960419130 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::total 960419130 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 2701988442 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 339915363 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 339915363 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 339915363 # Request fanout histogram +sim_seconds 0.168950 +sim_ticks 168950040000 +final_tick 168950040000 +sim_freq 1000000000000 +host_inst_rate 689046 +host_op_rate 1213300 +host_tick_rate 736853372 +host_mem_usage 412400 +host_seconds 229.29 +sim_insts 157988548 +sim_ops 278192465 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 168950040000 +system.physmem.bytes_read::cpu.inst 1741569312 +system.physmem.bytes_read::cpu.data 717246013 +system.physmem.bytes_read::total 2458815325 +system.physmem.bytes_inst_read::cpu.inst 1741569312 +system.physmem.bytes_inst_read::total 1741569312 +system.physmem.bytes_written::cpu.data 243173117 +system.physmem.bytes_written::total 243173117 +system.physmem.num_reads::cpu.inst 217696164 +system.physmem.num_reads::cpu.data 90779447 +system.physmem.num_reads::total 308475611 +system.physmem.num_writes::cpu.data 31439752 +system.physmem.num_writes::total 31439752 +system.physmem.bw_read::cpu.inst 10308191179 +system.physmem.bw_read::cpu.data 4245314254 +system.physmem.bw_read::total 14553505433 +system.physmem.bw_inst_read::cpu.inst 10308191179 +system.physmem.bw_inst_read::total 10308191179 +system.physmem.bw_write::cpu.data 1439319677 +system.physmem.bw_write::total 1439319677 +system.physmem.bw_total::cpu.inst 10308191179 +system.physmem.bw_total::cpu.data 5684633931 +system.physmem.bw_total::total 15992825110 +system.pwrStateResidencyTicks::UNDEFINED 168950040000 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 168950040000 +system.cpu.apic_clk_domain.clock 8000 +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 168950040000 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 168950040000 +system.cpu.workload.numSyscalls 444 +system.cpu.pwrStateResidencyTicks::ON 168950040000 +system.cpu.numCycles 337900081 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 157988548 +system.cpu.committedOps 278192465 +system.cpu.num_int_alu_accesses 278169482 +system.cpu.num_fp_alu_accesses 40 +system.cpu.num_func_calls 8475189 +system.cpu.num_conditional_control_insts 18628007 +system.cpu.num_int_insts 278169482 +system.cpu.num_fp_insts 40 +system.cpu.num_int_register_reads 635379407 +system.cpu.num_int_register_writes 217447860 +system.cpu.num_fp_register_reads 40 +system.cpu.num_fp_register_writes 26 +system.cpu.num_cc_register_reads 104140596 +system.cpu.num_cc_register_writes 61764861 +system.cpu.num_mem_refs 122219137 +system.cpu.num_load_insts 90779385 +system.cpu.num_store_insts 31439752 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 337900081 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 29309705 +system.cpu.op_class::No_OpClass 16695 0.01% 0.01% +system.cpu.op_class::IntAlu 155945354 56.06% 56.06% +system.cpu.op_class::IntMult 10938 0.00% 56.07% +system.cpu.op_class::IntDiv 329 0.00% 56.07% +system.cpu.op_class::FloatAdd 12 0.00% 56.07% +system.cpu.op_class::FloatCmp 0 0.00% 56.07% +system.cpu.op_class::FloatCvt 0 0.00% 56.07% +system.cpu.op_class::FloatMult 0 0.00% 56.07% +system.cpu.op_class::FloatMultAcc 0 0.00% 56.07% +system.cpu.op_class::FloatDiv 0 0.00% 56.07% +system.cpu.op_class::FloatMisc 0 0.00% 56.07% +system.cpu.op_class::FloatSqrt 0 0.00% 56.07% +system.cpu.op_class::SimdAdd 0 0.00% 56.07% +system.cpu.op_class::SimdAddAcc 0 0.00% 56.07% +system.cpu.op_class::SimdAlu 0 0.00% 56.07% +system.cpu.op_class::SimdCmp 0 0.00% 56.07% +system.cpu.op_class::SimdCvt 0 0.00% 56.07% +system.cpu.op_class::SimdMisc 0 0.00% 56.07% +system.cpu.op_class::SimdMult 0 0.00% 56.07% +system.cpu.op_class::SimdMultAcc 0 0.00% 56.07% +system.cpu.op_class::SimdShift 0 0.00% 56.07% +system.cpu.op_class::SimdShiftAcc 0 0.00% 56.07% +system.cpu.op_class::SimdSqrt 0 0.00% 56.07% +system.cpu.op_class::SimdFloatAdd 0 0.00% 56.07% +system.cpu.op_class::SimdFloatAlu 0 0.00% 56.07% +system.cpu.op_class::SimdFloatCmp 0 0.00% 56.07% +system.cpu.op_class::SimdFloatCvt 0 0.00% 56.07% +system.cpu.op_class::SimdFloatDiv 0 0.00% 56.07% +system.cpu.op_class::SimdFloatMisc 0 0.00% 56.07% +system.cpu.op_class::SimdFloatMult 0 0.00% 56.07% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.07% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.07% +system.cpu.op_class::MemRead 90779371 32.63% 88.70% +system.cpu.op_class::MemWrite 31439738 11.30% 100.00% +system.cpu.op_class::FloatMemRead 14 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 14 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 278192465 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 168950040000 +system.membus.trans_dist::ReadReq 308475611 +system.membus.trans_dist::ReadResp 308475611 +system.membus.trans_dist::WriteReq 31439752 +system.membus.trans_dist::WriteResp 31439752 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 435392328 +system.membus.pkt_count_system.cpu.icache_port::total 435392328 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 244438398 +system.membus.pkt_count_system.cpu.dcache_port::total 244438398 +system.membus.pkt_count::total 679830726 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1741569312 +system.membus.pkt_size_system.cpu.icache_port::total 1741569312 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 960419130 +system.membus.pkt_size_system.cpu.dcache_port::total 960419130 +system.membus.pkt_size::total 2701988442 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 339915363 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 339915363 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 339915363 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index 8d377039e..7ee3ff550 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sp gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 29 2017 20:18:54 -gem5 started Mar 29 2017 20:19:04 -gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 121347 +gem5 compiled Mar 29 2017 21:12:17 +gem5 started Mar 29 2017 21:12:27 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 42630 command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second @@ -81,4 +81,4 @@ Iteration 9 completed [Iteration 10, Thread 1] Critical section done, previously next=2, now next=1 Iteration 10 completed PASSED :-) -Exiting @ tick 126524000 because target called exit() +Exiting @ tick 126524000 because exiting with last active thread context diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index c550cf53f..a10174db1 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000127 sim_ticks 126524000 final_tick 126524000 sim_freq 1000000000000 -host_inst_rate 214440 -host_op_rate 214440 -host_tick_rate 23217304 +host_inst_rate 211101 +host_op_rate 211100 +host_tick_rate 22855727 host_mem_usage 280860 -host_seconds 5.45 +host_seconds 5.54 sim_insts 1168600 sim_ops 1168600 system.voltage_domain.voltage 1 @@ -316,7 +316,7 @@ system.cpu0.fetch.Insts 585438 system.cpu0.fetch.Branches 99156 system.cpu0.fetch.predictedBranches 90042 system.cpu0.fetch.Cycles 194902 -system.cpu0.fetch.SquashCycles 3487 +system.cpu0.fetch.SquashCycles 3486 system.cpu0.fetch.MiscStallCycles 9 system.cpu0.fetch.PendingTrapStallCycles 2371 system.cpu0.fetch.IcacheWaitRetryStallCycles 8 @@ -373,7 +373,7 @@ system.cpu0.iq.iqInstsAdded 468496 system.cpu0.iq.iqNonSpecInstsAdded 1145 system.cpu0.iq.iqInstsIssued 464441 system.cpu0.iq.iqSquashedInstsIssued 106 -system.cpu0.iq.iqSquashedInstsExamined 16686 +system.cpu0.iq.iqSquashedInstsExamined 16685 system.cpu0.iq.iqSquashedOperandsExamined 13469 system.cpu0.iq.iqSquashedNonSpecRemoved 586 system.cpu0.iq.issued_per_cycle::samples 222303 @@ -474,7 +474,7 @@ system.cpu0.iq.rate 1.835380 system.cpu0.iq.fu_busy_cnt 333 system.cpu0.iq.fu_busy_rate 0.000717 system.cpu0.iq.int_inst_queue_reads 1151624 -system.cpu0.iq.int_inst_queue_writes 486379 +system.cpu0.iq.int_inst_queue_writes 486378 system.cpu0.iq.int_inst_queue_wakeup_accesses 461879 system.cpu0.iq.fp_inst_queue_reads 0 system.cpu0.iq.fp_inst_queue_writes 0 @@ -592,7 +592,7 @@ system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% system.cpu0.commit.op_class_0::total 540180 system.cpu0.commit.bw_lim_events 456 system.cpu0.rob.rob_reads 774865 -system.cpu0.rob.rob_writes 1118644 +system.cpu0.rob.rob_writes 1118643 system.cpu0.timesIdled 329 system.cpu0.idleCycles 30746 system.cpu0.committedInsts 452871 @@ -1142,7 +1142,7 @@ system.cpu1.cpi 0.859746 system.cpu1.cpi_total 0.859746 system.cpu1.ipc 1.163134 system.cpu1.ipc_total 1.163134 -system.cpu1.int_regfile_reads 419202 +system.cpu1.int_regfile_reads 419203 system.cpu1.int_regfile_writes 195886 system.cpu1.fp_regfile_writes 64 system.cpu1.misc_regfile_reads 120419 @@ -1682,7 +1682,7 @@ system.cpu2.cpi 0.897099 system.cpu2.cpi_total 0.897099 system.cpu2.ipc 1.114704 system.cpu2.ipc_total 1.114704 -system.cpu2.int_regfile_reads 403345 +system.cpu2.int_regfile_reads 403346 system.cpu2.int_regfile_writes 188790 system.cpu2.fp_regfile_writes 64 system.cpu2.misc_regfile_reads 114754 @@ -2218,7 +2218,7 @@ system.cpu3.cpi 0.704137 system.cpu3.cpi_total 0.704137 system.cpu3.ipc 1.420178 system.cpu3.ipc_total 1.420178 -system.cpu3.int_regfile_reads 509137 +system.cpu3.int_regfile_reads 509138 system.cpu3.int_regfile_writes 236602 system.cpu3.fp_regfile_writes 64 system.cpu3.misc_regfile_reads 150205 diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini index d84a9f055..9aefbd6d1 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini @@ -88,6 +88,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu0.tracer width=1 @@ -98,14 +99,14 @@ icache_port=system.cpu0.icache.cpu_side [system.cpu0.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -119,6 +120,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu0.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -131,15 +133,16 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu0.dtb] type=SparcTLB @@ -149,14 +152,14 @@ size=64 [system.cpu0.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -170,6 +173,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu0.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -182,15 +186,16 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu0.interrupts] type=SparcInterrupts @@ -210,7 +215,7 @@ type=ExeTracer eventq_index=0 [system.cpu0.workload] -type=LiveProcess +type=Process cmd=test_atomic 4 cwd= drivers= @@ -219,14 +224,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/m5threads/bin/sparc/linux/test_atomic +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -267,6 +273,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu1.tracer width=1 @@ -277,14 +284,14 @@ icache_port=system.cpu1.icache.cpu_side [system.cpu1.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -298,6 +305,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu1.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -310,15 +318,16 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu1.dtb] type=SparcTLB @@ -328,14 +337,14 @@ size=64 [system.cpu1.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -349,6 +358,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu1.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -361,15 +371,16 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu1.interrupts] type=SparcInterrupts @@ -423,6 +434,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu2.tracer width=1 @@ -433,14 +445,14 @@ icache_port=system.cpu2.icache.cpu_side [system.cpu2.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -454,6 +466,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu2.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -466,15 +479,16 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu2.dtb] type=SparcTLB @@ -484,14 +498,14 @@ size=64 [system.cpu2.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -505,6 +519,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu2.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -517,15 +532,16 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu2.interrupts] type=SparcInterrupts @@ -579,6 +595,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu3.tracer width=1 @@ -589,14 +606,14 @@ icache_port=system.cpu3.icache.cpu_side [system.cpu3.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -610,6 +627,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu3.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -622,15 +640,16 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu3.dtb] type=SparcTLB @@ -640,14 +659,14 @@ size=64 [system.cpu3.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -661,6 +680,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu3.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -673,15 +693,16 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu3.interrupts] type=SparcInterrupts @@ -719,14 +740,14 @@ transition_latency=100000000 [system.l2c] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -740,6 +761,7 @@ response_latency=20 sequential_access=false size=4194304 system=system +tag_latency=20 tags=system.l2c.tags tgts_per_mshr=12 write_buffers=8 @@ -752,15 +774,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=4194304 +tag_latency=20 [system.membus] type=CoherentXBar @@ -799,6 +822,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -806,7 +830,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.toL2Bus] diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr index a5c275fc8..32afe7799 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr @@ -3,4 +3,5 @@ warn: ClockedObject: More than one power state change request encountered within warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... warn: ClockedObject: Already in the requested power state, request ignored diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout index f5b06fc1f..527306347 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sp gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:30:06 -gem5 started Jul 21 2016 14:30:37 -gem5 executing on e108600-lin, pid 38680 -command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp +gem5 compiled Mar 29 2017 17:08:10 +gem5 started Mar 29 2017 17:08:19 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 126091 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Init done [Iteration 1, Thread 1] Got lock [Iteration 1, Thread 1] Critical section done, previously next=0, now next=1 @@ -82,4 +81,4 @@ Iteration 9 completed [Iteration 10, Thread 2] Critical section done, previously next=1, now next=2 Iteration 10 completed PASSED :-) -Exiting @ tick 87707000 because target called exit() +Exiting @ tick 87707000 because exiting with last active thread context diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index e242611fb..e21097758 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -1,1031 +1,1031 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000088 # Number of seconds simulated -sim_ticks 87707000 # Number of ticks simulated -final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1154171 # Simulator instruction rate (inst/s) -host_op_rate 1154139 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 149440007 # Simulator tick rate (ticks/s) -host_mem_usage 264052 # Number of bytes of host memory used -host_seconds 0.59 # Real time elapsed on the host -sim_insts 677333 # Number of instructions simulated -sim_ops 677333 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::total 35776 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 18048 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 22272 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 282 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 62 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::total 559 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 205776050 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 120400880 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 45241543 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 14594046 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 2189107 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 9486130 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 729702 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 9486130 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 407903588 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 205776050 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 45241543 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 2189107 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 729702 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 253936402 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 205776050 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 120400880 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 45241543 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 14594046 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 2189107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 9486130 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 729702 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 9486130 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 407903588 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.workload.numSyscalls 89 # Number of system calls -system.cpu0.pwrStateResidencyTicks::ON 87707000 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 175415 # number of cpu cycles simulated -system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 175326 # Number of instructions committed -system.cpu0.committedOps 175326 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 120376 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 390 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 28824 # number of instructions that are conditional controls -system.cpu0.num_int_insts 120376 # number of integer instructions -system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 349286 # number of times the integer registers were read -system.cpu0.num_int_register_writes 121983 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 82397 # number of memory refs -system.cpu0.num_load_insts 54591 # Number of load instructions -system.cpu0.num_store_insts 27806 # Number of store instructions -system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu0.num_busy_cycles 175414.998000 # Number of busy cycles -system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu0.Branches 29689 # Number of branches fetched -system.cpu0.op_class::No_OpClass 26416 15.06% 15.06% # Class of executed instruction -system.cpu0.op_class::IntAlu 66491 37.91% 52.97% # Class of executed instruction -system.cpu0.op_class::IntMult 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::FloatMultAcc 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::FloatMisc 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::MemRead 54675 31.17% 84.15% # Class of executed instruction -system.cpu0.op_class::MemWrite 27806 15.85% 100.00% # Class of executed instruction -system.cpu0.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 175388 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 150.745705 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 81882 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 490.311377 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 150.745705 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.294425 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.294425 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 329804 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 329804 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 54430 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 54430 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 27578 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits::cpu0.data 15 # number of SwapReq hits -system.cpu0.dcache.SwapReq_hits::total 15 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 82008 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 82008 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 82008 # number of overall hits -system.cpu0.dcache.overall_hits::total 82008 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 151 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 151 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 177 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 177 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses::cpu0.data 27 # number of SwapReq misses -system.cpu0.dcache.SwapReq_misses::total 27 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 328 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 328 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 328 # number of overall misses -system.cpu0.dcache.overall_misses::total 328 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 54581 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 54581 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 27755 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 27755 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 82336 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 82336 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 82336 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 82336 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002767 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.002767 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006377 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.006377 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.642857 # miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_miss_rate::total 0.642857 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.003984 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.003984 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.003984 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.003984 # miss rate for overall accesses -system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks -system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 215 # number of replacements -system.cpu0.icache.tags.tagsinuse 222.772732 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 374.563169 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 222.772732 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 199 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 175855 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 175855 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 174921 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 174921 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 174921 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 174921 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 174921 # number of overall hits -system.cpu0.icache.overall_hits::total 174921 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses -system.cpu0.icache.overall_misses::total 467 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 175388 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 175388 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 175388 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 175388 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 175388 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 175388 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002663 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.002663 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002663 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.002663 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002663 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.002663 # miss rate for overall accesses -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 215 # number of writebacks -system.cpu0.icache.writebacks::total 215 # number of writebacks -system.cpu1.pwrStateResidencyTicks::ON 87707000 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 173297 # number of cpu cycles simulated -system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 167400 # Number of instructions committed -system.cpu1.committedOps 167400 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 107326 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 633 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 34043 # number of instructions that are conditional controls -system.cpu1.num_int_insts 107326 # number of integer instructions -system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 254436 # number of times the integer registers were read -system.cpu1.num_int_register_writes 94218 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 49494 # number of memory refs -system.cpu1.num_load_insts 39345 # Number of load instructions -system.cpu1.num_store_insts 10149 # Number of store instructions -system.cpu1.num_idle_cycles 7872.827276 # Number of idle cycles -system.cpu1.num_busy_cycles 165424.172724 # Number of busy cycles -system.cpu1.not_idle_fraction 0.954570 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.045430 # Percentage of idle cycles -system.cpu1.Branches 35694 # Number of branches fetched -system.cpu1.op_class::No_OpClass 26475 15.81% 15.81% # Class of executed instruction -system.cpu1.op_class::IntAlu 71873 42.93% 58.74% # Class of executed instruction -system.cpu1.op_class::IntMult 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::FloatMultAcc 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::FloatMisc 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::MemRead 58935 35.20% 93.94% # Class of executed instruction -system.cpu1.op_class::MemWrite 10149 6.06% 100.00% # Class of executed instruction -system.cpu1.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 167432 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 30.295170 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 21529 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 828.038462 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 30.295170 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.059170 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.059170 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 198211 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 198211 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 39152 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 39152 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 9968 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 9968 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 49120 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 49120 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 49120 # number of overall hits -system.cpu1.dcache.overall_hits::total 49120 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 185 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 185 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 102 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 102 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 61 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 61 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 287 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 287 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 287 # number of overall misses -system.cpu1.dcache.overall_misses::total 287 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 39337 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 39337 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 10070 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 10070 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 77 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 77 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 49407 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 49407 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 49407 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 49407 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004703 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.004703 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.010129 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.010129 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.792208 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.792208 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005809 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.005809 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005809 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.005809 # miss rate for overall accesses -system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 278 # number of replacements -system.cpu1.icache.tags.tagsinuse 76.752158 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 167074 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 466.687151 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.752158 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149907 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.149907 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 167790 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 167790 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 167074 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 167074 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 167074 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 167074 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 167074 # number of overall hits -system.cpu1.icache.overall_hits::total 167074 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 358 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 358 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 358 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 358 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 358 # number of overall misses -system.cpu1.icache.overall_misses::total 358 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 167432 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 167432 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 167432 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 167432 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 167432 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 167432 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002138 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.002138 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.002138 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002138 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.002138 # miss rate for overall accesses -system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 278 # number of writebacks -system.cpu1.icache.writebacks::total 278 # number of writebacks -system.cpu2.pwrStateResidencyTicks::ON 87707000 # Cumulative time (in ticks) in various power states -system.cpu2.numCycles 173296 # number of cpu cycles simulated -system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 167335 # Number of instructions committed -system.cpu2.committedOps 167335 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 114196 # Number of integer alu accesses -system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu2.num_func_calls 633 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 30577 # number of instructions that are conditional controls -system.cpu2.num_int_insts 114196 # number of integer instructions -system.cpu2.num_fp_insts 0 # number of float instructions -system.cpu2.num_int_register_reads 295784 # number of times the integer registers were read -system.cpu2.num_int_register_writes 111461 # number of times the integer registers were written -system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu2.num_mem_refs 59830 # number of memory refs -system.cpu2.num_load_insts 42793 # Number of load instructions -system.cpu2.num_store_insts 17037 # Number of store instructions -system.cpu2.num_idle_cycles 7936.997017 # Number of idle cycles -system.cpu2.num_busy_cycles 165359.002983 # Number of busy cycles -system.cpu2.not_idle_fraction 0.954200 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0.045800 # Percentage of idle cycles -system.cpu2.Branches 32221 # Number of branches fetched -system.cpu2.op_class::No_OpClass 23013 13.75% 13.75% # Class of executed instruction -system.cpu2.op_class::IntAlu 75303 44.99% 58.74% # Class of executed instruction -system.cpu2.op_class::IntMult 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::IntDiv 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::FloatAdd 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::FloatCmp 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::FloatCvt 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::FloatMult 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::FloatMultAcc 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::FloatDiv 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::FloatMisc 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::FloatSqrt 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdAdd 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdAddAcc 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdAlu 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdCmp 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdCvt 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdMisc 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdMult 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdMultAcc 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdShift 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdShiftAcc 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdSqrt 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdFloatAdd 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdFloatAlu 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdFloatCmp 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdFloatCvt 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdFloatDiv 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdFloatMisc 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdFloatMult 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdFloatSqrt 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::MemRead 52014 31.08% 89.82% # Class of executed instruction -system.cpu2.op_class::MemWrite 17037 10.18% 100.00% # Class of executed instruction -system.cpu2.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::total 167367 # Class of executed instruction -system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 29.575165 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 35457 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1313.222222 # Average number of references to valid blocks. -system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 29.575165 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.057764 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.057764 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_task_id_blocks::1024 27 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.cpu2.dcache.tags.occ_task_id_percent::1024 0.052734 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 239521 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 239521 # Number of data accesses -system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu2.dcache.ReadReq_hits::cpu2.data 42635 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 42635 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 16864 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 16864 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 59499 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 59499 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 59499 # number of overall hits -system.cpu2.dcache.overall_hits::total 59499 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 150 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 150 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 105 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 105 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 54 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 54 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 255 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 255 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 255 # number of overall misses -system.cpu2.dcache.overall_misses::total 255 # number of overall misses -system.cpu2.dcache.ReadReq_accesses::cpu2.data 42785 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 42785 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 16969 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 16969 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 66 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 59754 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 59754 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 59754 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 59754 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003506 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.003506 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006188 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.006188 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.818182 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.818182 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004267 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.004267 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004267 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.004267 # miss rate for overall accesses -system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu2.icache.tags.replacements 278 # number of replacements -system.cpu2.icache.tags.tagsinuse 74.781471 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 167009 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 466.505587 # Average number of references to valid blocks. -system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 74.781471 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.146058 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.146058 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id -system.cpu2.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 167725 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 167725 # Number of data accesses -system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu2.icache.ReadReq_hits::cpu2.inst 167009 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 167009 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 167009 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 167009 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 167009 # number of overall hits -system.cpu2.icache.overall_hits::total 167009 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 358 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 358 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 358 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 358 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 358 # number of overall misses -system.cpu2.icache.overall_misses::total 358 # number of overall misses -system.cpu2.icache.ReadReq_accesses::cpu2.inst 167367 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 167367 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 167367 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 167367 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 167367 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 167367 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002139 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.002139 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002139 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.002139 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002139 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.002139 # miss rate for overall accesses -system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.icache.writebacks::writebacks 278 # number of writebacks -system.cpu2.icache.writebacks::total 278 # number of writebacks -system.cpu3.pwrStateResidencyTicks::ON 87707000 # Cumulative time (in ticks) in various power states -system.cpu3.numCycles 173297 # number of cpu cycles simulated -system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.committedInsts 167272 # Number of instructions committed -system.cpu3.committedOps 167272 # Number of ops (including micro ops) committed -system.cpu3.num_int_alu_accesses 113295 # Number of integer alu accesses -system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu3.num_func_calls 633 # number of times a function call or return occured -system.cpu3.num_conditional_control_insts 30996 # number of instructions that are conditional controls -system.cpu3.num_int_insts 113295 # number of integer instructions -system.cpu3.num_fp_insts 0 # number of float instructions -system.cpu3.num_int_register_reads 290503 # number of times the integer registers were read -system.cpu3.num_int_register_writes 109270 # number of times the integer registers were written -system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu3.num_mem_refs 58510 # number of memory refs -system.cpu3.num_load_insts 42344 # Number of load instructions -system.cpu3.num_store_insts 16166 # Number of store instructions -system.cpu3.num_idle_cycles 7999.282495 # Number of idle cycles -system.cpu3.num_busy_cycles 165297.717505 # Number of busy cycles -system.cpu3.not_idle_fraction 0.953841 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0.046159 # Percentage of idle cycles -system.cpu3.Branches 32639 # Number of branches fetched -system.cpu3.op_class::No_OpClass 23433 14.01% 14.01% # Class of executed instruction -system.cpu3.op_class::IntAlu 74851 44.74% 58.75% # Class of executed instruction -system.cpu3.op_class::IntMult 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::IntDiv 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::FloatAdd 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::FloatCmp 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::FloatCvt 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::FloatMult 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::FloatMultAcc 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::FloatDiv 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::FloatMisc 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::FloatSqrt 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdAdd 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdAddAcc 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdAlu 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdCmp 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdCvt 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdMisc 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdMult 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdMultAcc 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdShift 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdShiftAcc 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdSqrt 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdFloatAdd 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdFloatAlu 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdFloatCmp 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdFloatCvt 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdFloatDiv 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdFloatMisc 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdFloatMult 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdFloatSqrt 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::MemRead 52854 31.59% 90.34% # Class of executed instruction -system.cpu3.op_class::MemWrite 16166 9.66% 100.00% # Class of executed instruction -system.cpu3.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::total 167304 # Class of executed instruction -system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 28.848199 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 33595 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 1292.115385 # Average number of references to valid blocks. -system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 28.848199 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.056344 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.056344 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.cpu3.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 234241 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 234241 # Number of data accesses -system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu3.dcache.ReadReq_hits::cpu3.data 42185 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 42185 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 15991 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 15991 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 58176 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 58176 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 58176 # number of overall hits -system.cpu3.dcache.overall_hits::total 58176 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 151 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 151 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 109 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 109 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 260 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 260 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 260 # number of overall misses -system.cpu3.dcache.overall_misses::total 260 # number of overall misses -system.cpu3.dcache.ReadReq_accesses::cpu3.data 42336 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 42336 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 16100 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 16100 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 64 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 64 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 58436 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 58436 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 58436 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 58436 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003567 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.003567 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.006770 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.006770 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.812500 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.812500 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004449 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.004449 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004449 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.004449 # miss rate for overall accesses -system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu3.icache.tags.replacements 279 # number of replacements -system.cpu3.icache.tags.tagsinuse 72.874953 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 166945 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 359 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 465.027855 # Average number of references to valid blocks. -system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 72.874953 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.142334 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.142334 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id -system.cpu3.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 167663 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 167663 # Number of data accesses -system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.cpu3.icache.ReadReq_hits::cpu3.inst 166945 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 166945 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 166945 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 166945 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 166945 # number of overall hits -system.cpu3.icache.overall_hits::total 166945 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 359 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 359 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 359 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 359 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 359 # number of overall misses -system.cpu3.icache.overall_misses::total 359 # number of overall misses -system.cpu3.icache.ReadReq_accesses::cpu3.inst 167304 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 167304 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 167304 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 167304 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 167304 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 167304 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002146 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.002146 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002146 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.002146 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002146 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.002146 # miss rate for overall accesses -system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.icache.writebacks::writebacks 279 # number of writebacks -system.cpu3.icache.writebacks::total 279 # number of writebacks -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 498.606697 # Cycle average of tags in use -system.l2c.tags.total_refs 1799 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 559 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.218247 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 153.517433 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 59.512205 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 19.205787 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1.942787 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 12.182505 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 0.965459 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 11.854293 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.002342 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000293 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000030 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.000186 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.000181 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.007608 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 559 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 511 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.008530 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 19423 # Number of tag accesses -system.l2c.tags.data_accesses 19423 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 495 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 495 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 30 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 17 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3.data 19 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 82 # number of UpgradeReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 185 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 296 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu2.inst 355 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu3.inst 358 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1194 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 3 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2.data 9 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu3.data 9 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 26 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 355 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::total 1220 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 185 # number of overall hits -system.l2c.overall_hits::cpu0.data 5 # number of overall hits -system.l2c.overall_hits::cpu1.inst 296 # number of overall hits -system.l2c.overall_hits::cpu1.data 3 # number of overall hits -system.l2c.overall_hits::cpu2.inst 355 # number of overall hits -system.l2c.overall_hits::cpu2.data 9 # number of overall hits -system.l2c.overall_hits::cpu3.inst 358 # number of overall hits -system.l2c.overall_hits::cpu3.data 9 # number of overall hits -system.l2c.overall_hits::total 1220 # number of overall hits -system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 282 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 62 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu2.inst 3 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu3.inst 1 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 348 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 66 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 7 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu2.data 1 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu3.data 1 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 75 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 3 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.inst 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::total 559 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 282 # number of overall misses -system.l2c.overall_misses::cpu0.data 165 # number of overall misses -system.l2c.overall_misses::cpu1.inst 62 # number of overall misses -system.l2c.overall_misses::cpu1.data 20 # number of overall misses -system.l2c.overall_misses::cpu2.inst 3 # number of overall misses -system.l2c.overall_misses::cpu2.data 13 # number of overall misses -system.l2c.overall_misses::cpu3.inst 1 # number of overall misses -system.l2c.overall_misses::cpu3.data 13 # number of overall misses -system.l2c.overall_misses::total 559 # number of overall misses -system.l2c.WritebackDirty_accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 1 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 495 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 495 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 82 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 467 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 358 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu2.inst 358 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu3.inst 359 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1542 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 71 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 10 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu2.data 10 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu3.data 10 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 101 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 23 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 22 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.data 22 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1779 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 23 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.008380 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.002786 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.225681 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.742574 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.008380 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.002786 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.008380 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.inst 0.002786 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.membus.snoop_filter.tot_requests 799 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 240 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 423 # Transaction distribution -system.membus.trans_dist::UpgradeReq 193 # Transaction distribution -system.membus.trans_dist::ReadExReq 183 # Transaction distribution -system.membus.trans_dist::ReadExResp 136 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 423 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1358 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1358 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 35776 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 35776 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 799 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 799 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 799 # Request fanout histogram -system.toL2Bus.snoop_filter.tot_requests 3918 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 1142 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1788 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadResp 2179 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1050 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 275 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 275 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 412 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 412 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1542 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 637 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 712 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 696 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 618 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 997 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 624 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6784 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43648 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 40704 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 40704 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 233088 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 0 # Total snoops (count) -system.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 3918 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.279735 # Request fanout histogram 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+system.toL2Bus.snoop_fanout::3 1030 26.29% 100.00% +system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% +system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% +system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% +system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% +system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.toL2Bus.snoop_fanout::min_value 0 +system.toL2Bus.snoop_fanout::max_value 3 +system.toL2Bus.snoop_fanout::total 3918 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini index 524dea641..02e1544f6 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini @@ -85,6 +85,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu0.tracer workload=system.cpu0.workload @@ -94,14 +95,14 @@ icache_port=system.cpu0.icache.cpu_side [system.cpu0.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -115,6 +116,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu0.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -127,15 +129,16 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu0.dtb] type=SparcTLB @@ -145,14 +148,14 @@ size=64 [system.cpu0.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -166,6 +169,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu0.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -178,15 +182,16 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu0.interrupts] type=SparcInterrupts @@ -206,7 +211,7 @@ type=ExeTracer eventq_index=0 [system.cpu0.workload] -type=LiveProcess +type=Process cmd=test_atomic 4 cwd= drivers= @@ -215,14 +220,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/m5threads/bin/sparc/linux/test_atomic +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -260,6 +266,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu1.tracer workload=system.cpu0.workload @@ -269,14 +276,14 @@ icache_port=system.cpu1.icache.cpu_side [system.cpu1.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -290,6 +297,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu1.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -302,15 +310,16 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu1.dtb] type=SparcTLB @@ -320,14 +329,14 @@ size=64 [system.cpu1.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -341,6 +350,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu1.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -353,15 +363,16 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu1.interrupts] type=SparcInterrupts @@ -412,6 +423,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu2.tracer workload=system.cpu0.workload @@ -421,14 +433,14 @@ icache_port=system.cpu2.icache.cpu_side [system.cpu2.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -442,6 +454,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu2.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -454,15 +467,16 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu2.dtb] type=SparcTLB @@ -472,14 +486,14 @@ size=64 [system.cpu2.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -493,6 +507,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu2.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -505,15 +520,16 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu2.interrupts] type=SparcInterrupts @@ -564,6 +580,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu3.tracer workload=system.cpu0.workload @@ -573,14 +590,14 @@ icache_port=system.cpu3.icache.cpu_side [system.cpu3.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -594,6 +611,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu3.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -606,15 +624,16 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu3.dtb] type=SparcTLB @@ -624,14 +643,14 @@ size=64 [system.cpu3.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -645,6 +664,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu3.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -657,15 +677,16 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu3.interrupts] type=SparcInterrupts @@ -703,14 +724,14 @@ transition_latency=100000000 [system.l2c] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -724,6 +745,7 @@ response_latency=20 sequential_access=false size=4194304 system=system +tag_latency=20 tags=system.l2c.tags tgts_per_mshr=12 write_buffers=8 @@ -736,15 +758,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=4194304 +tag_latency=20 [system.membus] type=CoherentXBar @@ -783,6 +806,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -790,7 +814,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.toL2Bus] diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr index a5c275fc8..32afe7799 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr @@ -3,4 +3,5 @@ warn: ClockedObject: More than one power state change request encountered within warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... warn: ClockedObject: Already in the requested power state, request ignored diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout index dc5d474a6..771ec0419 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sp gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:30:06 -gem5 started Jul 21 2016 14:30:36 -gem5 executing on e108600-lin, pid 38675 -command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp +gem5 compiled Mar 29 2017 17:08:10 +gem5 started Mar 29 2017 17:08:19 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 126092 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Init done [Iteration 1, Thread 2] Got lock [Iteration 1, Thread 2] Critical section done, previously next=0, now next=2 @@ -27,59 +26,59 @@ Iteration 1 completed Iteration 2 completed [Iteration 3, Thread 2] Got lock [Iteration 3, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 3, Thread 1] Got lock -[Iteration 3, Thread 1] Critical section done, previously next=2, now next=1 [Iteration 3, Thread 3] Got lock -[Iteration 3, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 3, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 3, Thread 1] Got lock +[Iteration 3, Thread 1] Critical section done, previously next=3, now next=1 Iteration 3 completed -[Iteration 4, Thread 3] Got lock -[Iteration 4, Thread 3] Critical section done, previously next=0, now next=3 -[Iteration 4, Thread 2] Got lock -[Iteration 4, Thread 2] Critical section done, previously next=3, now next=2 [Iteration 4, Thread 1] Got lock -[Iteration 4, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 4, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 4, Thread 2] Got lock +[Iteration 4, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 4, Thread 3] Got lock +[Iteration 4, Thread 3] Critical section done, previously next=2, now next=3 Iteration 4 completed +[Iteration 5, Thread 3] Got lock +[Iteration 5, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 5, Thread 1] Got lock -[Iteration 5, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 5, Thread 1] Critical section done, previously next=3, now next=1 [Iteration 5, Thread 2] Got lock [Iteration 5, Thread 2] Critical section done, previously next=1, now next=2 -[Iteration 5, Thread 3] Got lock -[Iteration 5, Thread 3] Critical section done, previously next=2, now next=3 Iteration 5 completed +[Iteration 6, Thread 2] Got lock +[Iteration 6, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 6, Thread 3] Got lock -[Iteration 6, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 6, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 6, Thread 1] Got lock [Iteration 6, Thread 1] Critical section done, previously next=3, now next=1 -[Iteration 6, Thread 2] Got lock -[Iteration 6, Thread 2] Critical section done, previously next=1, now next=2 Iteration 6 completed -[Iteration 7, Thread 2] Got lock -[Iteration 7, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 7, Thread 1] Got lock -[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 7, Thread 2] Got lock +[Iteration 7, Thread 2] Critical section done, previously next=1, now next=2 [Iteration 7, Thread 3] Got lock -[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 7, Thread 3] Critical section done, previously next=2, now next=3 Iteration 7 completed [Iteration 8, Thread 3] Got lock [Iteration 8, Thread 3] Critical section done, previously next=0, now next=3 -[Iteration 8, Thread 2] Got lock -[Iteration 8, Thread 2] Critical section done, previously next=3, now next=2 [Iteration 8, Thread 1] Got lock -[Iteration 8, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 8, Thread 2] Got lock +[Iteration 8, Thread 2] Critical section done, previously next=1, now next=2 Iteration 8 completed -[Iteration 9, Thread 1] Got lock -[Iteration 9, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 9, Thread 2] Got lock -[Iteration 9, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 9, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 9, Thread 3] Got lock [Iteration 9, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 9, Thread 1] Got lock +[Iteration 9, Thread 1] Critical section done, previously next=3, now next=1 Iteration 9 completed -[Iteration 10, Thread 3] Got lock -[Iteration 10, Thread 3] Critical section done, previously next=0, now next=3 -[Iteration 10, Thread 2] Got lock -[Iteration 10, Thread 2] Critical section done, previously next=3, now next=2 [Iteration 10, Thread 1] Got lock -[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 10, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 10, Thread 2] Got lock +[Iteration 10, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 10, Thread 3] Got lock +[Iteration 10, Thread 3] Critical section done, previously next=2, now next=3 Iteration 10 completed PASSED :-) -Exiting @ tick 264174500 because target called exit() +Exiting @ tick 263409500 because exiting with last active thread context diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index bdf146296..e816fec12 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,1659 +1,1659 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000263 # Number of seconds simulated -sim_ticks 263409500 # Number of ticks simulated -final_tick 263409500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 870162 # Simulator instruction rate (inst/s) -host_op_rate 870149 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 345251596 # Simulator tick rate (ticks/s) -host_mem_usage 264052 # Number of bytes of host memory used -host_seconds 0.76 # Real time elapsed on the host -sim_insts 663871 # Number of instructions simulated -sim_ops 663871 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 3712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 36608 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 3712 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 58 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 23 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 572 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 69245794 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 40089670 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 2429677 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 3644515 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 14092127 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 5588257 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 242968 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 3644515 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 138977524 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 69245794 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 2429677 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 14092127 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 242968 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 86010565 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 69245794 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 40089670 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 2429677 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3644515 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 14092127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 5588257 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 242968 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 3644515 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 138977524 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.workload.numSyscalls 89 # Number of system calls -system.cpu0.pwrStateResidencyTicks::ON 263409500 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 526819 # number of cpu cycles simulated -system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 158244 # Number of instructions committed -system.cpu0.committedOps 158244 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 108988 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 390 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 25977 # number of instructions that are conditional controls -system.cpu0.num_int_insts 108988 # number of integer instructions -system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 315122 # number of times the integer registers were read -system.cpu0.num_int_register_writes 110594 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 73856 # number of memory refs -system.cpu0.num_load_insts 48897 # Number of load instructions -system.cpu0.num_store_insts 24959 # Number of store instructions -system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu0.num_busy_cycles 526818.998000 # Number of busy cycles -system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu0.Branches 26842 # Number of branches fetched -system.cpu0.op_class::No_OpClass 23569 14.89% 14.89% # Class of executed instruction -system.cpu0.op_class::IntAlu 60797 38.40% 53.29% # Class of executed instruction -system.cpu0.op_class::IntMult 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatMultAcc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatMisc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::MemRead 48981 30.94% 84.23% # Class of executed instruction -system.cpu0.op_class::MemWrite 24959 15.77% 100.00% # Class of executed instruction -system.cpu0.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 158306 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 144.946606 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 73324 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 439.065868 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 144.946606 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.283099 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.283099 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 295657 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 295657 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 48717 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 48717 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 24725 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 24725 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits -system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 73442 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 73442 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 73442 # number of overall hits -system.cpu0.dcache.overall_hits::total 73442 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 170 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 170 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses -system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 353 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 353 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 353 # number of overall misses -system.cpu0.dcache.overall_misses::total 353 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4701000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4701000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6585500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 6585500 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 400000 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 400000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 11286500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 11286500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 11286500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 11286500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 48887 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 48887 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 24908 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 24908 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 73795 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 73795 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 73795 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 73795 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003477 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.003477 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007347 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007347 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004784 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.004784 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004784 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.004784 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27652.941176 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 27652.941176 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35986.338798 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 35986.338798 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 15384.615385 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 15384.615385 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31973.087819 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 31973.087819 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31973.087819 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 31973.087819 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks -system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 170 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 353 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 353 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4531000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4531000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6402500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6402500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 374000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 374000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10933500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10933500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10933500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10933500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003477 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003477 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007347 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007347 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004784 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.004784 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004784 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.004784 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26652.941176 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26652.941176 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 34986.338798 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34986.338798 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 14384.615385 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 14384.615385 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30973.087819 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30973.087819 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30973.087819 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30973.087819 # average overall mshr miss latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 215 # number of replacements -system.cpu0.icache.tags.tagsinuse 211.173601 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 157840 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 337.987152 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 211.173601 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.412448 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.412448 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 158774 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 158774 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 157840 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 157840 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 157840 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 157840 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 157840 # number of overall hits -system.cpu0.icache.overall_hits::total 157840 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses -system.cpu0.icache.overall_misses::total 467 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20426000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 20426000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 20426000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 20426000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 20426000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 20426000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 158307 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 158307 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 158307 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 158307 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 158307 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 158307 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002950 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.002950 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002950 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.002950 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002950 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.002950 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 43738.758030 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 43738.758030 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 43738.758030 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 43738.758030 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 43738.758030 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 43738.758030 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 215 # number of writebacks -system.cpu0.icache.writebacks::total 215 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19959000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 19959000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19959000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 19959000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19959000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 19959000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002950 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.002950 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.002950 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42738.758030 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 42738.758030 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 42738.758030 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 42738.758030 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 42738.758030 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 42738.758030 # average overall mshr miss latency -system.cpu1.pwrStateResidencyTicks::ON 263409500 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 526818 # number of cpu cycles simulated -system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 169340 # Number of instructions committed -system.cpu1.committedOps 169340 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 111465 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 637 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 32946 # number of instructions that are conditional controls -system.cpu1.num_int_insts 111465 # number of integer instructions -system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 276307 # number of times the integer registers were read -system.cpu1.num_int_register_writes 104671 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 54688 # number of memory refs -system.cpu1.num_load_insts 41399 # Number of load instructions -system.cpu1.num_store_insts 13289 # Number of store instructions -system.cpu1.num_idle_cycles 74658.860000 # Number of idle cycles -system.cpu1.num_busy_cycles 452159.140000 # Number of busy cycles -system.cpu1.not_idle_fraction 0.858283 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.141717 # Percentage of idle cycles -system.cpu1.Branches 34599 # Number of branches fetched -system.cpu1.op_class::No_OpClass 25380 14.98% 14.98% # Class of executed instruction -system.cpu1.op_class::IntAlu 74993 44.28% 59.26% # Class of executed instruction -system.cpu1.op_class::IntMult 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::FloatMultAcc 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::FloatMisc 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.26% # Class of executed instruction -system.cpu1.op_class::MemRead 55710 32.89% 92.15% # Class of executed instruction -system.cpu1.op_class::MemWrite 13289 7.85% 100.00% # Class of executed instruction -system.cpu1.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 169372 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 26.434544 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 28854 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 994.965517 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.434544 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.051630 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.051630 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 218970 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 218970 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 41227 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 41227 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 13113 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 13113 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 54340 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 54340 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 54340 # number of overall hits -system.cpu1.dcache.overall_hits::total 54340 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 164 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 164 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 105 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 105 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 269 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 269 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 269 # number of overall misses -system.cpu1.dcache.overall_misses::total 269 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1132500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1132500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1426000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1426000 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 250000 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 250000 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 2558500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 2558500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 2558500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 2558500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 41391 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 41391 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 13218 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 13218 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 69 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 54609 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 54609 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 54609 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 54609 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003962 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.003962 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.007944 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.007944 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.811594 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004926 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.004926 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004926 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.004926 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 6905.487805 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 6905.487805 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 13580.952381 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 13580.952381 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4464.285714 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 4464.285714 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 9511.152416 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 9511.152416 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 9511.152416 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 9511.152416 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 164 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 164 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 269 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 269 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 269 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 269 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 968500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 968500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1321000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1321000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 194000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 194000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2289500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2289500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2289500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2289500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003962 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003962 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.007944 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.007944 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.811594 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.811594 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004926 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.004926 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004926 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.004926 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 5905.487805 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 5905.487805 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12580.952381 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12580.952381 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3464.285714 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3464.285714 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 8511.152416 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 8511.152416 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 8511.152416 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 8511.152416 # average overall mshr miss latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 280 # number of replacements -system.cpu1.icache.tags.tagsinuse 66.813763 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 169007 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 461.767760 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 66.813763 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.130496 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.130496 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 169739 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 169739 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 169007 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 169007 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 169007 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 169007 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 169007 # number of overall hits -system.cpu1.icache.overall_hits::total 169007 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses -system.cpu1.icache.overall_misses::total 366 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5703000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5703000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5703000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5703000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5703000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5703000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 169373 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 169373 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 169373 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 169373 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 169373 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 169373 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002161 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.002161 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002161 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.002161 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002161 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.002161 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15581.967213 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 15581.967213 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15581.967213 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 15581.967213 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15581.967213 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 15581.967213 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 280 # number of writebacks -system.cpu1.icache.writebacks::total 280 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5337000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5337000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5337000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5337000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5337000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5337000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002161 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002161 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002161 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.002161 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002161 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.002161 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14581.967213 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 14581.967213 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14581.967213 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 14581.967213 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14581.967213 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 14581.967213 # average overall mshr miss latency -system.cpu2.pwrStateResidencyTicks::ON 263409500 # Cumulative time (in ticks) in various power states -system.cpu2.numCycles 526819 # number of cpu cycles simulated -system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 165892 # Number of instructions committed -system.cpu2.committedOps 165892 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 110657 # Number of integer alu accesses -system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu2.num_func_calls 637 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 31626 # number of instructions that are conditional controls -system.cpu2.num_int_insts 110657 # number of integer instructions -system.cpu2.num_fp_insts 0 # number of float instructions -system.cpu2.num_int_register_reads 278357 # number of times the integer registers were read -system.cpu2.num_int_register_writes 106099 # number of times the integer registers were written -system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu2.num_mem_refs 55200 # number of memory refs -system.cpu2.num_load_insts 40995 # Number of load instructions -system.cpu2.num_store_insts 14205 # Number of store instructions -system.cpu2.num_idle_cycles 74930.001716 # Number of idle cycles -system.cpu2.num_busy_cycles 451888.998284 # Number of busy cycles -system.cpu2.not_idle_fraction 0.857769 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0.142231 # Percentage of idle cycles -system.cpu2.Branches 33279 # Number of branches fetched -system.cpu2.op_class::No_OpClass 24060 14.50% 14.50% # Class of executed instruction -system.cpu2.op_class::IntAlu 74589 44.95% 59.45% # Class of executed instruction -system.cpu2.op_class::IntMult 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::IntDiv 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::FloatAdd 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::FloatCmp 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::FloatCvt 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::FloatMult 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::FloatMultAcc 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::FloatDiv 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::FloatMisc 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::FloatSqrt 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdAdd 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdAddAcc 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdAlu 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdCmp 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdCvt 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdMisc 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdMult 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdMultAcc 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdShift 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdSqrt 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdFloatMult 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.45% # Class of executed instruction -system.cpu2.op_class::MemRead 53070 31.98% 91.44% # Class of executed instruction -system.cpu2.op_class::MemWrite 14205 8.56% 100.00% # Class of executed instruction -system.cpu2.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::total 165924 # Class of executed instruction -system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 27.420509 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 30687 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1058.172414 # Average number of references to valid blocks. -system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.420509 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.053556 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.053556 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 221019 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 221019 # Number of data accesses -system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu2.dcache.ReadReq_hits::cpu2.data 40826 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 40826 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 14029 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 14029 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 54855 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 54855 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 54855 # number of overall hits -system.cpu2.dcache.overall_hits::total 54855 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 162 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 162 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 105 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 105 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 56 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 56 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 267 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 267 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 267 # number of overall misses -system.cpu2.dcache.overall_misses::total 267 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 1409000 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 1409000 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1485000 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 1485000 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 251000 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 251000 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 2894000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 2894000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 2894000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 2894000 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 40988 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 40988 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 14134 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 14134 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 55122 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 55122 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 55122 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 55122 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003952 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.003952 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.007429 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.007429 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.811594 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004844 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.004844 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004844 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.004844 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 8697.530864 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 8697.530864 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 14142.857143 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 14142.857143 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4482.142857 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 4482.142857 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 10838.951311 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 10838.951311 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 10838.951311 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 10838.951311 # average overall miss latency -system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 162 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 105 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 56 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 267 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 267 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1247000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1247000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1380000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1380000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 195000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 195000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2627000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 2627000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2627000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 2627000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003952 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003952 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.007429 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.007429 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.811594 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.811594 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004844 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.004844 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004844 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.004844 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 7697.530864 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 7697.530864 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13142.857143 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13142.857143 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3482.142857 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3482.142857 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9838.951311 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9838.951311 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9838.951311 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9838.951311 # average overall mshr miss latency -system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu2.icache.tags.replacements 280 # number of replacements -system.cpu2.icache.tags.tagsinuse 69.231273 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 165559 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 452.346995 # Average number of references to valid blocks. -system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 69.231273 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.135217 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.135217 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id -system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 166291 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 166291 # Number of data accesses -system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu2.icache.ReadReq_hits::cpu2.inst 165559 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 165559 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 165559 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 165559 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 165559 # number of overall hits -system.cpu2.icache.overall_hits::total 165559 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses -system.cpu2.icache.overall_misses::total 366 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8164000 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 8164000 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 8164000 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 8164000 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 8164000 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 8164000 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 165925 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 165925 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 165925 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 165925 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 165925 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 165925 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002206 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.002206 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002206 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.002206 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002206 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.002206 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 22306.010929 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 22306.010929 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 22306.010929 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 22306.010929 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 22306.010929 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 22306.010929 # average overall miss latency -system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.icache.writebacks::writebacks 280 # number of writebacks -system.cpu2.icache.writebacks::total 280 # number of writebacks -system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses -system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses -system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7798000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 7798000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7798000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 7798000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7798000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 7798000 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002206 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002206 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002206 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.002206 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002206 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.002206 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21306.010929 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21306.010929 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21306.010929 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 21306.010929 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21306.010929 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 21306.010929 # average overall mshr miss latency -system.cpu3.pwrStateResidencyTicks::ON 263409500 # Cumulative time (in ticks) in various power states -system.cpu3.numCycles 526818 # number of cpu cycles simulated -system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.committedInsts 170395 # Number of instructions committed -system.cpu3.committedOps 170395 # Number of ops (including micro ops) committed -system.cpu3.num_int_alu_accesses 111057 # Number of integer alu accesses -system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu3.num_func_calls 637 # number of times a function call or return occured -system.cpu3.num_conditional_control_insts 33676 # number of instructions that are conditional controls -system.cpu3.num_int_insts 111057 # number of integer instructions -system.cpu3.num_fp_insts 0 # number of float instructions -system.cpu3.num_int_register_reads 271753 # number of times the integer registers were read -system.cpu3.num_int_register_writes 102596 # number of times the integer registers were written -system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu3.num_mem_refs 53550 # number of memory refs -system.cpu3.num_load_insts 41191 # Number of load instructions -system.cpu3.num_store_insts 12359 # Number of store instructions -system.cpu3.num_idle_cycles 75201.858967 # Number of idle cycles -system.cpu3.num_busy_cycles 451616.141033 # Number of busy cycles -system.cpu3.not_idle_fraction 0.857253 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0.142747 # Percentage of idle cycles -system.cpu3.Branches 35332 # Number of branches fetched -system.cpu3.op_class::No_OpClass 26110 15.32% 15.32% # Class of executed instruction -system.cpu3.op_class::IntAlu 74791 43.88% 59.20% # Class of executed instruction -system.cpu3.op_class::IntMult 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::IntDiv 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::FloatAdd 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::FloatCmp 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::FloatCvt 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::FloatMult 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::FloatMultAcc 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::FloatDiv 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::FloatMisc 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::FloatSqrt 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdAdd 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdAddAcc 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdAlu 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdCmp 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdCvt 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdMisc 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdMult 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdMultAcc 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdShift 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdShiftAcc 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdSqrt 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdFloatAdd 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdFloatAlu 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdFloatCmp 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdFloatCvt 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdFloatDiv 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdFloatMisc 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdFloatMult 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::SimdFloatSqrt 0 0.00% 59.20% # Class of executed instruction -system.cpu3.op_class::MemRead 57167 33.54% 92.75% # Class of executed instruction -system.cpu3.op_class::MemWrite 12359 7.25% 100.00% # Class of executed instruction -system.cpu3.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::total 170427 # Class of executed instruction -system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 25.613981 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 27108 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 903.600000 # Average number of references to valid blocks. -system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.613981 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050027 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.050027 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu3.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 214417 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 214417 # Number of data accesses -system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu3.dcache.ReadReq_hits::cpu3.data 41020 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 41020 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 12180 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 12180 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 53200 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 53200 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 53200 # number of overall hits -system.cpu3.dcache.overall_hits::total 53200 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 163 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 163 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 105 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 105 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 58 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 58 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 268 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 268 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 268 # number of overall misses -system.cpu3.dcache.overall_misses::total 268 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 1141000 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 1141000 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1445000 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 1445000 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 263000 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 263000 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 2586000 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 2586000 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 2586000 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 2586000 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 41183 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 41183 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 12285 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 12285 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 72 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 72 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 53468 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 53468 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 53468 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 53468 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003958 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.003958 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.008547 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.008547 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.805556 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.805556 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005012 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.005012 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005012 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.005012 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 7000 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 7000 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 13761.904762 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 13761.904762 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4534.482759 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 4534.482759 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 9649.253731 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 9649.253731 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 9649.253731 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 9649.253731 # average overall miss latency -system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 163 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 58 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 268 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 268 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 978000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 978000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1340000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1340000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 205000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 205000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2318000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 2318000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2318000 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 2318000 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003958 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003958 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.008547 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.008547 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.805556 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.805556 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.005012 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.005012 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.005012 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.005012 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6000 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6000 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12761.904762 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12761.904762 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3534.482759 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3534.482759 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 8649.253731 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 8649.253731 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 8649.253731 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 8649.253731 # average overall mshr miss latency -system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu3.icache.tags.replacements 281 # number of replacements -system.cpu3.icache.tags.tagsinuse 64.803703 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 170061 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 463.381471 # Average number of references to valid blocks. -system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 64.803703 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.126570 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.126570 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id -system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 170795 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 170795 # Number of data accesses -system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.cpu3.icache.ReadReq_hits::cpu3.inst 170061 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 170061 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 170061 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 170061 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 170061 # number of overall hits -system.cpu3.icache.overall_hits::total 170061 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses -system.cpu3.icache.overall_misses::total 367 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5475500 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 5475500 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 5475500 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 5475500 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 5475500 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 5475500 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 170428 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 170428 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 170428 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 170428 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 170428 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 170428 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002153 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.002153 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002153 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.002153 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002153 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.002153 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14919.618529 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 14919.618529 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14919.618529 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 14919.618529 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14919.618529 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 14919.618529 # average overall miss latency -system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.icache.writebacks::writebacks 281 # number of writebacks -system.cpu3.icache.writebacks::total 281 # number of writebacks -system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses -system.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses -system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses -system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5108500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 5108500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5108500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 5108500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5108500 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 5108500 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002153 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002153 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002153 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.002153 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002153 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.002153 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13919.618529 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13919.618529 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13919.618529 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 13919.618529 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13919.618529 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 13919.618529 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 470.663959 # Cycle average of tags in use -system.l2c.tags.total_refs 1794 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 572 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.136364 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::cpu0.inst 230.500098 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 147.566608 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 6.217156 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 10.908895 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 46.660458 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 17.373358 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 0.877256 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 10.560130 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::cpu0.inst 0.003517 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.002252 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000095 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000166 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000712 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.000265 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000013 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.000161 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.007182 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 572 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 511 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.008728 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 19676 # Number of tag accesses -system.l2c.tags.data_accesses 19676 # Number of data accesses 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latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 50512.121212 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 51000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 50800 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 50508.620690 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 50652.173913 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 50500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 51433.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 50566.433566 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 50529.824561 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 50512.121212 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 51000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 50800 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 50508.620690 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 50652.173913 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 50500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 51433.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 50566.433566 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 839 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 261 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 430 # Transaction distribution -system.membus.trans_dist::UpgradeReq 195 # Transaction distribution -system.membus.trans_dist::ReadExReq 208 # Transaction distribution -system.membus.trans_dist::ReadExResp 142 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 430 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1405 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1405 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 261 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 839 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 839 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 839 # Request fanout histogram -system.membus.reqLayer0.occupancy 587124 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 2860000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.1 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 3977 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 1080 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1895 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1056 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 274 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 420 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 420 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1566 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 659 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 581 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1012 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 366 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1012 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1015 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 368 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5868 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43648 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 41344 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 41344 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 41472 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 183616 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1028 # Total snoops (count) -system.toL2Bus.snoopTraffic 53312 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 2919 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.294964 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.172134 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 1002 34.33% 34.33% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 753 25.80% 60.12% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 465 15.93% 76.05% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 699 23.95% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2919 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3053983 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 700500 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 499498 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 550995 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 431976 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 552491 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 427974 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 554986 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 431477 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) +sim_seconds 0.000263 +sim_ticks 263409500 +final_tick 263409500 +sim_freq 1000000000000 +host_inst_rate 743335 +host_op_rate 743323 +host_tick_rate 294930057 +host_mem_usage 276508 +host_seconds 0.89 +sim_insts 663871 +sim_ops 663871 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 263409500 +system.physmem.bytes_read::cpu0.inst 18240 +system.physmem.bytes_read::cpu0.data 10560 +system.physmem.bytes_read::cpu1.inst 640 +system.physmem.bytes_read::cpu1.data 960 +system.physmem.bytes_read::cpu2.inst 3712 +system.physmem.bytes_read::cpu2.data 1472 +system.physmem.bytes_read::cpu3.inst 64 +system.physmem.bytes_read::cpu3.data 960 +system.physmem.bytes_read::total 36608 +system.physmem.bytes_inst_read::cpu0.inst 18240 +system.physmem.bytes_inst_read::cpu1.inst 640 +system.physmem.bytes_inst_read::cpu2.inst 3712 +system.physmem.bytes_inst_read::cpu3.inst 64 +system.physmem.bytes_inst_read::total 22656 +system.physmem.num_reads::cpu0.inst 285 +system.physmem.num_reads::cpu0.data 165 +system.physmem.num_reads::cpu1.inst 10 +system.physmem.num_reads::cpu1.data 15 +system.physmem.num_reads::cpu2.inst 58 +system.physmem.num_reads::cpu2.data 23 +system.physmem.num_reads::cpu3.inst 1 +system.physmem.num_reads::cpu3.data 15 +system.physmem.num_reads::total 572 +system.physmem.bw_read::cpu0.inst 69245794 +system.physmem.bw_read::cpu0.data 40089670 +system.physmem.bw_read::cpu1.inst 2429677 +system.physmem.bw_read::cpu1.data 3644515 +system.physmem.bw_read::cpu2.inst 14092127 +system.physmem.bw_read::cpu2.data 5588257 +system.physmem.bw_read::cpu3.inst 242968 +system.physmem.bw_read::cpu3.data 3644515 +system.physmem.bw_read::total 138977524 +system.physmem.bw_inst_read::cpu0.inst 69245794 +system.physmem.bw_inst_read::cpu1.inst 2429677 +system.physmem.bw_inst_read::cpu2.inst 14092127 +system.physmem.bw_inst_read::cpu3.inst 242968 +system.physmem.bw_inst_read::total 86010565 +system.physmem.bw_total::cpu0.inst 69245794 +system.physmem.bw_total::cpu0.data 40089670 +system.physmem.bw_total::cpu1.inst 2429677 +system.physmem.bw_total::cpu1.data 3644515 +system.physmem.bw_total::cpu2.inst 14092127 +system.physmem.bw_total::cpu2.data 5588257 +system.physmem.bw_total::cpu3.inst 242968 +system.physmem.bw_total::cpu3.data 3644515 +system.physmem.bw_total::total 138977524 +system.pwrStateResidencyTicks::UNDEFINED 263409500 +system.cpu_clk_domain.clock 500 +system.cpu0.workload.numSyscalls 26 +system.cpu0.pwrStateResidencyTicks::ON 263409500 +system.cpu0.numCycles 526819 +system.cpu0.numWorkItemsStarted 0 +system.cpu0.numWorkItemsCompleted 0 +system.cpu0.committedInsts 158244 +system.cpu0.committedOps 158244 +system.cpu0.num_int_alu_accesses 108988 +system.cpu0.num_fp_alu_accesses 0 +system.cpu0.num_func_calls 390 +system.cpu0.num_conditional_control_insts 25977 +system.cpu0.num_int_insts 108988 +system.cpu0.num_fp_insts 0 +system.cpu0.num_int_register_reads 315122 +system.cpu0.num_int_register_writes 110594 +system.cpu0.num_fp_register_reads 0 +system.cpu0.num_fp_register_writes 0 +system.cpu0.num_mem_refs 73856 +system.cpu0.num_load_insts 48897 +system.cpu0.num_store_insts 24959 +system.cpu0.num_idle_cycles 0 +system.cpu0.num_busy_cycles 526819 +system.cpu0.not_idle_fraction 1 +system.cpu0.idle_fraction 0 +system.cpu0.Branches 26842 +system.cpu0.op_class::No_OpClass 23569 14.89% 14.89% +system.cpu0.op_class::IntAlu 60797 38.40% 53.29% +system.cpu0.op_class::IntMult 0 0.00% 53.29% +system.cpu0.op_class::IntDiv 0 0.00% 53.29% +system.cpu0.op_class::FloatAdd 0 0.00% 53.29% +system.cpu0.op_class::FloatCmp 0 0.00% 53.29% +system.cpu0.op_class::FloatCvt 0 0.00% 53.29% +system.cpu0.op_class::FloatMult 0 0.00% 53.29% +system.cpu0.op_class::FloatMultAcc 0 0.00% 53.29% +system.cpu0.op_class::FloatDiv 0 0.00% 53.29% +system.cpu0.op_class::FloatMisc 0 0.00% 53.29% +system.cpu0.op_class::FloatSqrt 0 0.00% 53.29% +system.cpu0.op_class::SimdAdd 0 0.00% 53.29% +system.cpu0.op_class::SimdAddAcc 0 0.00% 53.29% +system.cpu0.op_class::SimdAlu 0 0.00% 53.29% +system.cpu0.op_class::SimdCmp 0 0.00% 53.29% +system.cpu0.op_class::SimdCvt 0 0.00% 53.29% +system.cpu0.op_class::SimdMisc 0 0.00% 53.29% +system.cpu0.op_class::SimdMult 0 0.00% 53.29% +system.cpu0.op_class::SimdMultAcc 0 0.00% 53.29% +system.cpu0.op_class::SimdShift 0 0.00% 53.29% +system.cpu0.op_class::SimdShiftAcc 0 0.00% 53.29% +system.cpu0.op_class::SimdSqrt 0 0.00% 53.29% +system.cpu0.op_class::SimdFloatAdd 0 0.00% 53.29% +system.cpu0.op_class::SimdFloatAlu 0 0.00% 53.29% +system.cpu0.op_class::SimdFloatCmp 0 0.00% 53.29% +system.cpu0.op_class::SimdFloatCvt 0 0.00% 53.29% +system.cpu0.op_class::SimdFloatDiv 0 0.00% 53.29% +system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.29% +system.cpu0.op_class::SimdFloatMult 0 0.00% 53.29% +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.29% +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.29% +system.cpu0.op_class::MemRead 48981 30.94% 84.23% +system.cpu0.op_class::MemWrite 24959 15.77% 100.00% +system.cpu0.op_class::FloatMemRead 0 0.00% 100.00% +system.cpu0.op_class::FloatMemWrite 0 0.00% 100.00% +system.cpu0.op_class::IprAccess 0 0.00% 100.00% +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu0.op_class::total 158306 +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 +system.cpu0.dcache.tags.replacements 2 +system.cpu0.dcache.tags.tagsinuse 144.946606 +system.cpu0.dcache.tags.total_refs 73324 +system.cpu0.dcache.tags.sampled_refs 167 +system.cpu0.dcache.tags.avg_refs 439.065868 +system.cpu0.dcache.tags.warmup_cycle 0 +system.cpu0.dcache.tags.occ_blocks::cpu0.data 144.946606 +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.283099 +system.cpu0.dcache.tags.occ_percent::total 0.283099 +system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 +system.cpu0.dcache.tags.tag_accesses 295657 +system.cpu0.dcache.tags.data_accesses 295657 +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 263409500 +system.cpu0.dcache.ReadReq_hits::cpu0.data 48717 +system.cpu0.dcache.ReadReq_hits::total 48717 +system.cpu0.dcache.WriteReq_hits::cpu0.data 24725 +system.cpu0.dcache.WriteReq_hits::total 24725 +system.cpu0.dcache.SwapReq_hits::cpu0.data 16 +system.cpu0.dcache.SwapReq_hits::total 16 +system.cpu0.dcache.demand_hits::cpu0.data 73442 +system.cpu0.dcache.demand_hits::total 73442 +system.cpu0.dcache.overall_hits::cpu0.data 73442 +system.cpu0.dcache.overall_hits::total 73442 +system.cpu0.dcache.ReadReq_misses::cpu0.data 170 +system.cpu0.dcache.ReadReq_misses::total 170 +system.cpu0.dcache.WriteReq_misses::cpu0.data 183 +system.cpu0.dcache.WriteReq_misses::total 183 +system.cpu0.dcache.SwapReq_misses::cpu0.data 26 +system.cpu0.dcache.SwapReq_misses::total 26 +system.cpu0.dcache.demand_misses::cpu0.data 353 +system.cpu0.dcache.demand_misses::total 353 +system.cpu0.dcache.overall_misses::cpu0.data 353 +system.cpu0.dcache.overall_misses::total 353 +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4701000 +system.cpu0.dcache.ReadReq_miss_latency::total 4701000 +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6585500 +system.cpu0.dcache.WriteReq_miss_latency::total 6585500 +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 400000 +system.cpu0.dcache.SwapReq_miss_latency::total 400000 +system.cpu0.dcache.demand_miss_latency::cpu0.data 11286500 +system.cpu0.dcache.demand_miss_latency::total 11286500 +system.cpu0.dcache.overall_miss_latency::cpu0.data 11286500 +system.cpu0.dcache.overall_miss_latency::total 11286500 +system.cpu0.dcache.ReadReq_accesses::cpu0.data 48887 +system.cpu0.dcache.ReadReq_accesses::total 48887 +system.cpu0.dcache.WriteReq_accesses::cpu0.data 24908 +system.cpu0.dcache.WriteReq_accesses::total 24908 +system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 +system.cpu0.dcache.SwapReq_accesses::total 42 +system.cpu0.dcache.demand_accesses::cpu0.data 73795 +system.cpu0.dcache.demand_accesses::total 73795 +system.cpu0.dcache.overall_accesses::cpu0.data 73795 +system.cpu0.dcache.overall_accesses::total 73795 +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003477 +system.cpu0.dcache.ReadReq_miss_rate::total 0.003477 +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007347 +system.cpu0.dcache.WriteReq_miss_rate::total 0.007347 +system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 +system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004784 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+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 50800 +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 50508.620690 +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 50652.173913 +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 50500 +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 51433.333333 +system.l2c.overall_avg_mshr_miss_latency::total 50566.433566 +system.membus.snoop_filter.tot_requests 839 +system.membus.snoop_filter.hit_single_requests 261 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 263409500 +system.membus.trans_dist::ReadResp 430 +system.membus.trans_dist::UpgradeReq 195 +system.membus.trans_dist::ReadExReq 208 +system.membus.trans_dist::ReadExResp 142 +system.membus.trans_dist::ReadSharedReq 430 +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1405 +system.membus.pkt_count::total 1405 +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 +system.membus.pkt_size::total 36608 +system.membus.snoops 261 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 839 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 839 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 839 +system.membus.reqLayer0.occupancy 587124 +system.membus.reqLayer0.utilization 0.2 +system.membus.respLayer1.occupancy 2860000 +system.membus.respLayer1.utilization 1.1 +system.toL2Bus.snoop_filter.tot_requests 3977 +system.toL2Bus.snoop_filter.hit_single_requests 1080 +system.toL2Bus.snoop_filter.hit_multi_requests 1895 +system.toL2Bus.snoop_filter.tot_snoops 0 +system.toL2Bus.snoop_filter.hit_single_snoops 0 +system.toL2Bus.snoop_filter.hit_multi_snoops 0 +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 263409500 +system.toL2Bus.trans_dist::ReadResp 2225 +system.toL2Bus.trans_dist::WritebackDirty 1 +system.toL2Bus.trans_dist::WritebackClean 1056 +system.toL2Bus.trans_dist::CleanEvict 1 +system.toL2Bus.trans_dist::UpgradeReq 274 +system.toL2Bus.trans_dist::UpgradeResp 274 +system.toL2Bus.trans_dist::ReadExReq 420 +system.toL2Bus.trans_dist::ReadExResp 420 +system.toL2Bus.trans_dist::ReadCleanReq 1566 +system.toL2Bus.trans_dist::ReadSharedReq 659 +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1149 +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 581 +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1012 +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 366 +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1012 +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 365 +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1015 +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 368 +system.toL2Bus.pkt_count::total 5868 +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43648 +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 41344 +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 41344 +system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 +system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 41472 +system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 +system.toL2Bus.pkt_size::total 183616 +system.toL2Bus.snoops 1028 +system.toL2Bus.snoopTraffic 53312 +system.toL2Bus.snoop_fanout::samples 2919 +system.toL2Bus.snoop_fanout::mean 1.294964 +system.toL2Bus.snoop_fanout::stdev 1.172134 +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.toL2Bus.snoop_fanout::0 1002 34.33% 34.33% +system.toL2Bus.snoop_fanout::1 753 25.80% 60.12% +system.toL2Bus.snoop_fanout::2 465 15.93% 76.05% +system.toL2Bus.snoop_fanout::3 699 23.95% 100.00% +system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% +system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% +system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% +system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% +system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.toL2Bus.snoop_fanout::min_value 0 +system.toL2Bus.snoop_fanout::max_value 3 +system.toL2Bus.snoop_fanout::total 2919 +system.toL2Bus.reqLayer0.occupancy 3053983 +system.toL2Bus.reqLayer0.utilization 1.2 +system.toL2Bus.respLayer0.occupancy 700500 +system.toL2Bus.respLayer0.utilization 0.3 +system.toL2Bus.respLayer1.occupancy 499498 +system.toL2Bus.respLayer1.utilization 0.2 +system.toL2Bus.respLayer2.occupancy 550995 +system.toL2Bus.respLayer2.utilization 0.2 +system.toL2Bus.respLayer3.occupancy 431976 +system.toL2Bus.respLayer3.utilization 0.2 +system.toL2Bus.respLayer4.occupancy 552491 +system.toL2Bus.respLayer4.utilization 0.2 +system.toL2Bus.respLayer5.occupancy 427974 +system.toL2Bus.respLayer5.utilization 0.2 +system.toL2Bus.respLayer6.occupancy 554986 +system.toL2Bus.respLayer6.utilization 0.2 +system.toL2Bus.respLayer7.occupancy 431477 +system.toL2Bus.respLayer7.utilization 0.2 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/config.ini index f1a56a700..458ee3b2d 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/config.ini +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/config.ini @@ -90,6 +90,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -165,8 +166,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -177,8 +176,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -239,7 +236,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=vortex lendian.raw cwd=build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic drivers= @@ -248,14 +245,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/vortex +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/vortex gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -279,6 +277,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -290,7 +289,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -298,6 +297,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -306,6 +312,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -313,7 +320,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simerr b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simerr index aadc3d011..04cbe4a7c 100755 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simerr +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simerr @@ -1,2 +1,4 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simout index 99c3eacd0..110c7664f 100755 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simout +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simout @@ -3,12 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-at gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 15:01:37 -gem5 executing on e108600-lin, pid 24147 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/50.vortex/arm/linux/simple-atomic +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 17:56:13 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54215 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/50.vortex/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Exiting @ tick 48960022500 because target called exit() +Exiting @ tick 48960022500 because exiting with last active thread context diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt index 7f158a1e8..6ce3f6504 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -1,262 +1,262 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.048960 # Number of seconds simulated -sim_ticks 48960022500 # Number of ticks simulated -final_tick 48960022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1769120 # Simulator instruction rate (inst/s) -host_op_rate 2262458 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1221438298 # Simulator tick rate (ticks/s) -host_mem_usage 267796 # Number of bytes of host memory used -host_seconds 40.08 # Real time elapsed on the host -sim_insts 70913204 # Number of instructions simulated -sim_ops 90688159 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 48960022500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 312580364 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 106573345 # Number of bytes read from this memory -system.physmem.bytes_read::total 419153709 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 312580364 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 312580364 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 78660211 # Number of bytes written to this memory -system.physmem.bytes_written::total 78660211 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 78145091 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 22919730 # Number of read requests responded to by this memory -system.physmem.num_reads::total 101064821 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 19865820 # Number of write requests responded to by this memory -system.physmem.num_writes::total 19865820 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 6384399925 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2176742157 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8561142083 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6384399925 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6384399925 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1606621218 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1606621218 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6384399925 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3783363376 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10167763301 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 48960022500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 48960022500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 48960022500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 48960022500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 48960022500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 1946 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 48960022500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 97920046 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 70913204 # Number of instructions committed -system.cpu.committedOps 90688159 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 81528528 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses -system.cpu.num_func_calls 3311620 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 9253630 # number of instructions that are conditional controls -system.cpu.num_int_insts 81528528 # number of integer instructions -system.cpu.num_fp_insts 56 # number of float instructions -system.cpu.num_int_register_reads 141479271 # number of times the integer registers were read -system.cpu.num_int_register_writes 53916335 # number of times the integer registers were written -system.cpu.num_fp_register_reads 36 # number of times the floating registers were read -system.cpu.num_fp_register_writes 20 # number of times the floating registers were written -system.cpu.num_cc_register_reads 266608097 # number of times the CC registers were read -system.cpu.num_cc_register_writes 36877111 # number of times the CC registers were written -system.cpu.num_mem_refs 43422001 # number of memory refs -system.cpu.num_load_insts 22866262 # Number of load instructions -system.cpu.num_store_insts 20555739 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 97920045.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 13741468 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 47187979 52.03% 52.03% # Class of executed instruction -system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::MemRead 22866242 25.21% 77.33% # Class of executed instruction -system.cpu.op_class::MemWrite 20555707 22.67% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 20 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 32 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 90690106 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 48960022500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 100925158 # Transaction distribution -system.membus.trans_dist::ReadResp 100941077 # Transaction distribution -system.membus.trans_dist::WriteReq 19849901 # Transaction distribution -system.membus.trans_dist::WriteResp 19849901 # Transaction distribution -system.membus.trans_dist::SoftPFReq 123744 # Transaction distribution -system.membus.trans_dist::SoftPFResp 123744 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 15919 # Transaction distribution -system.membus.trans_dist::StoreCondReq 15919 # Transaction distribution -system.membus.trans_dist::StoreCondResp 15919 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 156290182 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 85571100 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 241861282 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 312580364 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 185233556 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 497813920 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 120930641 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 120930641 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 120930641 # Request fanout histogram +sim_seconds 0.048960 +sim_ticks 48960022500 +final_tick 48960022500 +sim_freq 1000000000000 +host_inst_rate 739512 +host_op_rate 945733 +host_tick_rate 510575162 +host_mem_usage 279300 +host_seconds 95.89 +sim_insts 70913204 +sim_ops 90688159 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 48960022500 +system.physmem.bytes_read::cpu.inst 312580364 +system.physmem.bytes_read::cpu.data 106573345 +system.physmem.bytes_read::total 419153709 +system.physmem.bytes_inst_read::cpu.inst 312580364 +system.physmem.bytes_inst_read::total 312580364 +system.physmem.bytes_written::cpu.data 78660211 +system.physmem.bytes_written::total 78660211 +system.physmem.num_reads::cpu.inst 78145091 +system.physmem.num_reads::cpu.data 22919730 +system.physmem.num_reads::total 101064821 +system.physmem.num_writes::cpu.data 19865820 +system.physmem.num_writes::total 19865820 +system.physmem.bw_read::cpu.inst 6384399925 +system.physmem.bw_read::cpu.data 2176742157 +system.physmem.bw_read::total 8561142083 +system.physmem.bw_inst_read::cpu.inst 6384399925 +system.physmem.bw_inst_read::total 6384399925 +system.physmem.bw_write::cpu.data 1606621218 +system.physmem.bw_write::total 1606621218 +system.physmem.bw_total::cpu.inst 6384399925 +system.physmem.bw_total::cpu.data 3783363376 +system.physmem.bw_total::total 10167763301 +system.pwrStateResidencyTicks::UNDEFINED 48960022500 +system.cpu_clk_domain.clock 500 +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 48960022500 +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.hits 0 +system.cpu.dstage2_mmu.stage2_tlb.misses 0 +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 48960022500 +system.cpu.dtb.walker.walks 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dtb.walker.walkRequestOrigin::total 0 +system.cpu.dtb.inst_hits 0 +system.cpu.dtb.inst_misses 0 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.flush_tlb 0 +system.cpu.dtb.flush_tlb_mva 0 +system.cpu.dtb.flush_tlb_mva_asid 0 +system.cpu.dtb.flush_tlb_asid 0 +system.cpu.dtb.flush_entries 0 +system.cpu.dtb.align_faults 0 +system.cpu.dtb.prefetch_faults 0 +system.cpu.dtb.domain_faults 0 +system.cpu.dtb.perms_faults 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.inst_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 48960022500 +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.hits 0 +system.cpu.istage2_mmu.stage2_tlb.misses 0 +system.cpu.istage2_mmu.stage2_tlb.accesses 0 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 48960022500 +system.cpu.itb.walker.walks 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.itb.walker.walkRequestOrigin::total 0 +system.cpu.itb.inst_hits 0 +system.cpu.itb.inst_misses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.flush_tlb 0 +system.cpu.itb.flush_tlb_mva 0 +system.cpu.itb.flush_tlb_mva_asid 0 +system.cpu.itb.flush_tlb_asid 0 +system.cpu.itb.flush_entries 0 +system.cpu.itb.align_faults 0 +system.cpu.itb.prefetch_faults 0 +system.cpu.itb.domain_faults 0 +system.cpu.itb.perms_faults 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.inst_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 1946 +system.cpu.pwrStateResidencyTicks::ON 48960022500 +system.cpu.numCycles 97920046 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 70913204 +system.cpu.committedOps 90688159 +system.cpu.num_int_alu_accesses 81528528 +system.cpu.num_fp_alu_accesses 56 +system.cpu.num_func_calls 3311620 +system.cpu.num_conditional_control_insts 9253630 +system.cpu.num_int_insts 81528528 +system.cpu.num_fp_insts 56 +system.cpu.num_int_register_reads 141479271 +system.cpu.num_int_register_writes 53916335 +system.cpu.num_fp_register_reads 36 +system.cpu.num_fp_register_writes 20 +system.cpu.num_cc_register_reads 266608097 +system.cpu.num_cc_register_writes 36877111 +system.cpu.num_mem_refs 43422001 +system.cpu.num_load_insts 22866262 +system.cpu.num_store_insts 20555739 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 97920046 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 13741468 +system.cpu.op_class::No_OpClass 0 0.00% 0.00% +system.cpu.op_class::IntAlu 47187979 52.03% 52.03% +system.cpu.op_class::IntMult 80119 0.09% 52.12% +system.cpu.op_class::IntDiv 0 0.00% 52.12% +system.cpu.op_class::FloatAdd 0 0.00% 52.12% +system.cpu.op_class::FloatCmp 0 0.00% 52.12% +system.cpu.op_class::FloatCvt 0 0.00% 52.12% +system.cpu.op_class::FloatMult 0 0.00% 52.12% +system.cpu.op_class::FloatMultAcc 0 0.00% 52.12% +system.cpu.op_class::FloatDiv 0 0.00% 52.12% +system.cpu.op_class::FloatMisc 0 0.00% 52.12% +system.cpu.op_class::FloatSqrt 0 0.00% 52.12% +system.cpu.op_class::SimdAdd 0 0.00% 52.12% +system.cpu.op_class::SimdAddAcc 0 0.00% 52.12% +system.cpu.op_class::SimdAlu 0 0.00% 52.12% +system.cpu.op_class::SimdCmp 0 0.00% 52.12% +system.cpu.op_class::SimdCvt 0 0.00% 52.12% +system.cpu.op_class::SimdMisc 0 0.00% 52.12% +system.cpu.op_class::SimdMult 0 0.00% 52.12% +system.cpu.op_class::SimdMultAcc 0 0.00% 52.12% +system.cpu.op_class::SimdShift 0 0.00% 52.12% +system.cpu.op_class::SimdShiftAcc 0 0.00% 52.12% +system.cpu.op_class::SimdSqrt 0 0.00% 52.12% +system.cpu.op_class::SimdFloatAdd 0 0.00% 52.12% +system.cpu.op_class::SimdFloatAlu 0 0.00% 52.12% +system.cpu.op_class::SimdFloatCmp 0 0.00% 52.12% +system.cpu.op_class::SimdFloatCvt 0 0.00% 52.12% +system.cpu.op_class::SimdFloatDiv 0 0.00% 52.12% +system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12% +system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% +system.cpu.op_class::MemRead 22866242 25.21% 77.33% +system.cpu.op_class::MemWrite 20555707 22.67% 100.00% +system.cpu.op_class::FloatMemRead 20 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 32 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 90690106 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 48960022500 +system.membus.trans_dist::ReadReq 100925158 +system.membus.trans_dist::ReadResp 100941077 +system.membus.trans_dist::WriteReq 19849901 +system.membus.trans_dist::WriteResp 19849901 +system.membus.trans_dist::SoftPFReq 123744 +system.membus.trans_dist::SoftPFResp 123744 +system.membus.trans_dist::LoadLockedReq 15919 +system.membus.trans_dist::StoreCondReq 15919 +system.membus.trans_dist::StoreCondResp 15919 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 156290182 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 85571100 +system.membus.pkt_count::total 241861282 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 312580364 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 185233556 +system.membus.pkt_size::total 497813920 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 120930641 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 120930641 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 120930641 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini index 6aaddcbd1..fac5ea3d0 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini @@ -87,6 +87,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -257,8 +258,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -269,8 +268,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -408,7 +405,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=vortex lendian.raw cwd=build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing drivers= @@ -417,14 +414,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/cpu2000/binaries/arm/linux/vortex +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/vortex gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simerr b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simerr index aadc3d011..04cbe4a7c 100755 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simerr +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simerr @@ -1,2 +1,4 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout index c41441e64..6f4676029 100755 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout @@ -3,12 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-ti gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 29 2016 19:03:48 -gem5 started Nov 29 2016 19:04:15 -gem5 executing on zizzer, pid 5745 -command line: /z/powerjg/gem5-upstream/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/50.vortex/arm/linux/simple-timing +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 17:56:13 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54226 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/50.vortex/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Exiting @ tick 128204299500 because target called exit() +Exiting @ tick 128204299500 because exiting with last active thread context diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index b70e9a80a..00105c43e 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -1,689 +1,689 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.128204 # Number of seconds simulated -sim_ticks 128204299500 # Number of ticks simulated -final_tick 128204299500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 442445 # Simulator instruction rate (inst/s) -host_op_rate 564877 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 806030069 # Simulator tick rate (ticks/s) -host_mem_usage 262052 # Number of bytes of host memory used -host_seconds 159.06 # Real time elapsed on the host -sim_insts 70373651 # Number of instructions simulated -sim_ops 89847385 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 233344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7939200 # Number of bytes read from this memory -system.physmem.bytes_read::total 8172544 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 233344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 233344 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5534528 # Number of bytes written to this memory -system.physmem.bytes_written::total 5534528 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3646 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124050 # Number of read requests responded to by this memory -system.physmem.num_reads::total 127696 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 86477 # Number of write requests responded to by this memory -system.physmem.num_writes::total 86477 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1820095 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 61926160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 63746255 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1820095 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1820095 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 43169597 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 43169597 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 43169597 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1820095 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 61926160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 106915853 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 1946 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 128204299500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 256408599 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 70373651 # Number of instructions committed -system.cpu.committedOps 89847385 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 81528528 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses -system.cpu.num_func_calls 3311620 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 9253630 # number of instructions that are conditional controls -system.cpu.num_int_insts 81528528 # number of integer instructions -system.cpu.num_fp_insts 56 # number of float instructions -system.cpu.num_int_register_reads 141328435 # number of times the integer registers were read -system.cpu.num_int_register_writes 53916335 # number of times the integer registers were written -system.cpu.num_fp_register_reads 36 # number of times the floating registers were read -system.cpu.num_fp_register_writes 20 # number of times the floating registers were written -system.cpu.num_cc_register_reads 334802072 # number of times the CC registers were read -system.cpu.num_cc_register_writes 36877111 # number of times the CC registers were written -system.cpu.num_mem_refs 43422001 # number of memory refs -system.cpu.num_load_insts 22866262 # Number of load instructions -system.cpu.num_store_insts 20555739 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 256408598.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 13741468 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 47187979 52.03% 52.03% # Class of executed instruction -system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::MemRead 22866242 25.21% 77.33% # Class of executed instruction -system.cpu.op_class::MemWrite 20555707 22.67% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 20 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 32 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 90690106 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 155902 # number of replacements -system.cpu.dcache.tags.tagsinuse 4075.864194 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42601590 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 266.263266 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1116590500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4075.864194 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995084 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995084 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 774 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3277 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 22743326 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22743326 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 83557 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 83557 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42486195 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42486195 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42569752 # number of overall hits -system.cpu.dcache.overall_hits::total 42569752 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 36741 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 36741 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 40187 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 40187 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 143773 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 143773 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 183960 # number of overall misses -system.cpu.dcache.overall_misses::total 183960 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 594992500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 594992500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 6509368500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 6509368500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7104361000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7104361000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7104361000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7104361000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22780067 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22780067 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 123744 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 123744 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42629968 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42629968 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42753712 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42753712 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001613 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.001613 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005392 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.324759 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.324759 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.003373 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.003373 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.004303 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.004303 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16194.238045 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16194.238045 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60817.031355 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60817.031355 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 49413.735541 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 49413.735541 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 38619.053055 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38619.053055 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 127926 # number of writebacks -system.cpu.dcache.writebacks::total 127926 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7633 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 7633 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7633 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7633 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7633 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7633 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29108 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 29108 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107032 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23858 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 23858 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 136140 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 136140 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 504199000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 504199000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6402336500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6402336500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1220892000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1220892000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6906535500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6906535500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8127427500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8127427500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001278 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001278 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.192801 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.192801 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003194 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003194 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17321.664147 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17321.664147 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59817.031355 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59817.031355 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 51173.275212 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 51173.275212 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50731.126047 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 50731.126047 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50797.056838 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 50797.056838 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 16890 # number of replacements -system.cpu.icache.tags.tagsinuse 1732.169683 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 78126184 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4131.911572 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1732.169683 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.845786 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.845786 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 294 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1645 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.985352 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 156309092 # Number of tag accesses -system.cpu.icache.tags.data_accesses 156309092 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 78126184 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 78126184 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 78126184 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 78126184 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 78126184 # number of overall hits -system.cpu.icache.overall_hits::total 78126184 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 18908 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 18908 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 18908 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses -system.cpu.icache.overall_misses::total 18908 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 429951000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 429951000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 429951000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 429951000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 429951000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 429951000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 78145092 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 78145092 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 78145092 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 78145092 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 78145092 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 78145092 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000242 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000242 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22739.105141 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22739.105141 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22739.105141 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22739.105141 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22739.105141 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22739.105141 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of 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-system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 411043000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 411043000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 411043000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 411043000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 411043000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 411043000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21739.105141 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21739.105141 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21739.105141 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21739.105141 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21739.105141 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21739.105141 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 96062 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31698.825375 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 219067 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 128830 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.700435 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 20554489000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 380.240484 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1041.373230 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 30277.211662 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.011604 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.031780 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.923987 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.967371 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 798 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 14304 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 16713 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 800 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 2912846 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 2912846 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 127926 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 127926 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 15790 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 15790 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4712 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4712 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 15262 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 15262 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31236 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 31236 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 15262 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 35948 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 51210 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 15262 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 35948 # number of overall hits -system.cpu.l2cache.overall_hits::total 51210 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 102320 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 102320 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3646 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 3646 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21730 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 21730 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3646 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 124050 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 127696 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3646 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 124050 # number of overall misses -system.cpu.l2cache.overall_misses::total 127696 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6192310500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6192310500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 221047500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 221047500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1315278500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 1315278500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 221047500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7507589000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 7728636500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 221047500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7507589000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 7728636500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 127926 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 127926 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 15790 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 15790 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 107032 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 107032 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 18908 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 18908 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 52966 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 52966 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 18908 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 159998 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 178906 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 18908 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 159998 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 178906 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955976 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.955976 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.192828 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.192828 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.410263 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.410263 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192828 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.775322 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.713760 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192828 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.775322 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.713760 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60519.062744 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60519.062744 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60627.399890 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60627.399890 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60528.232858 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60528.232858 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60627.399890 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60520.669085 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60523.716483 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60627.399890 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60520.669085 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60523.716483 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 86477 # number of writebacks -system.cpu.l2cache.writebacks::total 86477 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 105 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 105 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102320 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102320 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3646 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3646 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21730 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21730 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3646 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 124050 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 127696 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3646 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 124050 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 127696 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5169110500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5169110500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 184587500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 184587500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1097978500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1097978500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 184587500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6267089000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6451676500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 184587500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6267089000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6451676500 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955976 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955976 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.192828 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.192828 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.410263 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.410263 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.192828 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775322 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.713760 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.192828 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775322 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.713760 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50519.062744 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50519.062744 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50627.399890 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50627.399890 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50528.232858 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50528.232858 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50627.399890 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50520.669085 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50523.716483 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50627.399890 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50520.669085 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50523.716483 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 351698 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 172817 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3696 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 3224 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3194 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 214403 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 16890 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 37561 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107032 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 18908 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 52966 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54706 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 475898 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 530604 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2291072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18427136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 20718208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 96062 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 5534528 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 274968 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.025367 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.157929 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 268023 97.47% 97.47% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 6915 2.51% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 30 0.01% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 274968 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 320665000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 28362000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 239997000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 220672 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 93041 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 25376 # Transaction distribution -system.membus.trans_dist::WritebackDirty 86477 # Transaction distribution -system.membus.trans_dist::CleanEvict 6466 # Transaction distribution -system.membus.trans_dist::ReadExReq 102320 # Transaction distribution -system.membus.trans_dist::ReadExResp 102320 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 25376 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 348335 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 348335 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13707072 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13707072 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 127704 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 127704 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 127704 # Request fanout histogram -system.membus.reqLayer0.occupancy 569386372 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 638480000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.5 # Layer utilization (%) +sim_seconds 0.128204 +sim_ticks 128204299500 +final_tick 128204299500 +sim_freq 1000000000000 +host_inst_rate 533817 +host_op_rate 681535 +host_tick_rate 972489774 +host_mem_usage 290320 +host_seconds 131.83 +sim_insts 70373651 +sim_ops 89847385 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 128204299500 +system.physmem.bytes_read::cpu.inst 233344 +system.physmem.bytes_read::cpu.data 7939200 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4075.864194 +system.cpu.dcache.tags.total_refs 42601590 +system.cpu.dcache.tags.sampled_refs 159998 +system.cpu.dcache.tags.avg_refs 266.263266 +system.cpu.dcache.tags.warmup_cycle 1116590500 +system.cpu.dcache.tags.occ_blocks::cpu.data 4075.864194 +system.cpu.dcache.tags.occ_percent::cpu.data 0.995084 +system.cpu.dcache.tags.occ_percent::total 0.995084 +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 +system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 +system.cpu.dcache.tags.age_task_id_blocks_1024::1 774 +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3277 +system.cpu.dcache.tags.occ_task_id_percent::1024 1 +system.cpu.dcache.tags.tag_accesses 85731098 +system.cpu.dcache.tags.data_accesses 85731098 +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 128204299500 +system.cpu.dcache.ReadReq_hits::cpu.data 22743326 +system.cpu.dcache.ReadReq_hits::total 22743326 +system.cpu.dcache.WriteReq_hits::cpu.data 19742869 +system.cpu.dcache.WriteReq_hits::total 19742869 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+system.membus.trans_dist::ReadExReq 102320 +system.membus.trans_dist::ReadExResp 102320 +system.membus.trans_dist::ReadSharedReq 25376 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 348335 +system.membus.pkt_count::total 348335 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13707072 +system.membus.pkt_size::total 13707072 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 127704 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 127704 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 127704 +system.membus.reqLayer0.occupancy 569386372 +system.membus.reqLayer0.utilization 0.4 +system.membus.respLayer1.occupancy 638480000 +system.membus.respLayer1.utilization 0.5 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini index 3a4f61f9d..325da9e41 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini @@ -88,6 +88,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -118,7 +119,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=vortex bendian.raw cwd=build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic drivers= @@ -127,14 +128,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/sparc/linux/vortex +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/sparc/linux/vortex gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -158,6 +160,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -169,7 +172,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -177,6 +180,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -185,6 +195,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -192,7 +203,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simerr b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simerr index e38712610..d418fa117 100755 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simerr +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simerr @@ -1,563 +1,565 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: ignoring syscall time(4026527848, ...) -warn: ignoring syscall time(4026527400, ...) -warn: ignoring syscall time(4026527312, ...) -warn: ignoring syscall time(4026527048, ...) -warn: ignoring syscall time(4026527048, ...) -warn: ignoring syscall time(4026527288, ...) -warn: ignoring syscall time(4026526840, ...) -warn: ignoring syscall time(4026527048, ...) -warn: ignoring syscall time(4026527048, ...) -warn: ignoring syscall time(4026526960, ...) -warn: ignoring syscall time(4026527040, ...) -warn: ignoring syscall time(4026527000, ...) -warn: ignoring syscall time(4026526984, ...) -warn: ignoring syscall time(4026526984, ...) -warn: ignoring syscall time(4026526872, ...) -warn: ignoring syscall time(4026526312, ...) -warn: ignoring syscall time(4026526832, ...) -warn: ignoring syscall time(4026526872, ...) -warn: ignoring syscall time(4026526872, ...) -warn: ignoring syscall time(4026526848, ...) -warn: ignoring syscall time(4026526840, ...) -warn: ignoring syscall time(4026526872, ...) -warn: ignoring syscall time(4026526856, ...) -warn: ignoring syscall time(4026526848, ...) -warn: ignoring syscall time(4026526936, ...) -warn: ignoring syscall time(4026527008, ...) -warn: ignoring syscall time(4026526560, ...) -warn: ignoring syscall time(4026527184, ...) -warn: ignoring syscall time(4026526632, ...) -warn: ignoring syscall time(4026526736, ...) -warn: ignoring syscall time(4026527320, ...) -warn: ignoring syscall time(4026527744, ...) -warn: ignoring syscall time(4026527048, ...) -warn: ignoring syscall time(4026526856, ...) -warn: ignoring syscall time(4026526872, ...) -warn: ignoring syscall time(4026527096, ...) -warn: ignoring syscall time(4026526648, ...) -warn: ignoring syscall time(4026526824, ...) -warn: ignoring syscall time(4026527320, ...) -warn: ignoring syscall time(4026527184, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026526912, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026526912, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026526912, ...) -warn: ignoring syscall time(4026526912, ...) -warn: ignoring syscall time(4026525968, ...) -warn: ignoring syscall time(4026525968, ...) -warn: ignoring syscall time(4026526056, ...) -warn: ignoring syscall time(4026527512, ...) -warn: ignoring syscall time(4026525760, ...) +info: Entering event queue @ 0. Starting simulation... +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +info: Increasing stack size by one page. +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall 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ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall 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ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simout index 09707d695..92f95a99b 100755 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simout @@ -3,12 +3,10 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simpl gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:30:06 -gem5 started Jul 21 2016 14:30:35 -gem5 executing on e108600-lin, pid 38667 -command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/50.vortex/sparc/linux/simple-atomic +gem5 compiled Apr 3 2017 18:41:19 +gem5 started Apr 3 2017 18:43:58 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 66518 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/50.vortex/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Exiting @ tick 68148677000 because target called exit() +Exiting @ tick 68148677000 because exiting with last active thread context diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt index eb352a8fe..e5f6b910a 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt @@ -1,139 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.068149 # Number of seconds simulated -sim_ticks 68148677000 # Number of ticks simulated -final_tick 68148677000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2768800 # Simulator instruction rate (inst/s) -host_op_rate 2804650 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1403953412 # Simulator tick rate (ticks/s) -host_mem_usage 249976 # Number of bytes of host memory used -host_seconds 48.54 # Real time elapsed on the host -sim_insts 134398959 # Number of instructions simulated -sim_ops 136139187 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 68148677000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 538214320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 147559360 # Number of bytes read from this memory -system.physmem.bytes_read::total 685773680 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 538214320 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 538214320 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 89882950 # Number of bytes written to this memory -system.physmem.bytes_written::total 89882950 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 134553580 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 37231300 # Number of read requests responded to by this memory -system.physmem.num_reads::total 171784880 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 20864304 # Number of write requests responded to by this memory -system.physmem.num_writes::total 20864304 # Number of write requests responded to by this memory -system.physmem.num_other::cpu.data 15916 # Number of other requests responded to by this memory -system.physmem.num_other::total 15916 # Number of other requests responded to by this memory -system.physmem.bw_read::cpu.inst 7897648842 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2165256414 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10062905256 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7897648842 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7897648842 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1318924357 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1318924357 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7897648842 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3484180771 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11381829614 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 68148677000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.numSyscalls 1946 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 68148677000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 136297355 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 134398959 # Number of instructions committed -system.cpu.committedOps 136139187 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 115187757 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 2326976 # Number of float alu accesses -system.cpu.num_func_calls 1709332 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8898968 # number of instructions that are conditional controls -system.cpu.num_int_insts 115187757 # number of integer instructions -system.cpu.num_fp_insts 2326976 # number of float instructions -system.cpu.num_int_register_reads 263032419 # number of times the integer registers were read -system.cpu.num_int_register_writes 113147731 # number of times the integer registers were written -system.cpu.num_fp_register_reads 4725606 # number of times the floating registers were read -system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written -system.cpu.num_mem_refs 58160261 # number of memory refs -system.cpu.num_load_insts 37275864 # Number of load instructions -system.cpu.num_store_insts 20884397 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 136297354.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 12719094 # Number of branches fetched -system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% # Class of executed instruction -system.cpu.op_class::IntAlu 66342067 48.68% 57.07% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 57.07% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 57.07% # Class of executed instruction -system.cpu.op_class::FloatAdd 325584 0.24% 57.31% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::MemRead 37046611 27.18% 84.49% # Class of executed instruction -system.cpu.op_class::MemWrite 19133112 14.04% 98.53% # Class of executed instruction -system.cpu.op_class::FloatMemRead 250107 0.18% 98.72% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 1751285 1.28% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 136293808 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 68148677000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 171784880 # Transaction distribution -system.membus.trans_dist::ReadResp 171784880 # Transaction distribution -system.membus.trans_dist::WriteReq 20864304 # Transaction distribution -system.membus.trans_dist::WriteResp 20864304 # Transaction distribution -system.membus.trans_dist::SwapReq 15916 # Transaction distribution -system.membus.trans_dist::SwapResp 15916 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 269107160 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 116223040 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 385330200 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 538214320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 237569638 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 775783958 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 192665100 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 192665100 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 192665100 # Request fanout histogram +sim_seconds 0.068149 +sim_ticks 68148677000 +final_tick 68148677000 +sim_freq 1000000000000 +host_inst_rate 1228497 +host_op_rate 1244404 +host_tick_rate 622924579 +host_mem_usage 262248 +host_seconds 109.40 +sim_insts 134398959 +sim_ops 136139187 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 68148677000 +system.physmem.bytes_read::cpu.inst 538214320 +system.physmem.bytes_read::cpu.data 147559360 +system.physmem.bytes_read::total 685773680 +system.physmem.bytes_inst_read::cpu.inst 538214320 +system.physmem.bytes_inst_read::total 538214320 +system.physmem.bytes_written::cpu.data 89882950 +system.physmem.bytes_written::total 89882950 +system.physmem.num_reads::cpu.inst 134553580 +system.physmem.num_reads::cpu.data 37231300 +system.physmem.num_reads::total 171784880 +system.physmem.num_writes::cpu.data 20864304 +system.physmem.num_writes::total 20864304 +system.physmem.num_other::cpu.data 15916 +system.physmem.num_other::total 15916 +system.physmem.bw_read::cpu.inst 7897648842 +system.physmem.bw_read::cpu.data 2165256414 +system.physmem.bw_read::total 10062905256 +system.physmem.bw_inst_read::cpu.inst 7897648842 +system.physmem.bw_inst_read::total 7897648842 +system.physmem.bw_write::cpu.data 1318924357 +system.physmem.bw_write::total 1318924357 +system.physmem.bw_total::cpu.inst 7897648842 +system.physmem.bw_total::cpu.data 3484180771 +system.physmem.bw_total::total 11381829614 +system.pwrStateResidencyTicks::UNDEFINED 68148677000 +system.cpu_clk_domain.clock 500 +system.cpu.workload.numSyscalls 1946 +system.cpu.pwrStateResidencyTicks::ON 68148677000 +system.cpu.numCycles 136297355 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 134398959 +system.cpu.committedOps 136139187 +system.cpu.num_int_alu_accesses 115187757 +system.cpu.num_fp_alu_accesses 2326976 +system.cpu.num_func_calls 1709332 +system.cpu.num_conditional_control_insts 8898968 +system.cpu.num_int_insts 115187757 +system.cpu.num_fp_insts 2326976 +system.cpu.num_int_register_reads 263032419 +system.cpu.num_int_register_writes 113147731 +system.cpu.num_fp_register_reads 4725606 +system.cpu.num_fp_register_writes 1150968 +system.cpu.num_mem_refs 58160261 +system.cpu.num_load_insts 37275864 +system.cpu.num_store_insts 20884397 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 136297355 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 12719094 +system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% +system.cpu.op_class::IntAlu 66342067 48.68% 57.07% +system.cpu.op_class::IntMult 0 0.00% 57.07% +system.cpu.op_class::IntDiv 0 0.00% 57.07% +system.cpu.op_class::FloatAdd 325584 0.24% 57.31% +system.cpu.op_class::FloatCmp 0 0.00% 57.31% +system.cpu.op_class::FloatCvt 0 0.00% 57.31% +system.cpu.op_class::FloatMult 0 0.00% 57.31% +system.cpu.op_class::FloatMultAcc 0 0.00% 57.31% +system.cpu.op_class::FloatDiv 0 0.00% 57.31% +system.cpu.op_class::FloatMisc 0 0.00% 57.31% +system.cpu.op_class::FloatSqrt 0 0.00% 57.31% +system.cpu.op_class::SimdAdd 0 0.00% 57.31% +system.cpu.op_class::SimdAddAcc 0 0.00% 57.31% +system.cpu.op_class::SimdAlu 0 0.00% 57.31% +system.cpu.op_class::SimdCmp 0 0.00% 57.31% +system.cpu.op_class::SimdCvt 0 0.00% 57.31% +system.cpu.op_class::SimdMisc 0 0.00% 57.31% +system.cpu.op_class::SimdMult 0 0.00% 57.31% +system.cpu.op_class::SimdMultAcc 0 0.00% 57.31% +system.cpu.op_class::SimdShift 0 0.00% 57.31% +system.cpu.op_class::SimdShiftAcc 0 0.00% 57.31% +system.cpu.op_class::SimdSqrt 0 0.00% 57.31% +system.cpu.op_class::SimdFloatAdd 0 0.00% 57.31% +system.cpu.op_class::SimdFloatAlu 0 0.00% 57.31% +system.cpu.op_class::SimdFloatCmp 0 0.00% 57.31% +system.cpu.op_class::SimdFloatCvt 0 0.00% 57.31% +system.cpu.op_class::SimdFloatDiv 0 0.00% 57.31% +system.cpu.op_class::SimdFloatMisc 0 0.00% 57.31% +system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% +system.cpu.op_class::MemRead 37046611 27.18% 84.49% +system.cpu.op_class::MemWrite 19133112 14.04% 98.53% +system.cpu.op_class::FloatMemRead 250107 0.18% 98.72% +system.cpu.op_class::FloatMemWrite 1751285 1.28% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 136293808 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 68148677000 +system.membus.trans_dist::ReadReq 171784880 +system.membus.trans_dist::ReadResp 171784880 +system.membus.trans_dist::WriteReq 20864304 +system.membus.trans_dist::WriteResp 20864304 +system.membus.trans_dist::SwapReq 15916 +system.membus.trans_dist::SwapResp 15916 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 269107160 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 116223040 +system.membus.pkt_count::total 385330200 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 538214320 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 237569638 +system.membus.pkt_size::total 775783958 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 192665100 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 192665100 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 192665100 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini index 14d66f92a..129a63c1e 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini @@ -85,6 +85,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -94,14 +95,14 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -115,6 +116,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -127,15 +129,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dtb] type=SparcTLB @@ -145,14 +148,14 @@ size=64 [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -166,6 +169,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -178,15 +182,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=SparcInterrupts @@ -204,14 +209,14 @@ size=64 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -225,6 +230,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -237,15 +243,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -281,7 +288,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=vortex bendian.raw cwd=build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing drivers= @@ -290,14 +297,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/sparc/linux/vortex +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/sparc/linux/vortex gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -321,6 +329,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -332,7 +341,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -340,6 +349,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -348,6 +364,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -355,7 +372,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simerr b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simerr index e38712610..d418fa117 100755 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simerr +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simerr @@ -1,563 +1,565 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: ignoring syscall time(4026527848, ...) -warn: ignoring syscall time(4026527400, ...) -warn: ignoring syscall time(4026527312, ...) -warn: ignoring syscall time(4026527048, ...) -warn: ignoring syscall time(4026527048, ...) -warn: ignoring syscall time(4026527288, ...) -warn: ignoring syscall time(4026526840, ...) -warn: ignoring syscall time(4026527048, ...) -warn: ignoring syscall time(4026527048, ...) -warn: ignoring syscall time(4026526960, ...) -warn: ignoring syscall time(4026527040, ...) -warn: ignoring syscall time(4026527000, ...) -warn: ignoring syscall time(4026526984, ...) -warn: ignoring syscall time(4026526984, ...) -warn: ignoring syscall time(4026526872, ...) -warn: ignoring syscall time(4026526312, ...) -warn: ignoring syscall time(4026526832, ...) -warn: ignoring syscall time(4026526872, ...) -warn: ignoring syscall time(4026526872, ...) -warn: ignoring syscall time(4026526848, ...) -warn: ignoring syscall time(4026526840, ...) -warn: ignoring syscall time(4026526872, ...) -warn: ignoring syscall time(4026526856, ...) -warn: ignoring syscall time(4026526848, ...) -warn: ignoring syscall time(4026526936, ...) -warn: ignoring syscall time(4026527008, ...) -warn: ignoring syscall time(4026526560, ...) -warn: ignoring syscall time(4026527184, ...) -warn: ignoring syscall time(4026526632, ...) -warn: ignoring syscall time(4026526736, ...) -warn: ignoring syscall time(4026527320, ...) -warn: ignoring syscall time(4026527744, ...) -warn: ignoring syscall time(4026527048, ...) -warn: ignoring syscall time(4026526856, ...) -warn: ignoring syscall time(4026526872, ...) -warn: ignoring syscall time(4026527096, ...) -warn: ignoring syscall time(4026526648, ...) -warn: ignoring syscall time(4026526824, ...) -warn: ignoring syscall time(4026527320, ...) -warn: ignoring syscall time(4026527184, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall times(4026527728, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026526912, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026526912, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026527472, ...) -warn: ignoring syscall time(4026526912, ...) -warn: ignoring syscall time(4026526912, ...) -warn: ignoring syscall time(4026525968, ...) -warn: ignoring syscall time(4026525968, ...) -warn: ignoring syscall time(4026526056, ...) -warn: ignoring syscall time(4026527512, ...) -warn: ignoring syscall time(4026525760, ...) +info: Entering event queue @ 0. Starting simulation... +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +info: Increasing stack size by one page. +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: ignoring syscall times(...) +warn: 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time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) +warn: ignoring syscall time(...) diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simout index 8920b4c6b..da084e8e1 100755 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simout @@ -3,12 +3,10 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simpl gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:30:06 -gem5 started Jul 21 2016 14:30:38 -gem5 executing on e108600-lin, pid 38688 -command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/50.vortex/sparc/linux/simple-timing +gem5 compiled Apr 3 2017 18:41:19 +gem5 started Apr 3 2017 18:41:55 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 65144 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/50.vortex/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Exiting @ tick 203115946500 because target called exit() +Exiting @ tick 203260902500 because exiting with last active thread context diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index 2c0880e3e..aec377294 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -1,558 +1,558 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.203261 # Number of seconds simulated -sim_ticks 203260902500 # Number of ticks simulated -final_tick 203260902500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1825324 # Simulator instruction rate (inst/s) -host_op_rate 1848958 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2760562270 # Simulator tick rate (ticks/s) -host_mem_usage 261500 # Number of bytes of host memory used -host_seconds 73.63 # Real time elapsed on the host -sim_insts 134398959 # Number of instructions simulated -sim_ops 136139187 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 526720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7845184 # Number of bytes read from this memory -system.physmem.bytes_read::total 8371904 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 526720 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 526720 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5476224 # Number of bytes written to this memory -system.physmem.bytes_written::total 5476224 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 8230 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 122581 # Number of read requests responded to by this memory -system.physmem.num_reads::total 130811 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 85566 # Number of write requests responded to by this memory -system.physmem.num_writes::total 85566 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2591349 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 38596621 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 41187970 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2591349 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2591349 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 26941846 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 26941846 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 26941846 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2591349 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 38596621 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 68129817 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.numSyscalls 1946 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 203260902500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 406521805 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 134398959 # Number of instructions committed -system.cpu.committedOps 136139187 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 115187757 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 2326976 # Number of float alu accesses -system.cpu.num_func_calls 1709332 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8898968 # number of instructions that are conditional controls -system.cpu.num_int_insts 115187757 # number of integer instructions -system.cpu.num_fp_insts 2326976 # number of float instructions -system.cpu.num_int_register_reads 263032419 # number of times the integer registers were read -system.cpu.num_int_register_writes 113147730 # number of times the integer registers were written -system.cpu.num_fp_register_reads 4725606 # number of times the floating registers were read -system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written -system.cpu.num_mem_refs 58160261 # number of memory refs -system.cpu.num_load_insts 37275864 # Number of load instructions -system.cpu.num_store_insts 20884397 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 406521804.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 12719094 # Number of branches fetched -system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% # Class of executed instruction -system.cpu.op_class::IntAlu 66342067 48.68% 57.07% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 57.07% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 57.07% # Class of executed instruction -system.cpu.op_class::FloatAdd 325584 0.24% 57.31% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::MemRead 37046611 27.18% 84.49% # Class of executed instruction -system.cpu.op_class::MemWrite 19133112 14.04% 98.53% # Class of executed instruction -system.cpu.op_class::FloatMemRead 250107 0.18% 98.72% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 1751285 1.28% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 136293808 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 146583 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.215868 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 57960841 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 150679 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 384.664359 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 829975500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.215868 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997855 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997855 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 462 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3598 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 116373719 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 116373719 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 37185800 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 37185800 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20759140 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits::cpu.data 15901 # number of SwapReq hits -system.cpu.dcache.SwapReq_hits::total 15901 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 57944940 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 57944940 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 57944940 # number of overall hits -system.cpu.dcache.overall_hits::total 57944940 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 45500 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 45500 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 105164 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 105164 # number of WriteReq misses -system.cpu.dcache.SwapReq_misses::cpu.data 15 # number of SwapReq misses -system.cpu.dcache.SwapReq_misses::total 15 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 150664 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 150664 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 150664 # number of overall misses -system.cpu.dcache.overall_misses::total 150664 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1655141000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1655141000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 6433166000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 6433166000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 446000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 446000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 8088307000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8088307000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 8088307000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8088307000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 20864304 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::cpu.data 15916 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::total 15916 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 58095604 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 58095604 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 58095604 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 58095604 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001222 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.001222 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005040 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005040 # miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000942 # miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_miss_rate::total 0.000942 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36376.725275 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36376.725275 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61172.701685 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61172.701685 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 29733.333333 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 29733.333333 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 53684.403706 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 53684.403706 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 53684.403706 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 53684.403706 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 123615 # number of writebacks -system.cpu.dcache.writebacks::total 123615 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45500 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 45500 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 105164 # number of WriteReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses::cpu.data 15 # number of SwapReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses::total 15 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 150664 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 150664 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 150664 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 150664 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1609641000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1609641000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6328002000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6328002000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 431000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 431000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7937643000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7937643000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7937643000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7937643000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005040 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000942 # mshr miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000942 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35376.725275 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35376.725275 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60172.701685 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60172.701685 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 28733.333333 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 28733.333333 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52684.403706 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52684.403706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52684.403706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52684.403706 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 184976 # number of replacements -system.cpu.icache.tags.tagsinuse 2004.091327 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 134366557 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 718.445531 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 144688165500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 2004.091327 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.978560 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.978560 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 456 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1427 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 269294186 # Number of tag accesses -system.cpu.icache.tags.data_accesses 269294186 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 134366557 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 134366557 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 134366557 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 134366557 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 134366557 # number of overall hits -system.cpu.icache.overall_hits::total 134366557 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 187024 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 187024 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 187024 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 187024 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 187024 # number of overall misses -system.cpu.icache.overall_misses::total 187024 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2844752500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2844752500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2844752500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2844752500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2844752500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2844752500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 134553581 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 134553581 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 134553581 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 134553581 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 134553581 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 134553581 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001390 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001390 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001390 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001390 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001390 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001390 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15210.628048 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15210.628048 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15210.628048 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15210.628048 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15210.628048 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15210.628048 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 184976 # number of writebacks -system.cpu.icache.writebacks::total 184976 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187024 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 187024 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 187024 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2657728500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2657728500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2657728500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2657728500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2657728500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2657728500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001390 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001390 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001390 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14210.628048 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14210.628048 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14210.628048 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14210.628048 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14210.628048 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14210.628048 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 99926 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32138.485238 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 536406 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 132694 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.042428 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 26729442000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 711.528666 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3108.349977 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28318.606595 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.021714 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.094859 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.864215 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.980789 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 188 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 570 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 10913 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20279 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 818 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 5486262 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 5486262 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 123615 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 123615 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 184923 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 184923 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 3868 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 3868 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 178794 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 178794 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 24230 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 24230 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 178794 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 28098 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 206892 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 178794 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 28098 # number of overall hits -system.cpu.l2cache.overall_hits::total 206892 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 101311 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 101311 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 8230 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 8230 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21270 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 21270 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 8230 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 122581 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 130811 # number of demand (read+write) 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-system.cpu.l2cache.ReadExReq_accesses::total 105179 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 187024 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 187024 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 45500 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 45500 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 187024 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 150679 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 337703 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 187024 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 150679 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 337703 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.963225 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.963225 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.044005 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.044005 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.467473 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.467473 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.044005 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.813524 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.387355 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.044005 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.813524 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.387355 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60506.761359 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60506.761359 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60540.522479 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60540.522479 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60504.348848 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60504.348848 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60540.522479 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60506.342745 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60508.493170 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60540.522479 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60506.342745 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60508.493170 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 85566 # number of writebacks -system.cpu.l2cache.writebacks::total 85566 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101311 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 101311 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 8230 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 8230 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21270 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21270 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 8230 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 122581 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 130811 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 8230 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 122581 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 130811 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5116890500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5116890500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 415948500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 415948500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1074227500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1074227500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 415948500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6191118000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6607066500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 415948500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6191118000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6607066500 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.963225 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.963225 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.044005 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.044005 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.467473 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.467473 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.044005 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.813524 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.387355 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.044005 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.813524 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.387355 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50506.761359 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50506.761359 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50540.522479 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50540.522479 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50504.348848 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50504.348848 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50540.522479 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50506.342745 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50508.493170 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50540.522479 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50506.342745 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50508.493170 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 669262 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 331559 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 66 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 3837 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3837 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 232524 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 209181 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 184976 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 37328 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 105179 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 105179 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 187024 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 45500 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 559024 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 447941 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1006965 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23808000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17554816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 41362816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 99926 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 5476224 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 437629 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.008919 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.094016 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 433726 99.11% 99.11% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3903 0.89% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 437629 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 643222000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 280536000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 226018500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 226995 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 96184 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 29500 # Transaction distribution -system.membus.trans_dist::WritebackDirty 85566 # Transaction distribution -system.membus.trans_dist::CleanEvict 10618 # Transaction distribution -system.membus.trans_dist::ReadExReq 101311 # Transaction distribution -system.membus.trans_dist::ReadExResp 101311 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 29500 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 357806 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 357806 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13848128 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13848128 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 130811 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 130811 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 130811 # Request fanout histogram -system.membus.reqLayer0.occupancy 570211500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 654055000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.3 # Layer utilization (%) +sim_seconds 0.203261 +sim_ticks 203260902500 +final_tick 203260902500 +sim_freq 1000000000000 +host_inst_rate 815865 +host_op_rate 826429 +host_tick_rate 1233889280 +host_mem_usage 273008 +host_seconds 164.73 +sim_insts 134398959 +sim_ops 136139187 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 203260902500 +system.physmem.bytes_read::cpu.inst 526720 +system.physmem.bytes_read::cpu.data 7845184 +system.physmem.bytes_read::total 8371904 +system.physmem.bytes_inst_read::cpu.inst 526720 +system.physmem.bytes_inst_read::total 526720 +system.physmem.bytes_written::writebacks 5476224 +system.physmem.bytes_written::total 5476224 +system.physmem.num_reads::cpu.inst 8230 +system.physmem.num_reads::cpu.data 122581 +system.physmem.num_reads::total 130811 +system.physmem.num_writes::writebacks 85566 +system.physmem.num_writes::total 85566 +system.physmem.bw_read::cpu.inst 2591349 +system.physmem.bw_read::cpu.data 38596621 +system.physmem.bw_read::total 41187970 +system.physmem.bw_inst_read::cpu.inst 2591349 +system.physmem.bw_inst_read::total 2591349 +system.physmem.bw_write::writebacks 26941846 +system.physmem.bw_write::total 26941846 +system.physmem.bw_total::writebacks 26941846 +system.physmem.bw_total::cpu.inst 2591349 +system.physmem.bw_total::cpu.data 38596621 +system.physmem.bw_total::total 68129817 +system.pwrStateResidencyTicks::UNDEFINED 203260902500 +system.cpu_clk_domain.clock 500 +system.cpu.workload.numSyscalls 1946 +system.cpu.pwrStateResidencyTicks::ON 203260902500 +system.cpu.numCycles 406521805 +system.cpu.numWorkItemsStarted 0 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+system.cpu.toL2Bus.trans_dist::ReadResp 232524 +system.cpu.toL2Bus.trans_dist::WritebackDirty 209181 +system.cpu.toL2Bus.trans_dist::WritebackClean 184976 +system.cpu.toL2Bus.trans_dist::CleanEvict 37328 +system.cpu.toL2Bus.trans_dist::ReadExReq 105179 +system.cpu.toL2Bus.trans_dist::ReadExResp 105179 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 187024 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 45500 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 559024 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 447941 +system.cpu.toL2Bus.pkt_count::total 1006965 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23808000 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17554816 +system.cpu.toL2Bus.pkt_size::total 41362816 +system.cpu.toL2Bus.snoops 99926 +system.cpu.toL2Bus.snoopTraffic 5476224 +system.cpu.toL2Bus.snoop_fanout::samples 437629 +system.cpu.toL2Bus.snoop_fanout::mean 0.008919 +system.cpu.toL2Bus.snoop_fanout::stdev 0.094016 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 433726 99.11% 99.11% +system.cpu.toL2Bus.snoop_fanout::1 3903 0.89% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 1 +system.cpu.toL2Bus.snoop_fanout::total 437629 +system.cpu.toL2Bus.reqLayer0.occupancy 643222000 +system.cpu.toL2Bus.reqLayer0.utilization 0.3 +system.cpu.toL2Bus.respLayer0.occupancy 280536000 +system.cpu.toL2Bus.respLayer0.utilization 0.1 +system.cpu.toL2Bus.respLayer1.occupancy 226018500 +system.cpu.toL2Bus.respLayer1.utilization 0.1 +system.membus.snoop_filter.tot_requests 226995 +system.membus.snoop_filter.hit_single_requests 96184 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 203260902500 +system.membus.trans_dist::ReadResp 29500 +system.membus.trans_dist::WritebackDirty 85566 +system.membus.trans_dist::CleanEvict 10618 +system.membus.trans_dist::ReadExReq 101311 +system.membus.trans_dist::ReadExResp 101311 +system.membus.trans_dist::ReadSharedReq 29500 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 357806 +system.membus.pkt_count::total 357806 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13848128 +system.membus.pkt_size::total 13848128 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 130811 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 130811 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 130811 +system.membus.reqLayer0.occupancy 570211500 +system.membus.reqLayer0.utilization 0.3 +system.membus.respLayer1.occupancy 654055000 +system.membus.respLayer1.utilization 0.3 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/config.ini index ac8a9f7d1..dba628374 100644 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/config.ini @@ -90,6 +90,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -165,8 +166,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -177,8 +176,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -239,7 +236,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=twolf smred cwd=build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-atomic drivers= @@ -248,14 +245,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/twolf +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/twolf gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -279,6 +277,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -290,7 +289,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -298,6 +297,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -306,6 +312,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -313,7 +320,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simerr b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simerr index aadc3d011..04cbe4a7c 100755 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simerr +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simerr @@ -1,2 +1,4 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simout b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simout index 5f855da74..15f6a3cf8 100755 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simout +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/simout @@ -3,21 +3,19 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-ato gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:38:25 -gem5 executing on e108600-lin, pid 23093 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/70.twolf/arm/linux/simple-atomic +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 18:00:23 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54878 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/70.twolf/arm/linux/simple-atomic Couldn't unlink build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-atomic/smred.sav Couldn't unlink build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 Standard Cell Placement and Global Routing Program Authors: Carl Sechen, Bill Swartz Yale University -info: Increasing stack size by one page. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 @@ -26,4 +24,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 99596491500 because target called exit() +122 123 124 Exiting @ tick 99596491500 because exiting with last active thread context diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt index de3dba60e..9f00c41e3 100644 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -1,262 +1,262 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.099596 # Number of seconds simulated -sim_ticks 99596491500 # Number of ticks simulated -final_tick 99596491500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2182343 # Simulator instruction rate (inst/s) -host_op_rate 2300541 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1261356268 # Simulator tick rate (ticks/s) -host_mem_usage 263320 # Number of bytes of host memory used -host_seconds 78.96 # Real time elapsed on the host -sim_insts 172317410 # Number of instructions simulated -sim_ops 181650342 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 759440208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 110533661 # Number of bytes read from this memory -system.physmem.bytes_read::total 869973869 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 759440208 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 759440208 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 45252940 # Number of bytes written to this memory -system.physmem.bytes_written::total 45252940 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 189860052 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 27777721 # Number of read requests responded to by this memory -system.physmem.num_reads::total 217637773 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 12386694 # Number of write requests responded to by this memory -system.physmem.num_writes::total 12386694 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7625170290 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1109814807 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8734985097 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7625170290 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7625170290 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 454362792 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 454362792 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7625170290 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1564177600 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9189347890 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 99596491500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 199192984 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 172317410 # Number of instructions committed -system.cpu.committedOps 181650342 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 143085668 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses -system.cpu.num_func_calls 3545028 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 32201008 # number of instructions that are conditional controls -system.cpu.num_int_insts 143085668 # number of integer instructions -system.cpu.num_fp_insts 1752310 # number of float instructions -system.cpu.num_int_register_reads 238310719 # number of times the integer registers were read -system.cpu.num_int_register_writes 98192342 # number of times the integer registers were written -system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written -system.cpu.num_cc_register_reads 543309970 # number of times the CC registers were read -system.cpu.num_cc_register_writes 190815535 # number of times the CC registers were written -system.cpu.num_mem_refs 40540779 # number of memory refs -system.cpu.num_load_insts 27896144 # Number of load instructions -system.cpu.num_store_insts 12644635 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 199192983.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 40300312 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 138988213 76.51% 76.51% # Class of executed instruction -system.cpu.op_class::IntMult 908940 0.50% 77.01% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 32754 0.02% 77.03% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 77.03% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 154829 0.09% 77.12% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 238880 0.13% 77.25% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 76016 0.04% 77.29% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 437591 0.24% 77.53% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 200806 0.11% 77.64% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.68% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.68% # Class of executed instruction -system.cpu.op_class::MemRead 27348059 15.06% 92.74% # Class of executed instruction -system.cpu.op_class::MemWrite 12498389 6.88% 99.62% # Class of executed instruction -system.cpu.op_class::FloatMemRead 548085 0.30% 99.92% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 146246 0.08% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 181650743 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 217614903 # Transaction distribution -system.membus.trans_dist::ReadResp 217637310 # Transaction distribution -system.membus.trans_dist::WriteReq 12364287 # Transaction distribution -system.membus.trans_dist::WriteResp 12364287 # Transaction distribution -system.membus.trans_dist::SoftPFReq 463 # Transaction distribution -system.membus.trans_dist::SoftPFResp 463 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 22407 # Transaction distribution -system.membus.trans_dist::StoreCondReq 22407 # Transaction distribution -system.membus.trans_dist::StoreCondResp 22407 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 379720104 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 80328830 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 460048934 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 759440208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 155786601 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 915226809 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 230024467 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 230024467 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 230024467 # Request fanout histogram +sim_seconds 0.099596 +sim_ticks 99596491500 +final_tick 99596491500 +sim_freq 1000000000000 +host_inst_rate 936229 +host_op_rate 986937 +host_tick_rate 541124372 +host_mem_usage 274820 +host_seconds 184.05 +sim_insts 172317410 +sim_ops 181650342 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 99596491500 +system.physmem.bytes_read::cpu.inst 759440208 +system.physmem.bytes_read::cpu.data 110533661 +system.physmem.bytes_read::total 869973869 +system.physmem.bytes_inst_read::cpu.inst 759440208 +system.physmem.bytes_inst_read::total 759440208 +system.physmem.bytes_written::cpu.data 45252940 +system.physmem.bytes_written::total 45252940 +system.physmem.num_reads::cpu.inst 189860052 +system.physmem.num_reads::cpu.data 27777721 +system.physmem.num_reads::total 217637773 +system.physmem.num_writes::cpu.data 12386694 +system.physmem.num_writes::total 12386694 +system.physmem.bw_read::cpu.inst 7625170290 +system.physmem.bw_read::cpu.data 1109814807 +system.physmem.bw_read::total 8734985097 +system.physmem.bw_inst_read::cpu.inst 7625170290 +system.physmem.bw_inst_read::total 7625170290 +system.physmem.bw_write::cpu.data 454362792 +system.physmem.bw_write::total 454362792 +system.physmem.bw_total::cpu.inst 7625170290 +system.physmem.bw_total::cpu.data 1564177600 +system.physmem.bw_total::total 9189347890 +system.pwrStateResidencyTicks::UNDEFINED 99596491500 +system.cpu_clk_domain.clock 500 +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 99596491500 +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.hits 0 +system.cpu.dstage2_mmu.stage2_tlb.misses 0 +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 99596491500 +system.cpu.dtb.walker.walks 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dtb.walker.walkRequestOrigin::total 0 +system.cpu.dtb.inst_hits 0 +system.cpu.dtb.inst_misses 0 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.flush_tlb 0 +system.cpu.dtb.flush_tlb_mva 0 +system.cpu.dtb.flush_tlb_mva_asid 0 +system.cpu.dtb.flush_tlb_asid 0 +system.cpu.dtb.flush_entries 0 +system.cpu.dtb.align_faults 0 +system.cpu.dtb.prefetch_faults 0 +system.cpu.dtb.domain_faults 0 +system.cpu.dtb.perms_faults 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.inst_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 99596491500 +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.hits 0 +system.cpu.istage2_mmu.stage2_tlb.misses 0 +system.cpu.istage2_mmu.stage2_tlb.accesses 0 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 99596491500 +system.cpu.itb.walker.walks 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.itb.walker.walkRequestOrigin::total 0 +system.cpu.itb.inst_hits 0 +system.cpu.itb.inst_misses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.flush_tlb 0 +system.cpu.itb.flush_tlb_mva 0 +system.cpu.itb.flush_tlb_mva_asid 0 +system.cpu.itb.flush_tlb_asid 0 +system.cpu.itb.flush_entries 0 +system.cpu.itb.align_faults 0 +system.cpu.itb.prefetch_faults 0 +system.cpu.itb.domain_faults 0 +system.cpu.itb.perms_faults 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.inst_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 400 +system.cpu.pwrStateResidencyTicks::ON 99596491500 +system.cpu.numCycles 199192984 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 172317410 +system.cpu.committedOps 181650342 +system.cpu.num_int_alu_accesses 143085668 +system.cpu.num_fp_alu_accesses 1752310 +system.cpu.num_func_calls 3545028 +system.cpu.num_conditional_control_insts 32201008 +system.cpu.num_int_insts 143085668 +system.cpu.num_fp_insts 1752310 +system.cpu.num_int_register_reads 238310719 +system.cpu.num_int_register_writes 98192342 +system.cpu.num_fp_register_reads 2822225 +system.cpu.num_fp_register_writes 2378039 +system.cpu.num_cc_register_reads 543309970 +system.cpu.num_cc_register_writes 190815535 +system.cpu.num_mem_refs 40540779 +system.cpu.num_load_insts 27896144 +system.cpu.num_store_insts 12644635 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 199192984 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 40300312 +system.cpu.op_class::No_OpClass 0 0.00% 0.00% +system.cpu.op_class::IntAlu 138988213 76.51% 76.51% +system.cpu.op_class::IntMult 908940 0.50% 77.01% +system.cpu.op_class::IntDiv 0 0.00% 77.01% +system.cpu.op_class::FloatAdd 0 0.00% 77.01% +system.cpu.op_class::FloatCmp 0 0.00% 77.01% +system.cpu.op_class::FloatCvt 0 0.00% 77.01% +system.cpu.op_class::FloatMult 0 0.00% 77.01% +system.cpu.op_class::FloatMultAcc 0 0.00% 77.01% +system.cpu.op_class::FloatDiv 0 0.00% 77.01% +system.cpu.op_class::FloatMisc 0 0.00% 77.01% +system.cpu.op_class::FloatSqrt 0 0.00% 77.01% +system.cpu.op_class::SimdAdd 0 0.00% 77.01% +system.cpu.op_class::SimdAddAcc 0 0.00% 77.01% +system.cpu.op_class::SimdAlu 0 0.00% 77.01% +system.cpu.op_class::SimdCmp 0 0.00% 77.01% +system.cpu.op_class::SimdCvt 0 0.00% 77.01% +system.cpu.op_class::SimdMisc 0 0.00% 77.01% +system.cpu.op_class::SimdMult 0 0.00% 77.01% +system.cpu.op_class::SimdMultAcc 0 0.00% 77.01% +system.cpu.op_class::SimdShift 0 0.00% 77.01% +system.cpu.op_class::SimdShiftAcc 0 0.00% 77.01% +system.cpu.op_class::SimdSqrt 0 0.00% 77.01% +system.cpu.op_class::SimdFloatAdd 32754 0.02% 77.03% +system.cpu.op_class::SimdFloatAlu 0 0.00% 77.03% +system.cpu.op_class::SimdFloatCmp 154829 0.09% 77.12% +system.cpu.op_class::SimdFloatCvt 238880 0.13% 77.25% +system.cpu.op_class::SimdFloatDiv 76016 0.04% 77.29% +system.cpu.op_class::SimdFloatMisc 437591 0.24% 77.53% +system.cpu.op_class::SimdFloatMult 200806 0.11% 77.64% +system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.68% +system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.68% +system.cpu.op_class::MemRead 27348059 15.06% 92.74% +system.cpu.op_class::MemWrite 12498389 6.88% 99.62% +system.cpu.op_class::FloatMemRead 548085 0.30% 99.92% +system.cpu.op_class::FloatMemWrite 146246 0.08% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 181650743 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 99596491500 +system.membus.trans_dist::ReadReq 217614903 +system.membus.trans_dist::ReadResp 217637310 +system.membus.trans_dist::WriteReq 12364287 +system.membus.trans_dist::WriteResp 12364287 +system.membus.trans_dist::SoftPFReq 463 +system.membus.trans_dist::SoftPFResp 463 +system.membus.trans_dist::LoadLockedReq 22407 +system.membus.trans_dist::StoreCondReq 22407 +system.membus.trans_dist::StoreCondResp 22407 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 379720104 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 80328830 +system.membus.pkt_count::total 460048934 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 759440208 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 155786601 +system.membus.pkt_size::total 915226809 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 230024467 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 230024467 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 230024467 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/config.ini index 4b53ac3b8..5b49b590a 100644 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/config.ini +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/config.ini @@ -87,6 +87,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -96,14 +97,14 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -117,6 +118,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -129,15 +131,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dstage2_mmu] type=ArmStage2MMU @@ -193,14 +196,14 @@ port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -214,6 +217,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -226,15 +230,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=ArmInterrupts @@ -253,8 +258,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -265,8 +268,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -325,14 +326,14 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -346,6 +347,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -358,15 +360,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -402,7 +405,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=twolf smred cwd=build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-timing drivers= @@ -411,14 +414,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/twolf +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/twolf gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -442,6 +446,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -453,7 +458,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -461,6 +466,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -469,6 +481,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -476,7 +489,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simerr b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simerr index aadc3d011..04cbe4a7c 100755 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simerr +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simerr @@ -1,2 +1,4 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simout b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simout index c9961e3be..07d5ab013 100755 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simout +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/simout @@ -3,21 +3,19 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:45:16 -gem5 executing on e108600-lin, pid 23175 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/70.twolf/arm/linux/simple-timing +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 17:57:55 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54318 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/70.twolf/arm/linux/simple-timing Couldn't unlink build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-timing/smred.sav Couldn't unlink build/ARM/tests/opt/quick/se/70.twolf/arm/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 Standard Cell Placement and Global Routing Program Authors: Carl Sechen, Bill Swartz Yale University -info: Increasing stack size by one page. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 @@ -26,4 +24,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 230197694500 because target called exit() +122 123 124 Exiting @ tick 230201146500 because exiting with last active thread context diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index 59d720796..fa75e6a0d 100644 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -1,669 +1,669 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.230201 # Number of seconds simulated -sim_ticks 230201146500 # Number of ticks simulated -final_tick 230201146500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1601768 # Simulator instruction rate (inst/s) -host_op_rate 1688668 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2145736650 # Simulator tick rate (ticks/s) -host_mem_usage 273052 # Number of bytes of host memory used -host_seconds 107.28 # Real time elapsed on the host -sim_insts 171842484 # Number of instructions simulated -sim_ops 181165371 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 110336 # Number of bytes read from this memory -system.physmem.bytes_read::total 220992 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 110656 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 110656 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 1729 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1724 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3453 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 480693 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 479303 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 959995 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 480693 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 480693 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 480693 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 479303 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 959995 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 230201146500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 460402293 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 171842484 # Number of instructions committed -system.cpu.committedOps 181165371 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 143085668 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses -system.cpu.num_func_calls 3545028 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 32201008 # number of instructions that are conditional controls -system.cpu.num_int_insts 143085668 # number of integer instructions -system.cpu.num_fp_insts 1752310 # number of float instructions -system.cpu.num_int_register_reads 238631773 # number of times the integer registers were read -system.cpu.num_int_register_writes 98192342 # number of times the integer registers were written -system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written -system.cpu.num_cc_register_reads 626384530 # number of times the CC registers were read -system.cpu.num_cc_register_writes 190815535 # number of times the CC registers were written -system.cpu.num_mem_refs 40540779 # number of memory refs -system.cpu.num_load_insts 27896144 # Number of load instructions -system.cpu.num_store_insts 12644635 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 460402292.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 40300312 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 138988213 76.51% 76.51% # Class of executed instruction -system.cpu.op_class::IntMult 908940 0.50% 77.01% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 32754 0.02% 77.03% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 77.03% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 154829 0.09% 77.12% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 238880 0.13% 77.25% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 76016 0.04% 77.29% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 437591 0.24% 77.53% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 200806 0.11% 77.64% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.68% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.68% # Class of executed instruction -system.cpu.op_class::MemRead 27348059 15.06% 92.74% # Class of executed instruction -system.cpu.op_class::MemWrite 12498389 6.88% 99.62% # Class of executed instruction -system.cpu.op_class::FloatMemRead 548085 0.30% 99.92% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 146246 0.08% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 181650743 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 40 # number of replacements -system.cpu.dcache.tags.tagsinuse 1363.564425 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22449.762996 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1363.564425 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.332901 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.332901 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1345 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.427002 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 80330619 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 80330619 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 27754163 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 27754163 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12363187 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40117350 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40117350 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40117812 # number of overall hits -system.cpu.dcache.overall_hits::total 40117812 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 688 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 688 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1100 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1100 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1788 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1788 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1789 # number of overall misses -system.cpu.dcache.overall_misses::total 1789 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 40571000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 40571000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 68930500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 68930500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 109501500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 109501500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 109501500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 109501500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 27754851 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 27754851 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 463 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 40119138 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 40119138 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 40119601 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 40119601 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000025 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000025 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000089 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002160 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.002160 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000045 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000045 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000045 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58969.476744 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 58969.476744 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62664.090909 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62664.090909 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61242.449664 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61242.449664 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61208.216881 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61208.216881 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 16 # number of writebacks -system.cpu.dcache.writebacks::total 16 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 688 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 688 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1100 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1100 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1788 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1788 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 39883000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 39883000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 67830500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 67830500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 62000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 62000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 107713500 # number of demand (read+write) MSHR miss cycles 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miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40403.146509 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 40403.146509 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40403.146509 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 40403.146509 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2511.620011 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2869 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3453 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.830872 # Average number of references to valid blocks. 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ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1729 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1724 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3453 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1729 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1724 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 3453 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 55176500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 55176500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 87407000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 87407000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31941500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31941500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 87407000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 87118000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 174525000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 87407000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 87118000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 174525000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992727 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992727 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.566699 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.917271 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.917271 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.713430 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.713430 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50527.930403 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50527.930403 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50553.499132 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50553.499132 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50540.348101 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50540.348101 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50553.499132 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50532.482599 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50543.006082 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50553.499132 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50532.482599 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50543.006082 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 6386 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 1644 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 64 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1506 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 24 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1100 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1100 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 3051 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 689 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7608 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3618 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 11226 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 291648 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 115520 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 407168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 4840 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.033471 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.179882 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 4678 96.65% 96.65% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 162 3.35% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4840 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4715000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 4576500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2683500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 3453 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 2361 # Transaction distribution -system.membus.trans_dist::ReadExReq 1092 # Transaction distribution -system.membus.trans_dist::ReadExResp 1092 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 2361 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6906 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6906 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 220992 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 220992 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 3453 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3453 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3453 # Request fanout histogram -system.membus.reqLayer0.occupancy 3601500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 17265000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +sim_seconds 0.230201 +sim_ticks 230201146500 +final_tick 230201146500 +sim_freq 1000000000000 +host_inst_rate 699032 +host_op_rate 736956 +host_tick_rate 936426495 +host_mem_usage 284812 +host_seconds 245.83 +sim_insts 171842484 +sim_ops 181165371 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 230201146500 +system.physmem.bytes_read::cpu.inst 110656 +system.physmem.bytes_read::cpu.data 110336 +system.physmem.bytes_read::total 220992 +system.physmem.bytes_inst_read::cpu.inst 110656 +system.physmem.bytes_inst_read::total 110656 +system.physmem.num_reads::cpu.inst 1729 +system.physmem.num_reads::cpu.data 1724 +system.physmem.num_reads::total 3453 +system.physmem.bw_read::cpu.inst 480693 +system.physmem.bw_read::cpu.data 479303 +system.physmem.bw_read::total 959995 +system.physmem.bw_inst_read::cpu.inst 480693 +system.physmem.bw_inst_read::total 480693 +system.physmem.bw_total::cpu.inst 480693 +system.physmem.bw_total::cpu.data 479303 +system.physmem.bw_total::total 959995 +system.pwrStateResidencyTicks::UNDEFINED 230201146500 +system.cpu_clk_domain.clock 500 +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 230201146500 +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.hits 0 +system.cpu.dstage2_mmu.stage2_tlb.misses 0 +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 230201146500 +system.cpu.dtb.walker.walks 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dtb.walker.walkRequestOrigin::total 0 +system.cpu.dtb.inst_hits 0 +system.cpu.dtb.inst_misses 0 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.flush_tlb 0 +system.cpu.dtb.flush_tlb_mva 0 +system.cpu.dtb.flush_tlb_mva_asid 0 +system.cpu.dtb.flush_tlb_asid 0 +system.cpu.dtb.flush_entries 0 +system.cpu.dtb.align_faults 0 +system.cpu.dtb.prefetch_faults 0 +system.cpu.dtb.domain_faults 0 +system.cpu.dtb.perms_faults 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.inst_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 230201146500 +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.hits 0 +system.cpu.istage2_mmu.stage2_tlb.misses 0 +system.cpu.istage2_mmu.stage2_tlb.accesses 0 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 230201146500 +system.cpu.itb.walker.walks 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.itb.walker.walkRequestOrigin::total 0 +system.cpu.itb.inst_hits 0 +system.cpu.itb.inst_misses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.flush_tlb 0 +system.cpu.itb.flush_tlb_mva 0 +system.cpu.itb.flush_tlb_mva_asid 0 +system.cpu.itb.flush_tlb_asid 0 +system.cpu.itb.flush_entries 0 +system.cpu.itb.align_faults 0 +system.cpu.itb.prefetch_faults 0 +system.cpu.itb.domain_faults 0 +system.cpu.itb.perms_faults 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.inst_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 400 +system.cpu.pwrStateResidencyTicks::ON 230201146500 +system.cpu.numCycles 460402293 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 171842484 +system.cpu.committedOps 181165371 +system.cpu.num_int_alu_accesses 143085668 +system.cpu.num_fp_alu_accesses 1752310 +system.cpu.num_func_calls 3545028 +system.cpu.num_conditional_control_insts 32201008 +system.cpu.num_int_insts 143085668 +system.cpu.num_fp_insts 1752310 +system.cpu.num_int_register_reads 238631773 +system.cpu.num_int_register_writes 98192342 +system.cpu.num_fp_register_reads 2822225 +system.cpu.num_fp_register_writes 2378039 +system.cpu.num_cc_register_reads 626384530 +system.cpu.num_cc_register_writes 190815535 +system.cpu.num_mem_refs 40540779 +system.cpu.num_load_insts 27896144 +system.cpu.num_store_insts 12644635 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 460402293 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 40300312 +system.cpu.op_class::No_OpClass 0 0.00% 0.00% +system.cpu.op_class::IntAlu 138988213 76.51% 76.51% +system.cpu.op_class::IntMult 908940 0.50% 77.01% +system.cpu.op_class::IntDiv 0 0.00% 77.01% +system.cpu.op_class::FloatAdd 0 0.00% 77.01% +system.cpu.op_class::FloatCmp 0 0.00% 77.01% +system.cpu.op_class::FloatCvt 0 0.00% 77.01% +system.cpu.op_class::FloatMult 0 0.00% 77.01% +system.cpu.op_class::FloatMultAcc 0 0.00% 77.01% +system.cpu.op_class::FloatDiv 0 0.00% 77.01% +system.cpu.op_class::FloatMisc 0 0.00% 77.01% +system.cpu.op_class::FloatSqrt 0 0.00% 77.01% +system.cpu.op_class::SimdAdd 0 0.00% 77.01% +system.cpu.op_class::SimdAddAcc 0 0.00% 77.01% +system.cpu.op_class::SimdAlu 0 0.00% 77.01% +system.cpu.op_class::SimdCmp 0 0.00% 77.01% +system.cpu.op_class::SimdCvt 0 0.00% 77.01% +system.cpu.op_class::SimdMisc 0 0.00% 77.01% +system.cpu.op_class::SimdMult 0 0.00% 77.01% +system.cpu.op_class::SimdMultAcc 0 0.00% 77.01% +system.cpu.op_class::SimdShift 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+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992727 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992727 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.566699 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.566699 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.917271 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.917271 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.566699 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963667 +system.cpu.l2cache.demand_mshr_miss_rate::total 0.713430 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.566699 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963667 +system.cpu.l2cache.overall_mshr_miss_rate::total 0.713430 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50527.930403 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50527.930403 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50553.499132 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50553.499132 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50540.348101 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50540.348101 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50553.499132 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50532.482599 +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50543.006082 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50553.499132 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50532.482599 +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50543.006082 +system.cpu.toL2Bus.snoop_filter.tot_requests 6386 +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1644 +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 64 +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 230201146500 +system.cpu.toL2Bus.trans_dist::ReadResp 3740 +system.cpu.toL2Bus.trans_dist::WritebackDirty 16 +system.cpu.toL2Bus.trans_dist::WritebackClean 1506 +system.cpu.toL2Bus.trans_dist::CleanEvict 24 +system.cpu.toL2Bus.trans_dist::ReadExReq 1100 +system.cpu.toL2Bus.trans_dist::ReadExResp 1100 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 3051 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 689 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7608 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3618 +system.cpu.toL2Bus.pkt_count::total 11226 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 291648 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 115520 +system.cpu.toL2Bus.pkt_size::total 407168 +system.cpu.toL2Bus.snoops 0 +system.cpu.toL2Bus.snoopTraffic 0 +system.cpu.toL2Bus.snoop_fanout::samples 4840 +system.cpu.toL2Bus.snoop_fanout::mean 0.033471 +system.cpu.toL2Bus.snoop_fanout::stdev 0.179882 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 4678 96.65% 96.65% +system.cpu.toL2Bus.snoop_fanout::1 162 3.35% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 1 +system.cpu.toL2Bus.snoop_fanout::total 4840 +system.cpu.toL2Bus.reqLayer0.occupancy 4715000 +system.cpu.toL2Bus.reqLayer0.utilization 0.0 +system.cpu.toL2Bus.respLayer0.occupancy 4576500 +system.cpu.toL2Bus.respLayer0.utilization 0.0 +system.cpu.toL2Bus.respLayer1.occupancy 2683500 +system.cpu.toL2Bus.respLayer1.utilization 0.0 +system.membus.snoop_filter.tot_requests 3453 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 230201146500 +system.membus.trans_dist::ReadResp 2361 +system.membus.trans_dist::ReadExReq 1092 +system.membus.trans_dist::ReadExResp 1092 +system.membus.trans_dist::ReadSharedReq 2361 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6906 +system.membus.pkt_count::total 6906 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 220992 +system.membus.pkt_size::total 220992 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 3453 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 3453 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 3453 +system.membus.reqLayer0.occupancy 3601500 +system.membus.reqLayer0.utilization 0.0 +system.membus.respLayer1.occupancy 17265000 +system.membus.respLayer1.utilization 0.0 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini index 3fd1ef26a..a38ce2f6f 100644 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini @@ -88,6 +88,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -118,7 +119,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=twolf smred cwd=build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic drivers= @@ -127,14 +128,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/sparc/linux/twolf +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/sparc/linux/twolf gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -158,6 +160,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -169,7 +172,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -177,6 +180,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -185,6 +195,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -192,7 +203,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/simerr b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/simerr index aadc3d011..04cbe4a7c 100755 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/simerr +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/simerr @@ -1,2 +1,4 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/simout index 87c7a18cb..22a19a069 100755 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/simout @@ -3,15 +3,14 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:30:06 -gem5 started Jul 21 2016 14:30:36 -gem5 executing on e108600-lin, pid 38671 -command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/70.twolf/sparc/linux/simple-atomic +gem5 compiled Apr 3 2017 18:41:19 +gem5 started Apr 3 2017 18:41:37 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 64822 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/70.twolf/sparc/linux/simple-atomic Couldn't unlink build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic/smred.sav Couldn't unlink build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 Standard Cell Placement and Global Routing Program @@ -25,5 +24,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -info: Increasing stack size by one page. -122 123 124 Exiting @ tick 96722945000 because target called exit() +122 123 124 Exiting @ tick 96722945000 because exiting with last active thread context diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt index be67f7e8e..e75fdc7de 100644 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt @@ -1,139 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.096723 # Number of seconds simulated -sim_ticks 96722945000 # Number of ticks simulated -final_tick 96722945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2624723 # Simulator instruction rate (inst/s) -host_op_rate 2624726 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1312370434 # Simulator tick rate (ticks/s) -host_mem_usage 246444 # Number of bytes of host memory used -host_seconds 73.70 # Real time elapsed on the host -sim_insts 193444518 # Number of instructions simulated -sim_ops 193444756 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 96722945000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 773782140 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 223463413 # Number of bytes read from this memory -system.physmem.bytes_read::total 997245553 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 773782140 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 773782140 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 72065412 # Number of bytes written to this memory -system.physmem.bytes_written::total 72065412 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 193445535 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 57735068 # Number of read requests responded to by this memory -system.physmem.num_reads::total 251180603 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 18976439 # Number of write requests responded to by this memory -system.physmem.num_writes::total 18976439 # Number of write requests responded to by this memory -system.physmem.num_other::cpu.data 22406 # Number of other requests responded to by this memory -system.physmem.num_other::total 22406 # Number of other requests responded to by this memory -system.physmem.bw_read::cpu.inst 7999985319 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2310345420 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10310330739 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7999985319 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7999985319 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 745070490 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 745070490 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7999985319 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3055415910 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11055401229 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 96722945000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.numSyscalls 401 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 96722945000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 193445891 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 193444518 # Number of instructions committed -system.cpu.committedOps 193444756 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 167974806 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses -system.cpu.num_func_calls 1957920 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8665106 # number of instructions that are conditional controls -system.cpu.num_int_insts 167974806 # number of integer instructions -system.cpu.num_fp_insts 1970372 # number of float instructions -system.cpu.num_int_register_reads 352617941 # number of times the integer registers were read -system.cpu.num_int_register_writes 163060124 # number of times the integer registers were written -system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written -system.cpu.num_mem_refs 76733958 # number of memory refs -system.cpu.num_load_insts 57735091 # Number of load instructions -system.cpu.num_store_insts 18998867 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 193445890.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 15132745 # Number of branches fetched -system.cpu.op_class::No_OpClass 13329871 6.89% 6.89% # Class of executed instruction -system.cpu.op_class::IntAlu 102506896 52.99% 59.88% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 59.88% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 59.88% # Class of executed instruction -system.cpu.op_class::FloatAdd 875036 0.45% 60.33% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::MemRead 56837780 29.38% 89.71% # Class of executed instruction -system.cpu.op_class::MemWrite 18800854 9.72% 99.43% # Class of executed instruction -system.cpu.op_class::FloatMemRead 897323 0.46% 99.90% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 198013 0.10% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 193445773 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 96722945000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 251180603 # Transaction distribution -system.membus.trans_dist::ReadResp 251180603 # Transaction distribution -system.membus.trans_dist::WriteReq 18976439 # Transaction distribution -system.membus.trans_dist::WriteResp 18976439 # Transaction distribution -system.membus.trans_dist::SwapReq 22406 # Transaction distribution -system.membus.trans_dist::SwapResp 22406 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 386891070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 153467826 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 540358896 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 773782140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 295708073 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1069490213 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 270179448 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 270179448 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 270179448 # Request fanout histogram +sim_seconds 0.096723 +sim_ticks 96722945000 +final_tick 96722945000 +sim_freq 1000000000000 +host_inst_rate 1253206 +host_op_rate 1253207 +host_tick_rate 626607046 +host_mem_usage 258716 +host_seconds 154.36 +sim_insts 193444518 +sim_ops 193444756 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 96722945000 +system.physmem.bytes_read::cpu.inst 773782140 +system.physmem.bytes_read::cpu.data 223463413 +system.physmem.bytes_read::total 997245553 +system.physmem.bytes_inst_read::cpu.inst 773782140 +system.physmem.bytes_inst_read::total 773782140 +system.physmem.bytes_written::cpu.data 72065412 +system.physmem.bytes_written::total 72065412 +system.physmem.num_reads::cpu.inst 193445535 +system.physmem.num_reads::cpu.data 57735068 +system.physmem.num_reads::total 251180603 +system.physmem.num_writes::cpu.data 18976439 +system.physmem.num_writes::total 18976439 +system.physmem.num_other::cpu.data 22406 +system.physmem.num_other::total 22406 +system.physmem.bw_read::cpu.inst 7999985319 +system.physmem.bw_read::cpu.data 2310345420 +system.physmem.bw_read::total 10310330739 +system.physmem.bw_inst_read::cpu.inst 7999985319 +system.physmem.bw_inst_read::total 7999985319 +system.physmem.bw_write::cpu.data 745070490 +system.physmem.bw_write::total 745070490 +system.physmem.bw_total::cpu.inst 7999985319 +system.physmem.bw_total::cpu.data 3055415910 +system.physmem.bw_total::total 11055401229 +system.pwrStateResidencyTicks::UNDEFINED 96722945000 +system.cpu_clk_domain.clock 500 +system.cpu.workload.numSyscalls 401 +system.cpu.pwrStateResidencyTicks::ON 96722945000 +system.cpu.numCycles 193445891 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 193444518 +system.cpu.committedOps 193444756 +system.cpu.num_int_alu_accesses 167974806 +system.cpu.num_fp_alu_accesses 1970372 +system.cpu.num_func_calls 1957920 +system.cpu.num_conditional_control_insts 8665106 +system.cpu.num_int_insts 167974806 +system.cpu.num_fp_insts 1970372 +system.cpu.num_int_register_reads 352617941 +system.cpu.num_int_register_writes 163060124 +system.cpu.num_fp_register_reads 3181089 +system.cpu.num_fp_register_writes 2974850 +system.cpu.num_mem_refs 76733958 +system.cpu.num_load_insts 57735091 +system.cpu.num_store_insts 18998867 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 193445891 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 15132745 +system.cpu.op_class::No_OpClass 13329871 6.89% 6.89% +system.cpu.op_class::IntAlu 102506896 52.99% 59.88% +system.cpu.op_class::IntMult 0 0.00% 59.88% +system.cpu.op_class::IntDiv 0 0.00% 59.88% +system.cpu.op_class::FloatAdd 875036 0.45% 60.33% +system.cpu.op_class::FloatCmp 0 0.00% 60.33% +system.cpu.op_class::FloatCvt 0 0.00% 60.33% +system.cpu.op_class::FloatMult 0 0.00% 60.33% +system.cpu.op_class::FloatMultAcc 0 0.00% 60.33% +system.cpu.op_class::FloatDiv 0 0.00% 60.33% +system.cpu.op_class::FloatMisc 0 0.00% 60.33% +system.cpu.op_class::FloatSqrt 0 0.00% 60.33% +system.cpu.op_class::SimdAdd 0 0.00% 60.33% +system.cpu.op_class::SimdAddAcc 0 0.00% 60.33% +system.cpu.op_class::SimdAlu 0 0.00% 60.33% +system.cpu.op_class::SimdCmp 0 0.00% 60.33% +system.cpu.op_class::SimdCvt 0 0.00% 60.33% +system.cpu.op_class::SimdMisc 0 0.00% 60.33% +system.cpu.op_class::SimdMult 0 0.00% 60.33% +system.cpu.op_class::SimdMultAcc 0 0.00% 60.33% +system.cpu.op_class::SimdShift 0 0.00% 60.33% +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.33% +system.cpu.op_class::SimdSqrt 0 0.00% 60.33% +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.33% +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.33% +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.33% +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.33% +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.33% +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.33% +system.cpu.op_class::SimdFloatMult 0 0.00% 60.33% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.33% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.33% +system.cpu.op_class::MemRead 56837780 29.38% 89.71% +system.cpu.op_class::MemWrite 18800854 9.72% 99.43% +system.cpu.op_class::FloatMemRead 897323 0.46% 99.90% +system.cpu.op_class::FloatMemWrite 198013 0.10% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 193445773 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 96722945000 +system.membus.trans_dist::ReadReq 251180603 +system.membus.trans_dist::ReadResp 251180603 +system.membus.trans_dist::WriteReq 18976439 +system.membus.trans_dist::WriteResp 18976439 +system.membus.trans_dist::SwapReq 22406 +system.membus.trans_dist::SwapResp 22406 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 386891070 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 153467826 +system.membus.pkt_count::total 540358896 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 773782140 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 295708073 +system.membus.pkt_size::total 1069490213 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 270179448 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 270179448 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 270179448 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/config.ini index f82285b56..02b45e3d3 100644 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/config.ini @@ -85,6 +85,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -94,14 +95,14 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -115,6 +116,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -127,15 +129,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dtb] type=SparcTLB @@ -145,14 +148,14 @@ size=64 [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -166,6 +169,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -178,15 +182,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=SparcInterrupts @@ -204,14 +209,14 @@ size=64 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -225,6 +230,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -237,15 +243,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -281,7 +288,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=twolf smred cwd=build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing drivers= @@ -290,14 +297,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/sparc/linux/twolf +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/sparc/linux/twolf gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -321,6 +329,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -332,7 +341,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -340,6 +349,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -348,6 +364,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -355,7 +372,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simerr b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simerr index aadc3d011..04cbe4a7c 100755 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simerr +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simerr @@ -1,2 +1,4 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simout index fcd3cff78..ba3d0f65e 100755 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/simout @@ -3,15 +3,14 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:30:06 -gem5 started Jul 21 2016 14:30:36 -gem5 executing on e108600-lin, pid 38674 -command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/70.twolf/sparc/linux/simple-timing +gem5 compiled Apr 3 2017 18:41:19 +gem5 started Apr 3 2017 18:41:39 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 64871 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/70.twolf/sparc/linux/simple-timing Couldn't unlink build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing/smred.sav Couldn't unlink build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 Standard Cell Placement and Global Routing Program @@ -25,5 +24,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -info: Increasing stack size by one page. -122 123 124 Exiting @ tick 270599529500 because target called exit() +122 123 124 Exiting @ tick 270604702500 because exiting with last active thread context diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt index a594c0ddc..dadd27923 100644 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -1,536 +1,536 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.270605 # Number of seconds simulated -sim_ticks 270604702500 # Number of ticks simulated -final_tick 270604702500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1830893 # Simulator instruction rate (inst/s) -host_op_rate 1830895 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2561189341 # Simulator tick rate (ticks/s) -host_mem_usage 255916 # Number of bytes of host memory used -host_seconds 105.66 # Real time elapsed on the host -sim_insts 193444518 # Number of instructions simulated -sim_ops 193444756 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 100864 # Number of bytes read from this memory -system.physmem.bytes_read::total 331072 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 230208 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 230208 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3597 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1576 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5173 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 850717 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 372736 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1223453 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 850717 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 850717 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 850717 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 372736 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1223453 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.numSyscalls 401 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 270604702500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 541209405 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 193444518 # Number of instructions committed -system.cpu.committedOps 193444756 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 167974806 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses -system.cpu.num_func_calls 1957920 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8665106 # number of instructions that are conditional controls -system.cpu.num_int_insts 167974806 # number of integer instructions -system.cpu.num_fp_insts 1970372 # number of float instructions -system.cpu.num_int_register_reads 352617941 # number of times the integer registers were read -system.cpu.num_int_register_writes 163060123 # number of times the integer registers were written -system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written -system.cpu.num_mem_refs 76733958 # number of memory refs -system.cpu.num_load_insts 57735091 # Number of load instructions -system.cpu.num_store_insts 18998867 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 541209404.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 15132745 # Number of branches fetched -system.cpu.op_class::No_OpClass 13329871 6.89% 6.89% # Class of executed instruction -system.cpu.op_class::IntAlu 102506896 52.99% 59.88% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 59.88% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 59.88% # Class of executed instruction -system.cpu.op_class::FloatAdd 875036 0.45% 60.33% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::MemRead 56837780 29.38% 89.71% # Class of executed instruction -system.cpu.op_class::MemWrite 18800854 9.72% 99.43% # Class of executed instruction -system.cpu.op_class::FloatMemRead 897323 0.46% 99.90% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 198013 0.10% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 193445773 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2 # number of replacements -system.cpu.dcache.tags.tagsinuse 1237.152973 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1237.152973 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.302039 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.302039 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1574 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1237 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.384277 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 153469402 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 153469402 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18975362 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits::cpu.data 22405 # number of SwapReq hits -system.cpu.dcache.SwapReq_hits::total 22405 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 76709932 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 76709932 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 76709932 # number of overall hits -system.cpu.dcache.overall_hits::total 76709932 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 498 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 498 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1077 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1077 # number of WriteReq misses -system.cpu.dcache.SwapReq_misses::cpu.data 1 # number of SwapReq misses -system.cpu.dcache.SwapReq_misses::total 1 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 1575 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1575 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1575 # number of overall misses -system.cpu.dcache.overall_misses::total 1575 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 31375500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31375500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 67852000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 67852000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 63000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 63000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 99227500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 99227500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 99227500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 99227500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 57735068 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 57735068 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 18976439 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::cpu.data 22406 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::total 22406 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 76711507 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 76711507 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 76711507 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 76711507 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000009 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000057 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000057 # miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000045 # miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_miss_rate::total 0.000045 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000021 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000021 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000021 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63003.012048 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63003.012048 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000.928505 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63000.928505 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 63000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 63000 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63001.587302 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63001.587302 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63001.587302 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63001.587302 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2 # number of writebacks -system.cpu.dcache.writebacks::total 2 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1077 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1077 # number of WriteReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses::cpu.data 1 # number of SwapReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses::total 1 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1575 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1575 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1575 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1575 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30877500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30877500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 66775000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 66775000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 62000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 62000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 97652500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 97652500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 97652500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 97652500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000057 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000045 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000021 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000021 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62003.012048 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62003.012048 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000.928505 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000.928505 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 62000 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 62000 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62001.587302 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 62001.587302 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62001.587302 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 62001.587302 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 10362 # number of replacements -system.cpu.icache.tags.tagsinuse 1591.520958 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1591.520958 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.777110 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.777110 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1926 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 624 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 514 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 687 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.940430 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 386903360 # Number of tag accesses -system.cpu.icache.tags.data_accesses 386903360 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 193433248 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 193433248 # number of overall hits -system.cpu.icache.overall_hits::total 193433248 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12288 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12288 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12288 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12288 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12288 # number of overall misses -system.cpu.icache.overall_misses::total 12288 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 339828000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 339828000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 339828000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 339828000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 339828000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 339828000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 193445536 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 193445536 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 193445536 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 193445536 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 193445536 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 193445536 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000064 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000064 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000064 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000064 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000064 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000064 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27655.273438 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27655.273438 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27655.273438 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27655.273438 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27655.273438 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27655.273438 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 10362 # number of writebacks -system.cpu.icache.writebacks::total 10362 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12288 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 12288 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 12288 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 12288 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 12288 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 12288 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 327540000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 327540000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 327540000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 327540000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 327540000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 327540000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000064 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000064 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000064 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26655.273438 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26655.273438 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26655.273438 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 26655.273438 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26655.273438 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 26655.273438 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3512.345683 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 19055 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5173 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 3.683549 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.192191 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1237.153491 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069433 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.037755 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.107188 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 5173 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 54 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 719 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 833 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3523 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.157867 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 198997 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 198997 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 2 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 10362 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 10362 # number of WritebackClean hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8691 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 8691 # number of ReadCleanReq hits -system.cpu.l2cache.demand_hits::cpu.inst 8691 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 8691 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 8691 # number of overall hits -system.cpu.l2cache.overall_hits::total 8691 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 1078 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1078 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3597 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 3597 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 498 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 498 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3597 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1576 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 5173 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3597 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1576 # number of overall misses -system.cpu.l2cache.overall_misses::total 5173 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 65220000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 65220000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 217646500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 217646500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30130000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 30130000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 217646500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 95350000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 312996500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 217646500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 95350000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 312996500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 2 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 2 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 10362 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 10362 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1078 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1078 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 12288 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 12288 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 498 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 498 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 12288 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1576 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 13864 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 12288 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1576 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 13864 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.292725 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.292725 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.292725 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.373125 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.292725 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.373125 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.927644 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.927644 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60507.784265 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60507.784265 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60502.008032 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60502.008032 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60507.784265 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60501.269036 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60505.799343 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60507.784265 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60501.269036 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60505.799343 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1078 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1078 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3597 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3597 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 498 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 498 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3597 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1576 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5173 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3597 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1576 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5173 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54440000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54440000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 181676500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 181676500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 25150000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 25150000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 181676500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 79590000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 261266500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 181676500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 79590000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 261266500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.292725 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.373125 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.373125 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.927644 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.927644 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50507.784265 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50507.784265 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50502.008032 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50502.008032 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50507.784265 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.269036 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50505.799343 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50507.784265 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.269036 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50505.799343 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 24228 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 10365 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 10362 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1078 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1078 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 12288 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 498 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 34938 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3154 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 38092 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1449600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 100992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1550592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 13864 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000072 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.008493 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 13863 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1 0.01% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 13864 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 22478000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 18432000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2364000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 5173 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 4095 # Transaction distribution -system.membus.trans_dist::ReadExReq 1078 # Transaction distribution -system.membus.trans_dist::ReadExResp 1078 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 4095 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10346 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10346 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 331072 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 5173 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5173 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5173 # Request fanout histogram -system.membus.reqLayer0.occupancy 5203000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 25865000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +sim_seconds 0.270605 +sim_ticks 270604702500 +final_tick 270604702500 +sim_freq 1000000000000 +host_inst_rate 850262 +host_op_rate 850263 +host_tick_rate 1189410021 +host_mem_usage 267428 +host_seconds 227.51 +sim_insts 193444518 +sim_ops 193444756 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 270604702500 +system.physmem.bytes_read::cpu.inst 230208 +system.physmem.bytes_read::cpu.data 100864 +system.physmem.bytes_read::total 331072 +system.physmem.bytes_inst_read::cpu.inst 230208 +system.physmem.bytes_inst_read::total 230208 +system.physmem.num_reads::cpu.inst 3597 +system.physmem.num_reads::cpu.data 1576 +system.physmem.num_reads::total 5173 +system.physmem.bw_read::cpu.inst 850717 +system.physmem.bw_read::cpu.data 372736 +system.physmem.bw_read::total 1223453 +system.physmem.bw_inst_read::cpu.inst 850717 +system.physmem.bw_inst_read::total 850717 +system.physmem.bw_total::cpu.inst 850717 +system.physmem.bw_total::cpu.data 372736 +system.physmem.bw_total::total 1223453 +system.pwrStateResidencyTicks::UNDEFINED 270604702500 +system.cpu_clk_domain.clock 500 +system.cpu.workload.numSyscalls 401 +system.cpu.pwrStateResidencyTicks::ON 270604702500 +system.cpu.numCycles 541209405 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 193444518 +system.cpu.committedOps 193444756 +system.cpu.num_int_alu_accesses 167974806 +system.cpu.num_fp_alu_accesses 1970372 +system.cpu.num_func_calls 1957920 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+system.cpu.l2cache.overall_mshr_misses::cpu.data 1576 +system.cpu.l2cache.overall_mshr_misses::total 5173 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54440000 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54440000 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 181676500 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 181676500 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 25150000 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 25150000 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 181676500 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 79590000 +system.cpu.l2cache.demand_mshr_miss_latency::total 261266500 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 181676500 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 79590000 +system.cpu.l2cache.overall_mshr_miss_latency::total 261266500 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.292725 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.292725 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.292725 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 +system.cpu.l2cache.demand_mshr_miss_rate::total 0.373125 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.292725 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 +system.cpu.l2cache.overall_mshr_miss_rate::total 0.373125 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.927644 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.927644 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50507.784265 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50507.784265 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50502.008032 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50502.008032 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50507.784265 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.269036 +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50505.799343 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50507.784265 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.269036 +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50505.799343 +system.cpu.toL2Bus.snoop_filter.tot_requests 24228 +system.cpu.toL2Bus.snoop_filter.hit_single_requests 10365 +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 270604702500 +system.cpu.toL2Bus.trans_dist::ReadResp 12786 +system.cpu.toL2Bus.trans_dist::WritebackDirty 2 +system.cpu.toL2Bus.trans_dist::WritebackClean 10362 +system.cpu.toL2Bus.trans_dist::ReadExReq 1078 +system.cpu.toL2Bus.trans_dist::ReadExResp 1078 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 12288 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 498 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 34938 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3154 +system.cpu.toL2Bus.pkt_count::total 38092 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1449600 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 100992 +system.cpu.toL2Bus.pkt_size::total 1550592 +system.cpu.toL2Bus.snoops 0 +system.cpu.toL2Bus.snoopTraffic 0 +system.cpu.toL2Bus.snoop_fanout::samples 13864 +system.cpu.toL2Bus.snoop_fanout::mean 0.000072 +system.cpu.toL2Bus.snoop_fanout::stdev 0.008493 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 13863 99.99% 99.99% +system.cpu.toL2Bus.snoop_fanout::1 1 0.01% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 1 +system.cpu.toL2Bus.snoop_fanout::total 13864 +system.cpu.toL2Bus.reqLayer0.occupancy 22478000 +system.cpu.toL2Bus.reqLayer0.utilization 0.0 +system.cpu.toL2Bus.respLayer0.occupancy 18432000 +system.cpu.toL2Bus.respLayer0.utilization 0.0 +system.cpu.toL2Bus.respLayer1.occupancy 2364000 +system.cpu.toL2Bus.respLayer1.utilization 0.0 +system.membus.snoop_filter.tot_requests 5173 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 270604702500 +system.membus.trans_dist::ReadResp 4095 +system.membus.trans_dist::ReadExReq 1078 +system.membus.trans_dist::ReadExResp 1078 +system.membus.trans_dist::ReadSharedReq 4095 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10346 +system.membus.pkt_count::total 10346 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 +system.membus.pkt_size::total 331072 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 5173 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 5173 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 5173 +system.membus.reqLayer0.occupancy 5203000 +system.membus.reqLayer0.utilization 0.0 +system.membus.respLayer1.occupancy 25865000 +system.membus.respLayer1.utilization 0.0 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/config.ini index f53bc72d5..f29a800e1 100644 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=atomic @@ -88,6 +89,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -167,7 +169,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=twolf smred cwd=build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic drivers= @@ -176,14 +178,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/twolf +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/twolf gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -207,6 +210,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -218,7 +222,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -226,6 +230,13 @@ width=16 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -234,6 +245,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -241,7 +253,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simerr b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simerr index aadc3d011..094173d40 100755 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simerr +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simerr @@ -1,2 +1,5 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simout index f40711d5c..c05a3785d 100755 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simout +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simout @@ -3,22 +3,19 @@ Redirecting stderr to build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-ato gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:35:23 -gem5 started Jul 21 2016 14:36:17 -gem5 executing on e108600-lin, pid 18540 -command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/70.twolf/x86/linux/simple-atomic +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:21 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87172 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/70.twolf/x86/linux/simple-atomic Couldn't unlink build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic/smred.sav Couldn't unlink build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 Standard Cell Placement and Global Routing Program Authors: Carl Sechen, Bill Swartz Yale University -info: Increasing stack size by one page. -info: Increasing stack size by one page. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 @@ -27,4 +24,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 131393279000 because target called exit() +122 123 124 Exiting @ tick 131393279000 because exiting with last active thread context diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt index fba8c2c09..78c52ebfd 100644 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -1,145 +1,145 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.131393 # Number of seconds simulated -sim_ticks 131393279000 # Number of ticks simulated -final_tick 131393279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1535006 # Simulator instruction rate (inst/s) -host_op_rate 2572810 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1527126307 # Simulator tick rate (ticks/s) -host_mem_usage 288212 # Number of bytes of host memory used -host_seconds 86.04 # Real time elapsed on the host -sim_insts 132071193 # Number of instructions simulated -sim_ops 221363385 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 131393279000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 1387954936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 310423752 # Number of bytes read from this memory -system.physmem.bytes_read::total 1698378688 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1387954936 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1387954936 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 99822191 # Number of bytes written to this memory -system.physmem.bytes_written::total 99822191 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 173494367 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 56682005 # Number of read requests responded to by this memory -system.physmem.num_reads::total 230176372 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 20515731 # Number of write requests responded to by this memory -system.physmem.num_writes::total 20515731 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 10563363260 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2362554267 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12925917527 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 10563363260 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 10563363260 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 759720678 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 759720678 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 10563363260 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3122274945 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13685638205 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 131393279000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 131393279000 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 131393279000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 131393279000 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 131393279000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 262786559 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 132071193 # Number of instructions committed -system.cpu.committedOps 221363385 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 219019986 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses -system.cpu.num_func_calls 1595632 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls -system.cpu.num_int_insts 219019986 # number of integer instructions -system.cpu.num_fp_insts 2162459 # number of float instructions -system.cpu.num_int_register_reads 519996939 # number of times the integer registers were read -system.cpu.num_int_register_writes 201355989 # number of times the integer registers were written -system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read -system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written -system.cpu.num_cc_register_reads 96962463 # number of times the CC registers were read -system.cpu.num_cc_register_writes 56242058 # number of times the CC registers were written -system.cpu.num_mem_refs 77165304 # number of memory refs -system.cpu.num_load_insts 56649587 # Number of load instructions -system.cpu.num_store_insts 20515717 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 262786558.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 12326938 # Number of branches fetched -system.cpu.op_class::No_OpClass 1176721 0.53% 0.53% # Class of executed instruction -system.cpu.op_class::IntAlu 134111833 60.58% 61.12% # Class of executed instruction -system.cpu.op_class::IntMult 772953 0.35% 61.47% # Class of executed instruction -system.cpu.op_class::IntDiv 7031501 3.18% 64.64% # Class of executed instruction -system.cpu.op_class::FloatAdd 1105073 0.50% 65.14% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::MemRead 55945136 25.27% 90.41% # Class of executed instruction -system.cpu.op_class::MemWrite 20410230 9.22% 99.63% # Class of executed instruction -system.cpu.op_class::FloatMemRead 704451 0.32% 99.95% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 105487 0.05% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 221363385 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 131393279000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 230176372 # Transaction distribution -system.membus.trans_dist::ReadResp 230176372 # Transaction distribution -system.membus.trans_dist::WriteReq 20515731 # Transaction distribution -system.membus.trans_dist::WriteResp 20515731 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 346988734 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.icache_port::total 346988734 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 154395472 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::total 154395472 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 501384206 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1387954936 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::total 1387954936 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 410245943 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::total 410245943 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1798200879 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 250692103 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 250692103 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 250692103 # Request fanout histogram +sim_seconds 0.131393 +sim_ticks 131393279000 +final_tick 131393279000 +sim_freq 1000000000000 +host_inst_rate 712720 +host_op_rate 1194584 +host_tick_rate 709061486 +host_mem_usage 300116 +host_seconds 185.31 +sim_insts 132071193 +sim_ops 221363385 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 131393279000 +system.physmem.bytes_read::cpu.inst 1387954936 +system.physmem.bytes_read::cpu.data 310423752 +system.physmem.bytes_read::total 1698378688 +system.physmem.bytes_inst_read::cpu.inst 1387954936 +system.physmem.bytes_inst_read::total 1387954936 +system.physmem.bytes_written::cpu.data 99822191 +system.physmem.bytes_written::total 99822191 +system.physmem.num_reads::cpu.inst 173494367 +system.physmem.num_reads::cpu.data 56682005 +system.physmem.num_reads::total 230176372 +system.physmem.num_writes::cpu.data 20515731 +system.physmem.num_writes::total 20515731 +system.physmem.bw_read::cpu.inst 10563363260 +system.physmem.bw_read::cpu.data 2362554267 +system.physmem.bw_read::total 12925917527 +system.physmem.bw_inst_read::cpu.inst 10563363260 +system.physmem.bw_inst_read::total 10563363260 +system.physmem.bw_write::cpu.data 759720678 +system.physmem.bw_write::total 759720678 +system.physmem.bw_total::cpu.inst 10563363260 +system.physmem.bw_total::cpu.data 3122274945 +system.physmem.bw_total::total 13685638205 +system.pwrStateResidencyTicks::UNDEFINED 131393279000 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 131393279000 +system.cpu.apic_clk_domain.clock 8000 +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 131393279000 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 131393279000 +system.cpu.workload.numSyscalls 400 +system.cpu.pwrStateResidencyTicks::ON 131393279000 +system.cpu.numCycles 262786559 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 132071193 +system.cpu.committedOps 221363385 +system.cpu.num_int_alu_accesses 219019986 +system.cpu.num_fp_alu_accesses 2162459 +system.cpu.num_func_calls 1595632 +system.cpu.num_conditional_control_insts 8268466 +system.cpu.num_int_insts 219019986 +system.cpu.num_fp_insts 2162459 +system.cpu.num_int_register_reads 519996939 +system.cpu.num_int_register_writes 201355989 +system.cpu.num_fp_register_reads 3037165 +system.cpu.num_fp_register_writes 1831403 +system.cpu.num_cc_register_reads 96962463 +system.cpu.num_cc_register_writes 56242058 +system.cpu.num_mem_refs 77165304 +system.cpu.num_load_insts 56649587 +system.cpu.num_store_insts 20515717 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 262786559 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 12326938 +system.cpu.op_class::No_OpClass 1176721 0.53% 0.53% +system.cpu.op_class::IntAlu 134111833 60.58% 61.12% +system.cpu.op_class::IntMult 772953 0.35% 61.47% +system.cpu.op_class::IntDiv 7031501 3.18% 64.64% +system.cpu.op_class::FloatAdd 1105073 0.50% 65.14% +system.cpu.op_class::FloatCmp 0 0.00% 65.14% +system.cpu.op_class::FloatCvt 0 0.00% 65.14% +system.cpu.op_class::FloatMult 0 0.00% 65.14% +system.cpu.op_class::FloatMultAcc 0 0.00% 65.14% +system.cpu.op_class::FloatDiv 0 0.00% 65.14% +system.cpu.op_class::FloatMisc 0 0.00% 65.14% +system.cpu.op_class::FloatSqrt 0 0.00% 65.14% +system.cpu.op_class::SimdAdd 0 0.00% 65.14% +system.cpu.op_class::SimdAddAcc 0 0.00% 65.14% +system.cpu.op_class::SimdAlu 0 0.00% 65.14% +system.cpu.op_class::SimdCmp 0 0.00% 65.14% +system.cpu.op_class::SimdCvt 0 0.00% 65.14% +system.cpu.op_class::SimdMisc 0 0.00% 65.14% +system.cpu.op_class::SimdMult 0 0.00% 65.14% +system.cpu.op_class::SimdMultAcc 0 0.00% 65.14% +system.cpu.op_class::SimdShift 0 0.00% 65.14% +system.cpu.op_class::SimdShiftAcc 0 0.00% 65.14% +system.cpu.op_class::SimdSqrt 0 0.00% 65.14% +system.cpu.op_class::SimdFloatAdd 0 0.00% 65.14% +system.cpu.op_class::SimdFloatAlu 0 0.00% 65.14% +system.cpu.op_class::SimdFloatCmp 0 0.00% 65.14% +system.cpu.op_class::SimdFloatCvt 0 0.00% 65.14% +system.cpu.op_class::SimdFloatDiv 0 0.00% 65.14% +system.cpu.op_class::SimdFloatMisc 0 0.00% 65.14% +system.cpu.op_class::SimdFloatMult 0 0.00% 65.14% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.14% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.14% +system.cpu.op_class::MemRead 55945136 25.27% 90.41% +system.cpu.op_class::MemWrite 20410230 9.22% 99.63% +system.cpu.op_class::FloatMemRead 704451 0.32% 99.95% +system.cpu.op_class::FloatMemWrite 105487 0.05% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 221363385 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 131393279000 +system.membus.trans_dist::ReadReq 230176372 +system.membus.trans_dist::ReadResp 230176372 +system.membus.trans_dist::WriteReq 20515731 +system.membus.trans_dist::WriteResp 20515731 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 346988734 +system.membus.pkt_count_system.cpu.icache_port::total 346988734 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 154395472 +system.membus.pkt_count_system.cpu.dcache_port::total 154395472 +system.membus.pkt_count::total 501384206 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1387954936 +system.membus.pkt_size_system.cpu.icache_port::total 1387954936 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 410245943 +system.membus.pkt_size_system.cpu.dcache_port::total 410245943 +system.membus.pkt_size::total 1798200879 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 250692103 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 250692103 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 250692103 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/config.ini index d04de745f..66b18ed6d 100644 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/config.ini +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=timing @@ -85,6 +86,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -100,14 +102,14 @@ eventq_index=0 [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -121,6 +123,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -133,15 +136,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dtb] type=X86TLB @@ -166,14 +170,14 @@ port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -187,6 +191,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -199,15 +204,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=X86LocalApic @@ -253,14 +259,14 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -274,6 +280,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -286,15 +293,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -330,7 +338,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=twolf smred cwd=build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing drivers= @@ -339,14 +347,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/twolf +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/twolf gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -370,6 +379,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -381,7 +391,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -389,6 +399,13 @@ width=16 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -397,6 +414,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -404,7 +422,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simerr b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simerr index aadc3d011..094173d40 100755 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simerr +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simerr @@ -1,2 +1,5 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simout b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simout index 6626953b4..cd651257e 100755 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simout @@ -3,22 +3,19 @@ Redirecting stderr to build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:35:23 -gem5 started Jul 21 2016 14:36:18 -gem5 executing on e108600-lin, pid 18557 -command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/70.twolf/x86/linux/simple-timing +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:21 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87178 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/70.twolf/x86/linux/simple-timing Couldn't unlink build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing/smred.sav Couldn't unlink build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 Standard Cell Placement and Global Routing Program Authors: Carl Sechen, Bill Swartz Yale University -info: Increasing stack size by one page. -info: Increasing stack size by one page. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 @@ -27,4 +24,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 250987138500 because target called exit() +122 123 124 Exiting @ tick 250991873500 because exiting with last active thread context diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index 466f07521..225096fb5 100644 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,531 +1,531 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.250992 # Number of seconds simulated -sim_ticks 250991873500 # Number of ticks simulated -final_tick 250991873500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1067110 # Simulator instruction rate (inst/s) -host_op_rate 1788574 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2027966293 # Simulator tick rate (ticks/s) -host_mem_usage 298984 # Number of bytes of host memory used -host_seconds 123.77 # Real time elapsed on the host -sim_insts 132071193 # Number of instructions simulated -sim_ops 221363385 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 121280 # Number of bytes read from this memory -system.physmem.bytes_read::total 303040 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 181760 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 181760 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2840 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1895 # Number of read requests responded to by this memory -system.physmem.num_reads::total 4735 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 724167 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 483203 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1207370 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 724167 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 724167 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 724167 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 483203 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1207370 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 250991873500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 501983747 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 132071193 # Number of instructions committed -system.cpu.committedOps 221363385 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 219019986 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses -system.cpu.num_func_calls 1595632 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls -system.cpu.num_int_insts 219019986 # number of integer instructions -system.cpu.num_fp_insts 2162459 # number of float instructions -system.cpu.num_int_register_reads 519996939 # number of times the integer registers were read -system.cpu.num_int_register_writes 201355989 # number of times the integer registers were written -system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read -system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written -system.cpu.num_cc_register_reads 96962463 # number of times the CC registers were read -system.cpu.num_cc_register_writes 56242058 # number of times the CC registers were written -system.cpu.num_mem_refs 77165304 # number of memory refs -system.cpu.num_load_insts 56649587 # Number of load instructions -system.cpu.num_store_insts 20515717 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 501983746.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 12326938 # Number of branches fetched -system.cpu.op_class::No_OpClass 1176721 0.53% 0.53% # Class of executed instruction -system.cpu.op_class::IntAlu 134111833 60.58% 61.12% # Class of executed instruction -system.cpu.op_class::IntMult 772953 0.35% 61.47% # Class of executed instruction -system.cpu.op_class::IntDiv 7031501 3.18% 64.64% # Class of executed instruction -system.cpu.op_class::FloatAdd 1105073 0.50% 65.14% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::MemRead 55945136 25.27% 90.41% # Class of executed instruction -system.cpu.op_class::MemWrite 20410230 9.22% 99.63% # Class of executed instruction -system.cpu.op_class::FloatMemRead 704451 0.32% 99.95% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 105487 0.05% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 221363385 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 41 # number of replacements -system.cpu.dcache.tags.tagsinuse 1363.408611 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1363.408611 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.332863 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.332863 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1864 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 472 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1328 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.455078 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 154397377 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 154397377 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 56681678 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20514153 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 77195831 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 77195831 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 77195831 # number of overall hits -system.cpu.dcache.overall_hits::total 77195831 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 327 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 327 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1578 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1578 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1905 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1905 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1905 # number of overall misses -system.cpu.dcache.overall_misses::total 1905 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 20253500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 20253500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 99266000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 99266000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 119519500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 119519500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 119519500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 119519500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 56682005 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 56682005 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 77197736 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 77197736 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 77197736 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 77197736 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000077 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61937.308869 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61937.308869 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62906.210393 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62906.210393 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62739.895013 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62739.895013 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62739.895013 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62739.895013 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 7 # number of writebacks -system.cpu.dcache.writebacks::total 7 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 327 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 327 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1578 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1578 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1905 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1905 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1905 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19926500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 19926500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 97688000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 97688000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 117614500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 117614500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 117614500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 117614500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000077 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60937.308869 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60937.308869 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61906.210393 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61906.210393 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61739.895013 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 61739.895013 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61739.895013 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 61739.895013 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 2836 # number of replacements -system.cpu.icache.tags.tagsinuse 1455.237724 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 173489673 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 36959.879207 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1455.237724 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.710565 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.710565 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1858 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 470 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 422 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 869 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.907227 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 346993428 # Number of tag accesses -system.cpu.icache.tags.data_accesses 346993428 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 173489673 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 173489673 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 173489673 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 173489673 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 173489673 # number of overall hits -system.cpu.icache.overall_hits::total 173489673 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4694 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4694 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4694 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4694 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4694 # number of overall misses -system.cpu.icache.overall_misses::total 4694 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 203072500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 203072500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 203072500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 203072500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 203072500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 203072500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 173494367 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 173494367 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 173494367 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 173494367 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 173494367 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 173494367 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000027 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000027 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000027 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000027 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43262.143161 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 43262.143161 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 43262.143161 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 43262.143161 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 43262.143161 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 43262.143161 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 2836 # number of writebacks -system.cpu.icache.writebacks::total 2836 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4694 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4694 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4694 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4694 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4694 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4694 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 198378500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 198378500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 198378500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 198378500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 198378500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 198378500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000027 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42262.143161 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42262.143161 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42262.143161 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 42262.143161 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42262.143161 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 42262.143161 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3195.628328 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4741 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4735 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.001267 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.901516 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1365.726812 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055844 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.041679 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.097523 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 4735 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 947 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3200 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.144501 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 80543 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 80543 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 7 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 7 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 2836 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 2836 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 3 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 3 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1854 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1854 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 7 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1854 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 10 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1864 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1854 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 10 # number of overall hits -system.cpu.l2cache.overall_hits::total 1864 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 1575 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1575 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2840 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2840 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 320 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 320 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2840 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1895 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 4735 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2840 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1895 # number of overall misses -system.cpu.l2cache.overall_misses::total 4735 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 95288500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 95288500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 171853000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 171853000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 19362000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 19362000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 171853000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 114650500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 286503500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 171853000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 114650500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 286503500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 7 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 7 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 2836 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 2836 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1578 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1578 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4694 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 4694 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 327 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 327 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 4694 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 6599 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 4694 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 6599 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.998099 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.998099 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.605028 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.605028 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.978593 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.978593 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.605028 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.994751 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.717533 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.605028 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.994751 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.717533 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.634921 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.634921 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60511.619718 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60511.619718 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60506.250000 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60506.250000 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60511.619718 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60501.583113 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60507.602957 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60511.619718 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60501.583113 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60507.602957 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1575 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1575 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2840 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2840 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 320 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 320 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2840 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1895 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 4735 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2840 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1895 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 4735 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 79538500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 79538500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 143453000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 143453000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16162000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16162000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 143453000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 95700500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 239153500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 143453000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 95700500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 239153500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.998099 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.998099 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.605028 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.978593 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.978593 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.717533 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.717533 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.634921 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.634921 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50511.619718 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50511.619718 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50506.250000 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50506.250000 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50511.619718 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.583113 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50507.602957 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50511.619718 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.583113 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50507.602957 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 9476 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2878 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 7 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 2836 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 34 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1578 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1578 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 4694 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 327 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12224 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3851 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16075 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 481920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 122368 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 604288 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 6599 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000152 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.012310 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 6598 99.98% 99.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1 0.02% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6599 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 7581000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7041000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2857500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 4735 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 3160 # Transaction distribution -system.membus.trans_dist::ReadExReq 1575 # Transaction distribution -system.membus.trans_dist::ReadExResp 1575 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3160 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 9470 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 303040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 303040 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 4735 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 4735 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request 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+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 122368 +system.cpu.toL2Bus.pkt_size::total 604288 +system.cpu.toL2Bus.snoops 0 +system.cpu.toL2Bus.snoopTraffic 0 +system.cpu.toL2Bus.snoop_fanout::samples 6599 +system.cpu.toL2Bus.snoop_fanout::mean 0.000152 +system.cpu.toL2Bus.snoop_fanout::stdev 0.012310 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 6598 99.98% 99.98% +system.cpu.toL2Bus.snoop_fanout::1 1 0.02% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 1 +system.cpu.toL2Bus.snoop_fanout::total 6599 +system.cpu.toL2Bus.reqLayer0.occupancy 7581000 +system.cpu.toL2Bus.reqLayer0.utilization 0.0 +system.cpu.toL2Bus.respLayer0.occupancy 7041000 +system.cpu.toL2Bus.respLayer0.utilization 0.0 +system.cpu.toL2Bus.respLayer1.occupancy 2857500 +system.cpu.toL2Bus.respLayer1.utilization 0.0 +system.membus.snoop_filter.tot_requests 4735 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 250991873500 +system.membus.trans_dist::ReadResp 3160 +system.membus.trans_dist::ReadExReq 1575 +system.membus.trans_dist::ReadExResp 1575 +system.membus.trans_dist::ReadSharedReq 3160 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 +system.membus.pkt_count::total 9470 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 303040 +system.membus.pkt_size::total 303040 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 4735 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 4735 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 4735 +system.membus.reqLayer0.occupancy 4771000 +system.membus.reqLayer0.utilization 0.0 +system.membus.respLayer1.occupancy 23675000 +system.membus.respLayer1.utilization 0.0 ---------- End Simulation Statistics ----------