From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 9 Jun 2020 11:08:12 +0000 (+0100)
Subject: add convenience variables in TestMemory
X-Git-Tag: div_pipeline~454
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f7e1491dc25588d7ccd72b6150449e664c940813;p=soc.git

add convenience variables in TestMemory
---

diff --git a/src/soc/experiment/testmem.py b/src/soc/experiment/testmem.py
index d4a13557..72a24ab7 100644
--- a/src/soc/experiment/testmem.py
+++ b/src/soc/experiment/testmem.py
@@ -5,6 +5,8 @@ class TestMemory(Elaboratable):
     def __init__(self, regwid, addrw):
         self.ddepth = 1 # regwid //8
         depth = (1<<addrw) // self.ddepth
+        self.depth = depth
+        self.regwid = regwid
         self.mem   = Memory(width=regwid, depth=depth,
                             init=range(0, depth*2, 2))
         self.rdport = self.mem.read_port() # not now transparent=False)