From: Sebastien Bourdeauducq Date: Fri, 26 Jul 2013 13:13:24 +0000 (+0200) Subject: Fragment -> _Fragment X-Git-Tag: 24jan2021_ls180~2099^2~443^2~13 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f7f19b78e4d3168eda675eea1a484cec81f6511f;p=litex.git Fragment -> _Fragment --- diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py index 86c12651..bfd6af73 100644 --- a/mibuild/generic_platform.py +++ b/mibuild/generic_platform.py @@ -2,6 +2,7 @@ from copy import copy import os, argparse from migen.fhdl.std import * +from migen.fhdl.structure import _Fragment from migen.genlib.record import Record from migen.fhdl import verilog @@ -194,7 +195,7 @@ class GenericPlatform: self.add_source(os.path.join(root, filename), language) def get_verilog(self, fragment, **kwargs): - if not isinstance(fragment, Fragment): + if not isinstance(fragment, _Fragment): fragment = fragment.get_fragment() # We may create a temporary clock/reset generator that would request pins. # Save the constraint manager state so that such pin requests disappear