From: Claire Xen <claire@clairexen.net>
Date: Fri, 17 Dec 2021 14:50:57 +0000 (+0100)
Subject: Update README.md
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f7f5135508cbb4b250b04433088d36b0c1a5a734;p=SymbiYosys.git

Update README.md
---

diff --git a/docs/examples/indinv/README.md b/docs/examples/indinv/README.md
index 8fb56d4..3ebc3c8 100644
--- a/docs/examples/indinv/README.md
+++ b/docs/examples/indinv/README.md
@@ -17,9 +17,12 @@ the following technique for proving and using inductive invariants.
 Consider the following circuit (stripped-down [example.sv](example.sv)):
 
 ```SystemVerilog
-module example(input logic clk, output reg [4:0] state); 
-	initial state = 27;
+module example(clk, state); 
+	input logic clk;
+	output logic [4:0] state = 27;
+
 	always_ff @(posedge clk) state <= (5'd 2 * state - 5'd 1) ^ (state & 5'd 7);
+
 	always_comb assert (state != 0);
 endmodule
 ```