From: Luke Kenneth Casson Leighton Date: Tue, 14 May 2019 04:27:09 +0000 (+0100) Subject: latch Function Unit registers based on "issue" signal X-Git-Tag: div_pipeline~2050 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f7fd88dfa6d3d7cafb655d7967a6d7fcd1d381de;p=soc.git latch Function Unit registers based on "issue" signal --- diff --git a/src/scoreboard/fn_unit.py b/src/scoreboard/fn_unit.py index a279c9f6..26a15194 100644 --- a/src/scoreboard/fn_unit.py +++ b/src/scoreboard/fn_unit.py @@ -139,9 +139,10 @@ class FnUnit(Elaboratable): dest_r = Signal(max=self.reg_width, reset_less=True) src1_r = Signal(max=self.reg_width, reset_less=True) src2_r = Signal(max=self.reg_width, reset_less=True) - latchregister(m, self.dest_i, dest_r, wr_l.qn) - latchregister(m, self.src1_i, src1_r, wr_l.qn) - latchregister(m, self.src2_i, src2_r, wr_l.qn) + # XXX latch based on *issue* rather than !latch (as in book) + latchregister(m, self.dest_i, dest_r, self.issue_i) #wr_l.qn) + latchregister(m, self.src1_i, src1_r, self.issue_i) #wr_l.qn) + latchregister(m, self.src2_i, src2_r, self.issue_i) #wr_l.qn) # dest decoder (use dest reg as input): write-pending out m.d.comb += dest_d.i.eq(dest_r)