From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 27 Oct 2022 00:55:23 +0000 (+0100)
Subject: endeavouring to implement shift-carry-dsld
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f7ffcca6532aaa5e35da22c9930380ca8701c755;p=openpower-isa.git

endeavouring to implement shift-carry-dsld
---

diff --git a/openpower/isa/svfixedarith.mdwn b/openpower/isa/svfixedarith.mdwn
index 2bd6864f..ad528604 100644
--- a/openpower/isa/svfixedarith.mdwn
+++ b/openpower/isa/svfixedarith.mdwn
@@ -55,13 +55,10 @@ VA2-Form
 
 Pseudo-code:
 
-    hi <- (RC)
-    lo <- (RA)
-    sh <- (RB)
-    n <- sh[58:63]
-    mask[0:63] <- MASK(n, 63)
-    v[0:63] <- (hi & mask) | (lo & ¬mask)
-    RT <- ROTL64(v, n)
+    n <- (RB)[58:63]
+    v <- ROTL128([0]*64 || (RA), n)
+    RT <- v[64:127] | ((RC) & MASK(n, 63))
+    RS <- v[0:63]
 
 Special Registers Altered:
 
diff --git a/src/openpower/decoder/helpers.py b/src/openpower/decoder/helpers.py
index ea3b659a..71d305df 100644
--- a/src/openpower/decoder/helpers.py
+++ b/src/openpower/decoder/helpers.py
@@ -843,6 +843,9 @@ class ISACallerHelper:
         value = rotl(value, bits, self.XLEN)
         return value
 
+    def ROTL128(self, value, bits):
+        return rotl(value, bits, self.XLEN*2)
+
     def ROTL64(self, value, bits):
         return rotl(value, bits, self.XLEN)